Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Fixed issue with Verilator hierarchical referencing by changing module names, moved run-imperas-linux to correct directory

Browse Source
This commit is contained in:
slmnemo 2024-04-12 21:58:20 -07:00
parent ce9ac4ae0b
commit 4b80457f3e
5 changed files with 15 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

0
sim/run-imperas-linux.sh → sim/questa/run-imperas-linux.sh
View File

2
src/uncore/uart_apb.sv
View File

@ -60,7 +60,7 @@ module uart_apb import cvw::*; #(parameter cvw_t P) (
else assign PRDATA = {Dout, Dout, Dout, Dout};
logic BAUDOUTb; // loop tx clock BAUDOUTb back to rx clock RCLK
uartPC16550D #(P.UART_PRESCALE) u(
uartPC16550D #(P.UART_PRESCALE) uartPC(
// Processor Interface
.PCLK, .PRESETn,
.A(entry), .Din,

2
src/uncore/uncore.sv
View File

@ -139,7 +139,7 @@ module uncore import cvw::*; #(parameter cvw_t P)(
end else begin : gpio
assign GPIOOUT = 0; assign GPIOEN = 0; assign GPIOIntr = 0;
end
if (P.UART_SUPPORTED == 1) begin : uart
if (P.UART_SUPPORTED == 1) begin : u
uart_apb #(P) uart(
.PCLK, .PRESETn, .PSEL(PSEL[3]), .PADDR(PADDR[2:0]), .PWDATA, .PSTRB, .PWRITE, .PENABLE,
.PRDATA(PRDATA[3]), .PREADY(PREADY[3]),

2
src/wally/wallypipelinedsoc.sv
View File

@ -79,7 +79,7 @@ module wallypipelinedsoc import cvw::*; #(parameter cvw_t P) (
);
// instantiate uncore if a bus interface exists
if (P.BUS_SUPPORTED) begin : uncore
if (P.BUS_SUPPORTED) begin : uc
uncore #(P) uncore(.HCLK, .HRESETn, .TIMECLK,
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT, .HSELEXTSDC,

24
testbench/testbench.sv
View File

@ -429,10 +429,10 @@ module testbench;
string romfilename, sdcfilename;
romfilename = {"../tests/custom/fpga-test-sdc/bin/fpga-test-sdc.memfile"};
sdcfilename = {"../testbench/sdc/ramdisk2.hex"};
//$readmemh(romfilename, dut.uncore.uncore.bootrom.bootrom.memory.ROM);
//$readmemh(romfilename, dut.uc.uncore.bootrom.bootrom.memory.ROM);
//$readmemh(sdcfilename, sdcard.sdcard.FLASHmem);
// shorten sdc timers for simulation
//dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
//dut.uc.uncore.sdc.SDC.LimitTimers = 1;
end
end
end else if (P.IROM_SUPPORTED) begin
@ -446,13 +446,13 @@ module testbench;
if (LoadMem) begin
if (TEST == "buildroot") begin
memFile = $fopen(bootmemfilename, "rb");
readResult = $fread(dut.uncore.uncore.bootrom.bootrom.memory.ROM, memFile);
readResult = $fread(dut.uc.uncore.bootrom.bootrom.memory.ROM, memFile);
$fclose(memFile);
memFile = $fopen(memfilename, "rb");
readResult = $fread(dut.uncore.uncore.ram.ram.memory.RAM, memFile);
readResult = $fread(dut.uc.uncore.ram.ram.memory.RAM, memFile);
$fclose(memFile);
end else
$readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
$readmemh(memfilename, dut.uc.uncore.ram.ram.memory.RAM);
if (TEST == "embench") $display("Read memfile %s", memfilename);
end
if (CopyRAM) begin
@ -461,7 +461,7 @@ module testbench;
EndIndex = (end_signature_addr >> LogXLEN) + 8;
BaseIndex = P.UNCORE_RAM_BASE >> LogXLEN;
for(ShadowIndex = StartIndex; ShadowIndex <= EndIndex; ShadowIndex++) begin
testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uncore.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex];
testbench.DCacheFlushFSM.ShadowRAM[ShadowIndex] = dut.uc.uncore.ram.ram.memory.RAM[ShadowIndex - BaseIndex];
end
end
end
@ -489,7 +489,7 @@ module testbench;
always @(posedge clk)
if (ResetMem) // program memory is sometimes reset (e.g. for CoreMark, which needs zeroed memory)
for (adrindex=0; adrindex<(P.UNCORE_RAM_RANGE>>1+(P.XLEN/32)); adrindex = adrindex+1)
dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = 0;
dut.uc.uncore.ram.ram.memory.RAM[adrindex] = 0;
////////////////////////////////////////////////////////////////////////////////
// Actual hardware
@ -583,9 +583,9 @@ module testbench;
if (P.UART_SUPPORTED) begin: uart_logger
always @(posedge clk) begin
if (TEST == "buildroot") begin
if (~dut.uncore.uncore.uart.uart.MEMWb & dut.uncore.uncore.uart.uart.u.A == 3'b000 & ~dut.uncore.uncore.uart.uart.u.DLAB) begin
if (~dut.uc.uncore.u.uart.MEMWb & dut.uc.uncore.u.uart.uartPC.A == 3'b000 & ~dut.uc.uncore.u.uart.uartPC.DLAB) begin
memFile = $fopen(uartoutfilename, "ab");
$fwrite(memFile, "%c", dut.uncore.uncore.uart.uart.u.Din);
$fwrite(memFile, "%c", dut.uc.uncore.u.uart.uartPC.Din);
$fclose(memFile);
end
end
@ -859,9 +859,9 @@ end
// **************************************
// ***** BUG BUG BUG make sure RT undoes this.
//if (P.DTIM_SUPPORTED) sig = testbench.dut.core.lsu.dtim.dtim.ram.RAM[testadrNoBase+i];
//else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
//if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uncore.uncore.ram.ram.memory.RAM[testadrNoBase+i];
//else if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uc.uncore.ram.ram.memory.RAM[testadrNoBase+i];
if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uc.uncore.ram.ram.memory.RAM[testadrNoBase+i];
//if (P.UNCORE_RAM_SUPPORTED) sig = testbench.dut.uc.uncore.ram.ram.memory.RAM[testadrNoBase+i];
//$display("signature[%h] = %h sig = %h", i, signature[i], sig);
//if (signature[i] !== sig & (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i])) begin
if (signature[i] !== testbench.DCacheFlushFSM.ShadowRAM[testadr+i]) begin