From 4b19f6d5421c1c058af8e0f358d730c03eb69770 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sat, 6 Apr 2024 08:22:39 -0700 Subject: [PATCH] testfloat running through wsim; moved lint, regression, wsim to bin directory so we don't need ./ --- {sim => bin}/lint-wally | 0 {sim => bin}/regression-wally | 8 +++ {sim => bin}/wsim | 28 ++++++--- sim/questa/testfloat-batch.do | 2 +- sim/questa/testfloat.do | 4 +- sim/questa/wally-batch.do | 16 ++--- sim/questa/wave-fpu.do | 58 +++++++++---------- .../{testbench-fp.sv => testbench_fp.sv} | 24 ++++---- testbench/{tests-fp.vh => tests_fp.vh} | 4 +- 9 files changed, 84 insertions(+), 60 deletions(-) rename {sim => bin}/lint-wally (100%) rename {sim => bin}/regression-wally (99%) rename {sim => bin}/wsim (63%) rename testbench/{testbench-fp.sv => testbench_fp.sv} (99%) rename testbench/{tests-fp.vh => tests_fp.vh} (99%) diff --git a/sim/lint-wally b/bin/lint-wally similarity index 100% rename from sim/lint-wally rename to bin/lint-wally diff --git a/sim/regression-wally b/bin/regression-wally similarity index 99% rename from sim/regression-wally rename to bin/regression-wally index b8d15632e..8819518e6 100755 --- a/sim/regression-wally +++ b/bin/regression-wally @@ -168,6 +168,10 @@ bpredtests = [ ["bpred_GSHARE_10_10_10_1_rv32gc", ["embench"], "configOptions", "-GPrintHPMCounters=1"] ] +################################## +# Data Types & Functions +################################## + TestCase = namedtuple("TestCase", ['name', 'variant', 'cmd', 'grepstr']) # name: the name of this test configuration (used in printing human-readable # output and picking logfile names) @@ -248,6 +252,10 @@ def run_test_case(config): print(" Check %s" % logname) return 1 +################################## +# Main body +################################## + regressionDir = os.path.dirname(os.path.abspath(__file__)) os.chdir(regressionDir) diff --git a/sim/wsim b/bin/wsim similarity index 63% rename from sim/wsim rename to bin/wsim index c11ee51f3..4fc1355f0 100755 --- a/sim/wsim +++ b/bin/wsim @@ -7,31 +7,43 @@ # example: wsim rv64gc arch64i # example: wsim rv64gc tests/riscof/work/riscv-arch-test/rv64i_m/I/src/ref/ref.elf # example: wsim rv32i arch32i -s verilator +# example: wsim fdqh_ieee_rv64gc add -t testbench_fp # run TestFloat # # SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 import argparse import os -# Read arguments +# Parse arguments parser = argparse.ArgumentParser() parser.add_argument("config", help="Configuration file") parser.add_argument("testsuite", help="Test suite or ELF file") parser.add_argument("--sim", "-s", help="Simulator", choices=["questa", "verilator", "vcs"], default="questa") +parser.add_argument("--tb", "-t", help="Testbench", choices=["testbench", "testbench_fp"], default="testbench") parser.add_argument("--gui", "-g", help="Simulate with GUI", action="store_true") parser.add_argument("--coverage", "-c", help="Code & Functional Coverage", action="store_true") args = parser.parse_args() print("Config: " + args.config + " tests " + args.testsuite + " sim " + args.sim + " gui " + str(args.gui)) +# Validate arguments +if (args.gui): + if (args.sim != "questa"): + print("GUI option only supported for Questa") + exit(1) + +if (args.coverage): + if (args.sim != "questa"): + print("Coverage option only available for Questa") + exit(1) + +# Launch selected simulator +cd = "cd $WALLY/sim/" +args.sim if (args.sim == "questa"): - cmd = "do wally-batch.do " + args.config + " " + args.testsuite + cmd = "do wally-batch.do " + args.config + " " + args.testsuite + " " + args.tb if (args.coverage): cmd += " -coverage" - os.system("cd $WALLY/sim/questa; vsim -c -do \"" + cmd + "\"") + os.system(cd + "; vsim -c -do \"" + cmd + "\"") elif (args.sim == "verilator"): - print("Running Verilator") + print("Running Verilator on %s %s", args.config, args.testsuite) elif (args.sim == "vcs"): - print("Running VCS") -else: - print("Unknown simulator") - exit(1) \ No newline at end of file + print("Running VCS on %s %s", args.config, args.testsuite) diff --git a/sim/questa/testfloat-batch.do b/sim/questa/testfloat-batch.do index f20867ddc..e266b7e0f 100644 --- a/sim/questa/testfloat-batch.do +++ b/sim/questa/testfloat-batch.do @@ -49,7 +49,7 @@ if {$WAV eq 0} { # Change TEST_SIZE to only test certain FP width # values are QP, DP, SP, HP or all for all tests -vopt +acc wkdir/work_${1}_${2}.testbenchfp -work wkdir/work_${1}_${2} -G TEST=$2 -G TEST_SIZE="all" -o testbenchopt +vopt +acc wkdir/work_${1}_${2}.testbench-fp -work wkdir/work_${1}_${2} -G TEST=$2 -G TEST_SIZE="all" -o testbenchopt vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 #-- Run the Simulation run -all diff --git a/sim/questa/testfloat.do b/sim/questa/testfloat.do index 796b540f3..dbfb85583 100644 --- a/sim/questa/testfloat.do +++ b/sim/questa/testfloat.do @@ -25,11 +25,11 @@ vlib work # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals # $num = the added words after the call -vlog +incdir+../config/deriv/$1 +incdir+../config/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-fp.sv ../src/fpu/*.sv ../src/fpu/*/*.sv ../src/generic/*.sv ../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 +vlog +incdir+../../config/deriv/$1 +incdir+../../config/$1 +incdir+../../config/shared ../../src/cvw.sv ../../testbench/testbench_fp.sv ../../src/fpu/*.sv ../../src/fpu/*/*.sv ../../src/generic/*.sv ../../src/generic/flop/*.sv -suppress 2583,7063,8607,2697 # Change TEST_SIZE to only test certain FP width # values are QP, DP, SP, HP or all for all tests -vsim -voptargs=+acc work.testbenchfp -GTEST=$2 -GTEST_SIZE="all" +vsim -voptargs=+acc work.testbench_fp -GTEST=$2 -GTEST_SIZE="all" # Set WAV variable to avoid having any output to wave (to limit disk space) quietly set WAV 1; diff --git a/sim/questa/wally-batch.do b/sim/questa/wally-batch.do index 5a69c906d..98ca5cba6 100644 --- a/sim/questa/wally-batch.do +++ b/sim/questa/wally-batch.do @@ -8,8 +8,8 @@ # # Takes 1:10 to run RV64IC tests using gui -# Usage: do wally-batch.do -# Example: do wally-batch.do rv32imc imperas-32i +# Usage: do wally-batch.do +# Example: do wally-batch.do rv64gc arch64i testbench # Use this wally-batch.do file to run this example. # Either bring up ModelSim and type the following at the "ModelSim>" prompt: @@ -22,8 +22,12 @@ onbreak {resume} set CFG ${1} set TESTSUITE ${2} +set TESTBENCH ${3} set WKDIR wkdir/${CFG}_${TESTSUITE} set WALLY $::env(WALLY) +set CONFIG ${WALLY}/config +set SRC ${WALLY}/src +set TB ${WALLY}/testbench # create library if [file exists ${WKDIR}] { @@ -68,15 +72,11 @@ if {$argc >= 3} { # "Extra checking for conflicts with always_comb done at vopt time" # because vsim will run vopt -set CONFIG ${WALLY}/config -set SRC ${WALLY}/src -set TB ${WALLY}/testbench - -vlog -lint -work ${WKDIR} +incdir+${CONFIG}/$1 +incdir+${CONFIG}/deriv/$1 +incdir+${CONFIG}/shared ${SRC}/cvw.sv ${TB}/testbench.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 +vlog -lint -work ${WKDIR} +incdir+${CONFIG}/$1 +incdir+${CONFIG}/deriv/$1 +incdir+${CONFIG}/shared ${SRC}/cvw.sv ${TB}/${TESTBENCH}.sv ${TB}/common/*.sv ${SRC}/*/*.sv ${SRC}/*/*/*.sv -suppress 2583 -suppress 7063,2596,13286 # start and run simulation # remove +acc flag for faster sim during regressions if there is no need to access internal signals -vopt wkdir/${CFG}_${TESTSUITE}.testbench -work ${WKDIR} -G TEST=$2 ${configOptions} -o testbenchopt ${CoverageVoptArg} +vopt wkdir/${CFG}_${TESTSUITE}.${TESTBENCH} -work ${WKDIR} -G TEST=$2 ${configOptions} -o testbenchopt ${CoverageVoptArg} vsim -lib ${WKDIR} testbenchopt -fatal 7 -suppress 3829 ${CoverageVsimArg} # vsim -lib wkdir/work_${1}_${2} testbenchopt -fatal 7 -suppress 3829 diff --git a/sim/questa/wave-fpu.do b/sim/questa/wave-fpu.do index 08b6b3378..f4da1e8a2 100644 --- a/sim/questa/wave-fpu.do +++ b/sim/questa/wave-fpu.do @@ -1,30 +1,30 @@ -add wave -noupdate /testbenchfp/clk -add wave -noupdate -radix decimal /testbenchfp/VectorNum -add wave -noupdate /testbenchfp/FrmNum -add wave -noupdate /testbenchfp/X -add wave -noupdate /testbenchfp/Y -add wave -noupdate /testbenchfp/Z -add wave -noupdate /testbenchfp/Res -add wave -noupdate /testbenchfp/Ans -add wave -noupdate /testbenchfp/reset -add wave -noupdate /testbenchfp/DivStart -add wave -noupdate /testbenchfp/FDivBusyE -add wave -noupdate /testbenchfp/CheckNow -add wave -noupdate /testbenchfp/DivDone -add wave -noupdate /testbenchfp/ResMatch -add wave -noupdate /testbenchfp/FlagMatch -add wave -noupdate /testbenchfp/CheckNow -add wave -noupdate /testbenchfp/NaNGood -add wave -group {PostProc} -noupdate /testbenchfp/postprocess/* -add wave -group {PostProc} -noupdate /testbenchfp/postprocess/specialcase/* -add wave -group {PostProc} -noupdate /testbenchfp/postprocess/flags/* -add wave -group {PostProc} -noupdate /testbenchfp/postprocess/normshift/* -add wave -group {PostProc} -noupdate /testbenchfp/postprocess/shiftcorrection/* -add wave -group {PostProc} -noupdate /testbenchfp/postprocess/resultsign/* -add wave -group {PostProc} -noupdate /testbenchfp/postprocess/round/* -add wave -group {PostProc} -noupdate /testbenchfp/postprocess/fmashiftcalc/* -add wave -group {PostProc} -noupdate /testbenchfp/postprocess/divshiftcalc/* -add wave -group {PostProc} -noupdate /testbenchfp/postprocess/cvtshiftcalc/* -add wave -group {Testbench} -noupdate /testbenchfp/* -add wave -group {Testbench} -noupdate /testbenchfp/readvectors/* +add wave -noupdate /testbench_fp/clk +add wave -noupdate -radix decimal /testbench_fp/VectorNum +add wave -noupdate /testbench_fp/FrmNum +add wave -noupdate /testbench_fp/X +add wave -noupdate /testbench_fp/Y +add wave -noupdate /testbench_fp/Z +add wave -noupdate /testbench_fp/Res +add wave -noupdate /testbench_fp/Ans +add wave -noupdate /testbench_fp/reset +add wave -noupdate /testbench_fp/DivStart +add wave -noupdate /testbench_fp/FDivBusyE +add wave -noupdate /testbench_fp/CheckNow +add wave -noupdate /testbench_fp/DivDone +add wave -noupdate /testbench_fp/ResMatch +add wave -noupdate /testbench_fp/FlagMatch +add wave -noupdate /testbench_fp/CheckNow +add wave -noupdate /testbench_fp/NaNGood +add wave -group {PostProc} -noupdate /testbench_fp/postprocess/* +add wave -group {PostProc} -noupdate /testbench_fp/postprocess/specialcase/* +add wave -group {PostProc} -noupdate /testbench_fp/postprocess/flags/* +add wave -group {PostProc} -noupdate /testbench_fp/postprocess/normshift/* +add wave -group {PostProc} -noupdate /testbench_fp/postprocess/shiftcorrection/* +add wave -group {PostProc} -noupdate /testbench_fp/postprocess/resultsign/* +add wave -group {PostProc} -noupdate /testbench_fp/postprocess/round/* +add wave -group {PostProc} -noupdate /testbench_fp/postprocess/fmashiftcalc/* +add wave -group {PostProc} -noupdate /testbench_fp/postprocess/divshiftcalc/* +add wave -group {PostProc} -noupdate /testbench_fp/postprocess/cvtshiftcalc/* +add wave -group {Testbench} -noupdate /testbench_fp/* +add wave -group {Testbench} -noupdate /testbench_fp/readvectors/* diff --git a/testbench/testbench-fp.sv b/testbench/testbench_fp.sv similarity index 99% rename from testbench/testbench-fp.sv rename to testbench/testbench_fp.sv index 474b54a89..21772cc48 100644 --- a/testbench/testbench-fp.sv +++ b/testbench/testbench_fp.sv @@ -23,15 +23,17 @@ //////////////////////////////////////////////////////////////////////////////////////////////// `include "config.vh" -`include "tests-fp.vh" +`include "tests_fp.vh" import cvw::*; -module testbenchfp; +module testbench_fp; // Two parameters TEST, TEST_SIZE used with testfloat.do in sim dir // to run specific precisions (e.g., quad or all) - parameter string TEST="none"; - parameter string TEST_SIZE="none"; +// parameter string TEST="none"; +// parameter string TEST_SIZE="none"; + parameter string TEST="add"; + parameter string TEST_SIZE="all"; `include "parameter-defs.vh" @@ -662,12 +664,14 @@ module testbenchfp; TestNum = 0; end - // set a the signals for all tests - always_comb UnitVal = Unit[TestNum]; - always_comb FmtVal = Fmt[TestNum]; - always_comb OpCtrlVal = OpCtrl[OpCtrlNum]; - always_comb WriteIntVal = WriteInt[OpCtrlNum]; - always_comb FrmVal = Frm[FrmNum]; + // set the signals for all tests + always_ff @(posedge clk) begin + UnitVal = Unit[TestNum]; + FmtVal = Fmt[TestNum]; + OpCtrlVal = OpCtrl[OpCtrlNum]; + WriteIntVal = WriteInt[OpCtrlNum]; + FrmVal = Frm[FrmNum]; + end // modify the format signal if only 2 percisions supported // - 1 for the larger precision diff --git a/testbench/tests-fp.vh b/testbench/tests_fp.vh similarity index 99% rename from testbench/tests-fp.vh rename to testbench/tests_fp.vh index e29cc8447..4c0e9cda5 100644 --- a/testbench/tests-fp.vh +++ b/testbench/tests_fp.vh @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// tests0fo.vh +// tests_fp.vh // // Written: Katherine Parry 2022 // Modified: @@ -24,7 +24,7 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`define PATH "../tests/fp/vectors/" +`define PATH "../../tests/fp/vectors/" `define ADD_OPCTRL 3'b110 `define MUL_OPCTRL 3'b100 `define SUB_OPCTRL 3'b111