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https://github.com/openhwgroup/cvw
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Cache cleanup write enables.
This commit is contained in:
Ross Thompson
parent
c2907ec0f4
commit
4a7ebb3757
46
pipelined/src/cache/cache.sv
vendored
46
pipelined/src/cache/cache.sv
vendored
@ -62,7 +62,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
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localparam LINEBYTELEN = LINELEN/8;
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localparam OFFSETLEN = $clog2(LINEBYTELEN);
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localparam SETLEN = $clog2(NUMLINES);
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localparam SETTOP = SETLEN+OFFSETLEN;
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localparam SETTOP = SETLEN+OFFSETLEN;
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localparam TAGLEN = `PA_BITS - SETTOP;
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localparam WORDSPERLINE = LINELEN/`XLEN;
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localparam LOGWPL = $clog2(WORDSPERLINE);
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@ -77,12 +77,9 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
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logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0];
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logic [NUMWAYS-1:0] WayHit;
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logic CacheHit;
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logic [WORDSPERLINE-1:0] SRAMWordEnable;
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logic SRAMWordWriteEnable;
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logic SRAMLineWriteEnable;
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logic FSMWordWriteEn;
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logic FSMLineWriteEn;
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logic [NUMWAYS-1:0] SRAMLineWayWriteEnable;
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logic [NUMWAYS-1:0] SRAMWayWriteEnable;
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logic [NUMWAYS-1:0] SRAMWordWayWriteEnable;
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logic [NUMWAYS-1:0] VictimWay;
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logic [NUMWAYS-1:0] VictimDirtyWay;
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logic VictimDirty;
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@ -106,7 +103,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
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logic [NUMWAYS-1:0] WayHitSaved, WayHitRaw;
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logic [LINELEN-1:0] ReadDataLineRaw, ReadDataLineSaved;
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logic [NUMWAYS-1:0] SelectedWay;
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logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay;
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logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay;
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logic [NUMWAYS-1:0] WriteWordWayEn, WriteLineWayEn;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Read Path
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@ -121,9 +119,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
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// Array of cache ways, along with victim, hit, dirty, and read merging logic
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cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0](
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.clk, .reset, .RAdr, .PAdr,
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.SRAMWayWriteEnable,
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.SRAMWordEnable,
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.TagWriteEnable(SRAMLineWayWriteEnable),
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.WriteWordEn(WriteWordWayEn),
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.WriteLineEn(WriteLineWayEn),
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.WriteData(SRAMWriteData),
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.SetValid(SetValidWay), .ClearValid(ClearValidWay), .SetDirty(SetDirtyWay), .ClearDirty(ClearDirtyWay),
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.SelEvict, .Victim(VictimWay), .Flush(FlushWay),
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@ -153,22 +150,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
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end else assign WayHit = WayHitRaw;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Write Path: Write Enables
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// Write Path: Write data and address. Muxes between writes from bus and writes from CPU.
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/////////////////////////////////////////////////////////////////////////////////////////////
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// *** Ross considering restructuring
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// move decoder and wordwritenable into cacheway.
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onehotdecoder #(LOGWPL) adrdec(
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.bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded));
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assign SRAMWordEnable = SRAMLineWriteEnable ? '1 : MemPAdrDecoded; // OR
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assign SRAMLineWayWriteEnable = SRAMLineWriteEnable ? VictimWay : '0; // AND
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assign SRAMWordWayWriteEnable = SRAMWordWriteEnable ? WayHit : '0; // AND
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mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWayWriteEnable), .d1(VictimWay),
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.s(SRAMLineWriteEnable), .y(SRAMWayWriteEnable));
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mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}),
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.d1(CacheMemWriteData), .s(SRAMLineWriteEnable), .y(SRAMWriteData));
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.d1(CacheMemWriteData), .s(FSMLineWriteEn), .y(SRAMWriteData));
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mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
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.d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}),
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.d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}),
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@ -192,11 +178,17 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
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assign FlushWayFlag = FlushWay[NUMWAYS-1];
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assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]};
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assign SelectedWay = SelFlush ? FlushWay : (SRAMLineWriteEnable ? VictimWay : WayHit);
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Write Path: Write Enables
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/////////////////////////////////////////////////////////////////////////////////////////////
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assign SelectedWay = SelFlush ? FlushWay : (FSMLineWriteEn ? VictimWay : WayHit);
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assign SetValidWay = SetValid ? SelectedWay : '0;
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assign ClearValidWay = ClearValid ? SelectedWay : '0;
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assign SetDirtyWay = SetDirty ? SelectedWay : '0;
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assign ClearDirtyWay = ClearDirty ? SelectedWay : '0;
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assign ClearDirtyWay = ClearDirty ? SelectedWay : '0;
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assign WriteWordWayEn = FSMWordWriteEn ? SelectedWay : '0;
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assign WriteLineWayEn = FSMLineWriteEn ? SelectedWay : '0;
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/////////////////////////////////////////////////////////////////////////////////////////////
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@ -207,8 +199,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) (
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.RW, .Atomic, .CPUBusy, .IgnoreRequest,
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.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted,
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.CacheMiss, .CacheAccess, .SelAdr, .SetValid,
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.ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnable,
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.SRAMLineWriteEnable, .SelEvict, .SelFlush,
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.ClearValid, .SetDirty, .ClearDirty, .FSMWordWriteEn,
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.FSMLineWriteEn, .SelEvict, .SelFlush,
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.FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst,
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.FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache,
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.save, .restore,
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19
pipelined/src/cache/cachefsm.sv
vendored
19
pipelined/src/cache/cachefsm.sv
vendored
@ -65,8 +65,8 @@ module cachefsm
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output logic ClearValid,
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output logic SetDirty,
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output logic ClearDirty,
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output logic SRAMWordWriteEnable,
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output logic SRAMLineWriteEnable,
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output logic FSMWordWriteEn,
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output logic FSMLineWriteEn,
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output logic SelEvict,
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output logic LRUWriteEn,
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output logic SelFlush,
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@ -174,6 +174,7 @@ module cachefsm
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endcase
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end
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// com back to CPU
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assign CacheCommitted = CurrState != STATE_READY;
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assign CacheStall = (CurrState == STATE_READY & (DoFlush | DoAMOMiss | DoReadMiss | DoWriteMiss)) |
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(CurrState == STATE_MISS_FETCH_WDV) |
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@ -186,6 +187,7 @@ module cachefsm
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(CurrState == STATE_FLUSH_INCR) |
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(CurrState == STATE_FLUSH_WRITE_BACK) |
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(CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag));
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// write enables internal to cache
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assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE;
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assign ClearValid = '0;
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assign SetDirty = (CurrState == STATE_READY & DoAMO) |
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@ -194,14 +196,15 @@ module cachefsm
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(CurrState == STATE_MISS_WRITE_WORD);
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assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE) |
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(CurrState == STATE_FLUSH_CLEAR_DIRTY);
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assign SRAMWordWriteEnable = (CurrState == STATE_READY & (DoAMOHit | DoWriteHit)) |
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(CurrState == STATE_MISS_READ_WORD_DELAY & DoAMO) |
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(CurrState == STATE_MISS_WRITE_WORD);
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assign SRAMLineWriteEnable = (CurrState == STATE_MISS_WRITE_CACHE_LINE);
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assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY);
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assign FSMWordWriteEn = (CurrState == STATE_READY & (DoAMOHit | DoWriteHit)) |
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(CurrState == STATE_MISS_READ_WORD_DELAY & DoAMO) |
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(CurrState == STATE_MISS_WRITE_WORD);
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assign FSMLineWriteEn = (CurrState == STATE_MISS_WRITE_CACHE_LINE);
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assign LRUWriteEn = (CurrState == STATE_READY & (DoAMOHit | DoReadHit | DoWriteHit)) |
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(CurrState == STATE_MISS_READ_WORD_DELAY) |
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(CurrState == STATE_MISS_WRITE_WORD);
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// Flush and eviction controls
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assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY);
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assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) |
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(CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK) |
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(CurrState == STATE_FLUSH_CLEAR_DIRTY);
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@ -211,9 +214,11 @@ module cachefsm
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(CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag));
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assign FlushAdrCntRst = (CurrState == STATE_READY & DoFlush);
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assign FlushWayCntRst = (CurrState == STATE_READY & DoFlush) | (CurrState == STATE_FLUSH_INCR);
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// Bus interface controls
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assign CacheFetchLine = (CurrState == STATE_READY & (DoAMOMiss | DoWriteMiss | DoReadMiss));
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assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_DONE & VictimDirty) |
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(CurrState == STATE_FLUSH_CHECK & VictimDirty);
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// handle cpu stall.
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assign restore = ((CurrState == STATE_CPU_BUSY) | (CurrState == STATE_CPU_BUSY_FINISH_AMO)) & ~`REPLAY;
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assign save = ((CurrState == STATE_READY & (DoAMOHit | DoReadHit | DoWriteHit) & CPUBusy) |
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(CurrState == STATE_MISS_READ_WORD_DELAY & (DoAMO | DoRead) & CPUBusy) |
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30
pipelined/src/cache/cacheway.sv
vendored
30
pipelined/src/cache/cacheway.sv
vendored
@ -37,9 +37,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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input logic [$clog2(NUMLINES)-1:0] RAdr,
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input logic [`PA_BITS-1:0] PAdr,
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input logic SRAMWayWriteEnable,
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input logic [LINELEN/`XLEN-1:0] SRAMWordEnable,
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input logic TagWriteEnable,
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input logic WriteWordEn,
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input logic WriteLineEn,
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input logic [LINELEN-1:0] WriteData,
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input logic SetValid,
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input logic ClearValid,
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@ -56,6 +55,10 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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output logic VictimDirty,
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output logic [TAGLEN-1:0] VictimTag);
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localparam WORDSPERLINE = LINELEN/`XLEN;
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localparam LOGWPL = $clog2(WORDSPERLINE);
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localparam LOGXLENBYTES = $clog2(`XLEN/8);
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logic [NUMLINES-1:0] ValidBits;
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logic [NUMLINES-1:0] DirtyBits;
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logic [LINELEN-1:0] ReadDataLine;
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@ -68,7 +71,18 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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logic [$clog2(NUMLINES)-1:0] RAdrD;
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logic SetValidD, ClearValidD;
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logic SetDirtyD, ClearDirtyD;
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logic SRAMWayWriteEnableD;
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logic [2**LOGWPL-1:0] MemPAdrDecoded;
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logic [LINELEN/`XLEN-1:0] SelectedWriteWordEn;
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Write Enable demux
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/////////////////////////////////////////////////////////////////////////////////////////////
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onehotdecoder #(LOGWPL) adrdec(
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.bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded));
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// If writing the whole line set all write enables to 1, else only set the correct word.
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assign SelectedWriteWordEn = WriteLineEn ? '1 : WriteWordEn ? MemPAdrDecoded : '0; // OR-AND
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/////////////////////////////////////////////////////////////////////////////////////////////
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// Tag Array
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@ -76,7 +90,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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sram1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk(clk),
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.Adr(RAdr), .ReadData(ReadTag),
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.WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(TagWriteEnable));
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.WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(WriteLineEn));
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// AND portion of distributed tag multiplexer
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assign SelTag = SelFlush ? Flush : Victim;
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@ -93,7 +107,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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sram1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk(clk), .Adr(RAdr),
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.ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ),
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.WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]),
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.WriteEnable(SRAMWayWriteEnable & SRAMWordEnable[words]));
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.WriteEnable(SelectedWriteWordEn[words]));
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end
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// AND portion of distributed read multiplexers
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@ -112,8 +126,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26,
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end
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// *** consider revisiting whether these delays are the best option?
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flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD);
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flop #(3) ValidCtrlDelayReg(clk, {SetValid, ClearValid, SRAMWayWriteEnable},
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{SetValidD, ClearValidD, SRAMWayWriteEnableD});
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flop #(2) ValidCtrlDelayReg(clk, {SetValid, ClearValid},
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{SetValidD, ClearValidD});
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assign Valid = ValidBits[RAdrD];
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/////////////////////////////////////////////////////////////////////////////////////////////
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