update config to derive MISA from macros

- Remove C_SUPPORTED and update decompress unit based on Zc* extensions
- Derive A_SUPPORTED from A subextensions
- Derive B_SUPPORTED from B subextensions
- Derive C_SUPPORTED from C subextensions

config/derivlist.txt

@@ -100,19 +100,23 @@ deriv syn_sram_rv64gc_noPriv syn_sram_rv64gc_pmp0
 ZICSR_SUPPORTED     0
 
 deriv syn_rv64gc_noFPU syn_rv64gc_noPriv
-MISA                (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+F_SUPPORTED         0
+D_SUPPORTED         0
 deriv syn_sram_rv64gc_noFPU syn_sram_rv64gc_noPriv
-MISA                (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+F_SUPPORTED         0
+D_SUPPORTED         0
 
 deriv syn_rv64gc_noMulDiv syn_rv64gc_noFPU
-MISA                (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0)
+M_SUPPORTED         0
 deriv syn_sram_rv64gc_noMulDiv syn_sram_rv64gc_noFPU
-MISA                (32'h00000104 | 1 << 18 | 1 << 20 | 1 << 0)
+M_SUPPORTED         0
 
 deriv syn_rv64gc_noAtomic syn_rv64gc_noMulDiv
-MISA                (32'h00000104 | 1 << 18 | 1 << 20)
+ZAAMO_SUPPORTED     0
+ZALRSC_SUPPORTED    0
 deriv syn_sram_rv64gc_noAtomic syn_sram_rv64gc_noMulDiv
-MISA                (32'h00000104 | 1 << 18 | 1 << 20)
+ZAAMO_SUPPORTED     0
+ZALRSC_SUPPORTED    0
 
 # Divider variants to check logical correctness
 
@@ -140,7 +144,6 @@ deriv div_4_2_rv32gc    rv32gc
 RADIX               32'd4
 IDIV_ON_FPU         0
 DIVCOPIES           32'd2
-IDIV_ON_FPU         0
 
 deriv div_4_4_rv32gc    rv32gc
 RADIX               32'd4
@@ -407,7 +410,8 @@ ZICBOM_SUPPORTED    0
 ZICBOZ_SUPPORTED    0
 SVPBMT_SUPPORTED    0
 SVNAPOT_SUPPORTED   0
-MISA                (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12)
+ZAAMO_SUPPORTED     0
+ZALRSC_SUPPORTED    0
 
 deriv nocache_rv64gc rv64gc
 ICACHE_SUPPORTED    0
@@ -417,7 +421,8 @@ ZICBOM_SUPPORTED    0
 ZICBOZ_SUPPORTED    0
 SVPBMT_SUPPORTED    0
 SVNAPOT_SUPPORTED   0
-MISA                (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12)
+ZAAMO_SUPPORTED     0
+ZALRSC_SUPPORTED    0
 
 deriv way_1_4096_512_rv32gc rv32gc
 DCACHE_NUMWAYS      32'd1
@@ -512,69 +517,61 @@ deriv nobigendian_rv64gc rv64gc
 BIGENDIAN_SUPPORTED 0
 
 deriv zaamo_rv32gc rv32gc
-MISA    (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 <<3 | 1 << 5);
+ZALRSC_SUPPORTED    0
-ZAAMO_SUPPORTED 1
 
 deriv zalrsc_rv32gc rv32gc
-MISA    (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 <<3 | 1 << 5);
+ZAAMO_SUPPORTED     0
-ZALRSC_SUPPORTED 1
 
 deriv zaamo_rv64gc rv64gc
-MISA    (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 <<3 | 1 << 5);
+ZALRSC_SUPPORTED    0
-ZAAMO_SUPPORTED 1
 
 deriv zalrsc_rv64gc rv64gc
-MISA    (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 <<3 | 1 << 5);
+ZAAMO_SUPPORTED     0
-ZALRSC_SUPPORTED 1
 
 # Floating-point modes supported
 
 deriv f_rv32gc rv32gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv fh_rv32gc rv32gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fd_rv32gc rv32gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fdh_rv32gc rv32gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdq_rv32gc rv32gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   0
 
 deriv fdqh_rv32gc rv32gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   1
 
 deriv f_rv64gc rv64gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv fh_rv64gc rv64gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fd_rv64gc rv64gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fdh_rv64gc rv64gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdq_rv64gc rv64gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   0
 
 deriv fdqh_rv64gc rv64gc
-MISA    (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 16 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     1
 ZFH_SUPPORTED   1
 
 # IEEE compatible variants for TestFloat
@@ -619,302 +616,278 @@ IEEE754     1
 
 #### F_only, RK variable
 deriv f_div_2_1_rv32gc    div_2_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_2_2_rv32gc    div_2_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_2_4_rv32gc    div_2_4_rv32gc
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_4_1_rv32gc    div_4_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_4_2_rv32gc    div_4_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_4_4_rv32gc    div_4_4_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_2_1_rv64gc    div_2_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_2_2_rv64gc    div_2_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_2_4_rv64gc    div_2_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_4_1_rv64gc    div_4_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_4_2_rv64gc    div_4_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv f_div_4_4_rv64gc    div_4_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 
 #### FH_only, RK variable
 deriv fh_div_2_1_rv32gc    div_2_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_2_2_rv32gc    div_2_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_2_4_rv32gc    div_2_4_rv32gc
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_4_1_rv32gc    div_4_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_4_2_rv32gc    div_4_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_4_4_rv32gc    div_4_4_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_2_1_rv64gc    div_2_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_2_2_rv64gc    div_2_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_2_4_rv64gc    div_2_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_4_1_rv64gc    div_4_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_4_2_rv64gc    div_4_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fh_div_4_4_rv64gc    div_4_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+D_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 # FD only , rk variable
 
 deriv fd_div_2_1_rv32gc    div_2_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_2_2_rv32gc    div_2_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_2_4_rv32gc    div_2_4_rv32gc
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_4_1_rv32gc    div_4_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_4_2_rv32gc    div_4_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_4_4_rv32gc    div_4_4_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_2_1_rv64gc    div_2_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_2_2_rv64gc    div_2_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_2_4_rv64gc    div_2_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_4_1_rv64gc    div_4_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_4_2_rv64gc    div_4_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 deriv fd_div_4_4_rv64gc    div_4_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   0
 
 
 # FDH only , rk variable
 
 deriv fdh_div_2_1_rv32gc    div_2_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_2_2_rv32gc    div_2_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_2_4_rv32gc    div_2_4_rv32gc
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_4_1_rv32gc    div_4_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_4_2_rv32gc    div_4_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_4_4_rv32gc    div_4_4_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_2_1_rv64gc    div_2_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_2_2_rv64gc    div_2_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_2_4_rv64gc    div_2_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_4_1_rv64gc    div_4_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_4_2_rv64gc    div_4_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 deriv fdh_div_4_4_rv64gc    div_4_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
 ZFH_SUPPORTED   1
 
 # FDQ only , rk variable
 
 deriv fdq_div_2_1_rv32gc    div_2_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv fdq_div_2_2_rv32gc    div_2_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv fdq_div_2_4_rv32gc    div_2_4_rv32gc
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv fdq_div_4_1_rv32gc    div_4_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv fdq_div_4_2_rv32gc    div_4_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv fdq_div_4_4_rv32gc    div_4_4_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv fdq_div_2_1_rv64gc    div_2_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv fdq_div_2_2_rv64gc    div_2_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv fdq_div_2_4_rv64gc    div_2_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv fdq_div_4_1_rv64gc    div_4_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv fdq_div_4_2_rv64gc    div_4_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 deriv fdq_div_4_4_rv64gc    div_4_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   0
 
 # FDQH only , rk variable
 
 deriv fdqh_div_2_1_rv32gc    div_2_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_2_2_rv32gc    div_2_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_2_4_rv32gc    div_2_4_rv32gc
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_4_1_rv32gc    div_4_1_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_4_2_rv32gc    div_4_2_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_4_4_rv32gc    div_4_4_rv32gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_2_1_rv64gc    div_2_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_2_2_rv64gc    div_2_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_2_4_rv64gc    div_2_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_4_1_rv64gc    div_4_1_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_4_2_rv64gc    div_4_2_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 deriv fdqh_div_4_4_rv64gc    div_4_4_rv64gc    
-MISA (32'h00000104 | 1<< 5 | 1 << 3 | 1 << 16 | 1<< 18 | 1 << 20 | 1 << 12 | 1 << 0)
+Q_SUPPORTED     0
 ZFH_SUPPORTED   1
 
 #### DIVIDER VARIANTS WITH IEEE

config/rv32e/config.vh

@@ -33,26 +33,79 @@ localparam XLEN = 32'd32;
 // IEEE 754 compliance
 localparam IEEE754 = 0;
 
-// E
+// RISC-V configuration per specification
-localparam MISA = (32'h00000010); 
+// Base instruction set (defaults to I if E is not supported)
-localparam ZICSR_SUPPORTED = 0;
+localparam E_SUPPORTED = 1;
-localparam ZIFENCEI_SUPPORTED = 0;
+
-localparam COUNTERS = 12'd0;
+// Integer instruction set extensions
-localparam ZICNTR_SUPPORTED = 0;
+localparam ZIFENCEI_SUPPORTED = 0; // Instruction-Fetch fence
-localparam ZIHPM_SUPPORTED = 0;
+localparam ZICSR_SUPPORTED = 0;    // CSR Instructions
+localparam ZICCLSM_SUPPORTED = 0;  // Misaligned loads/stores
+localparam ZICOND_SUPPORTED = 0;   // Integer conditional operations
+
+// Multiplication & division extensions
+localparam M_SUPPORTED = 0;
+localparam ZMMUL_SUPPORTED= 0;
+
+// Atomic extensions
+// A extension is Zaamo + Zalrsc
+localparam ZAAMO_SUPPORTED = 0;
+localparam ZALRSC_SUPPORTED = 0;
+
+// Bit manipulation extensions
+// B extension is Zba + Zbb + Zbs
+localparam ZBA_SUPPORTED = 0;
+localparam ZBB_SUPPORTED = 0;
+localparam ZBS_SUPPORTED = 0;
+localparam ZBC_SUPPORTED = 0;
+
+// Scalar crypto extensions
+// Zkn is all 6
+localparam ZBKB_SUPPORTED = 0;
+localparam ZBKC_SUPPORTED = 0;
+localparam ZBKX_SUPPORTED = 0;
+localparam ZKND_SUPPORTED = 0;
+localparam ZKNE_SUPPORTED = 0;
+localparam ZKNH_SUPPORTED = 0;
+
+// Compressed extensions
+// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
+// All compressed extensions require Zca
+localparam ZCA_SUPPORTED = 0;
+localparam ZCB_SUPPORTED = 0;
+localparam ZCF_SUPPORTED = 0; // RV32 only, requires F
+localparam ZCD_SUPPORTED = 0; // requires D
+
+// Floating point extensions
+localparam F_SUPPORTED = 0;
+localparam D_SUPPORTED = 0;
+localparam Q_SUPPORTED = 0;
 localparam ZFH_SUPPORTED = 0;
 localparam ZFA_SUPPORTED = 0;
-localparam SSTC_SUPPORTED = 0;
+
+// Privelege modes
+localparam S_SUPPORTED = 0; // Supervisor mode
+localparam U_SUPPORTED = 0; // User mode
+
+// Supervisor level extensions
+localparam SSTC_SUPPORTED = 0; // Supervisor-mode timer interrupts
+
+// Hardware performance counters
+localparam ZICNTR_SUPPORTED = 0;
+localparam ZIHPM_SUPPORTED = 0;
+localparam COUNTERS = 12'd0;
+
+// Cache-management operation extensions
 localparam ZICBOM_SUPPORTED = 0;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
-localparam ZICCLSM_SUPPORTED = 0;
+
-localparam ZICOND_SUPPORTED = 0;
+// Virtual memory extensions
 localparam SVPBMT_SUPPORTED = 0;
 localparam SVNAPOT_SUPPORTED = 0;
 localparam SVINVAL_SUPPORTED = 0;
-localparam ZAAMO_SUPPORTED = 0;
+localparam SVADU_SUPPORTED = 0;
-localparam ZALRSC_SUPPORTED = 0;
+
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 1;
@@ -154,6 +207,7 @@ localparam PLIC_UART_ID = 32'd10;
 localparam PLIC_SPI_ID = 32'd6;
 localparam PLIC_SDC_ID = 32'd9;
 
+// Branch prediction
 localparam BPRED_SUPPORTED = 0;
 localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 localparam BPRED_SIZE = 32'd10;
@@ -162,34 +216,10 @@ localparam BTB_SIZE = 32'd10;
 localparam RAS_SIZE = 32'd16;
 localparam INSTR_CLASS_PRED = 0;
 
-localparam SVADU_SUPPORTED = 0;
-localparam ZMMUL_SUPPORTED = 0;
-
 // FPU division architecture
 localparam RADIX = 32'd4;
 localparam DIVCOPIES = 32'd4;
 
-// bit manipulation
-localparam ZBA_SUPPORTED = 0;
-localparam ZBB_SUPPORTED = 0;
-localparam ZBC_SUPPORTED = 0;
-localparam ZBS_SUPPORTED = 0;
-
-// New compressed instructions
-localparam ZCB_SUPPORTED = 0;
-localparam ZCA_SUPPORTED = 0;
-localparam ZCF_SUPPORTED = 0;
-localparam ZCD_SUPPORTED = 0;
-
-// K extension instructions                                                                
-localparam ZBKB_SUPPORTED = 0;
-localparam ZBKC_SUPPORTED = 0;
-localparam ZBKX_SUPPORTED = 0;
-localparam ZKNE_SUPPORTED = 0;
-localparam ZKND_SUPPORTED = 0;
-localparam ZK_SUPPORTED = 0;
-localparam ZKNH_SUPPORTED = 0;
-
 // Memory synthesis configuration
 localparam USE_SRAM = 0;
 

config/rv32gc/config.vh

@@ -35,25 +35,79 @@ localparam XLEN = 32'd32;
 // IEEE 754 compliance
 localparam IEEE754 = 0;
 
-localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5);
+// RISC-V configuration per specification
-localparam ZICSR_SUPPORTED = 1;
+// Base instruction set (defaults to I if E is not supported)
-localparam ZIFENCEI_SUPPORTED = 1;
+localparam E_SUPPORTED = 0;
-localparam COUNTERS = 12'd32;
+
-localparam ZICNTR_SUPPORTED = 1;
+// Integer instruction set extensions
-localparam ZIHPM_SUPPORTED = 1;
+localparam ZIFENCEI_SUPPORTED = 1; // Instruction-Fetch fence
+localparam ZICSR_SUPPORTED = 1;    // CSR Instructions
+localparam ZICCLSM_SUPPORTED = 0;  // Misaligned loads/stores
+localparam ZICOND_SUPPORTED = 1;   // Integer conditional operations
+
+// Multiplication & division extensions
+localparam M_SUPPORTED = 1;
+localparam ZMMUL_SUPPORTED= 0;
+
+// Atomic extensions
+// A extension is Zaamo + Zalrsc
+localparam ZAAMO_SUPPORTED = 1;
+localparam ZALRSC_SUPPORTED = 1;
+
+// Bit manipulation extensions
+// B extension is Zba + Zbb + Zbs
+localparam ZBA_SUPPORTED = 1;
+localparam ZBB_SUPPORTED = 1;
+localparam ZBS_SUPPORTED = 1;
+localparam ZBC_SUPPORTED = 1;
+
+// Scalar crypto extensions
+// Zkn is all 6
+localparam ZBKB_SUPPORTED = 1;
+localparam ZBKC_SUPPORTED = 1;
+localparam ZBKX_SUPPORTED = 1;
+localparam ZKND_SUPPORTED = 1;
+localparam ZKNE_SUPPORTED = 1;
+localparam ZKNH_SUPPORTED = 1;
+
+// Compressed extensions
+// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
+// All compressed extensions require Zca
+localparam ZCA_SUPPORTED = 1;
+localparam ZCB_SUPPORTED = 1;
+localparam ZCF_SUPPORTED = 1; // RV32 only, requires F
+localparam ZCD_SUPPORTED = 1; // requires D
+
+// Floating point extensions
+localparam F_SUPPORTED = 1;
+localparam D_SUPPORTED = 1;
+localparam Q_SUPPORTED = 0;
 localparam ZFH_SUPPORTED = 1;
 localparam ZFA_SUPPORTED = 1;
-localparam SSTC_SUPPORTED = 1;
+
+// Privelege modes
+localparam S_SUPPORTED = 1; // Supervisor mode
+localparam U_SUPPORTED = 1; // User mode
+
+// Supervisor level extensions
+localparam SSTC_SUPPORTED = 1; // Supervisor-mode timer interrupts
+
+// Hardware performance counters
+localparam ZICNTR_SUPPORTED = 1;
+localparam ZIHPM_SUPPORTED = 1;
+localparam COUNTERS = 12'd32;
+
+// Cache-management operation extensions
 localparam ZICBOM_SUPPORTED = 1;
 localparam ZICBOZ_SUPPORTED = 1;
 localparam ZICBOP_SUPPORTED = 1;
-localparam ZICCLSM_SUPPORTED = 0;
+
-localparam ZICOND_SUPPORTED = 1;
+// Virtual memory extensions
 localparam SVPBMT_SUPPORTED = 0;
 localparam SVNAPOT_SUPPORTED = 0;
 localparam SVINVAL_SUPPORTED = 1;
-localparam ZAAMO_SUPPORTED = 0;
+localparam SVADU_SUPPORTED = 1;
-localparam ZALRSC_SUPPORTED = 0;
+
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 1;
@@ -155,6 +209,7 @@ localparam PLIC_UART_ID = 32'd10;
 localparam PLIC_SPI_ID = 32'd6;
 localparam PLIC_SDC_ID = 32'd9;
 
+// Branch prediction
 localparam BPRED_SUPPORTED = 1;
 localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 localparam BPRED_SIZE = 32'd10;
@@ -163,34 +218,10 @@ localparam BTB_SIZE = 32'd10;
 localparam RAS_SIZE = 32'd16;
 localparam INSTR_CLASS_PRED = 1;
 
-localparam SVADU_SUPPORTED = 1;
-localparam ZMMUL_SUPPORTED = 0;
-
 // FPU division architecture
 localparam RADIX = 32'd4;
 localparam DIVCOPIES = 32'd2;
 
-// bit manipulation
-localparam ZBA_SUPPORTED = 1;
-localparam ZBB_SUPPORTED = 1;
-localparam ZBC_SUPPORTED = 1;
-localparam ZBS_SUPPORTED = 1;
-
-// New compressed instructions
-localparam ZCB_SUPPORTED = 1;
-localparam ZCA_SUPPORTED = 0;
-localparam ZCF_SUPPORTED = 0;
-localparam ZCD_SUPPORTED = 0;
-
-// K extension instructions                                                                
-localparam ZBKB_SUPPORTED = 1;
-localparam ZBKC_SUPPORTED = 1;
-localparam ZBKX_SUPPORTED = 1;
-localparam ZKND_SUPPORTED = 1;
-localparam ZKNE_SUPPORTED = 1;
-localparam ZKNH_SUPPORTED = 1;
-localparam ZK_SUPPORTED = 1;
-
 // Memory synthesis configuration
 localparam USE_SRAM = 0;
 

config/rv32i/config.vh

@@ -33,26 +33,79 @@ localparam XLEN = 32'd32;
 // IEEE 754 compliance
 localparam IEEE754 = 0;
 
-// I
+// RISC-V configuration per specification
-localparam MISA = (32'h00000100);
+// Base instruction set (defaults to I if E is not supported)
-localparam ZICSR_SUPPORTED = 0;
+localparam E_SUPPORTED = 0;
-localparam ZIFENCEI_SUPPORTED = 0;
+
-localparam COUNTERS = 0;
+// Integer instruction set extensions
-localparam ZICNTR_SUPPORTED = 0;
+localparam ZIFENCEI_SUPPORTED = 0; // Instruction-Fetch fence
-localparam ZIHPM_SUPPORTED = 0;
+localparam ZICSR_SUPPORTED = 0;    // CSR Instructions
+localparam ZICCLSM_SUPPORTED = 0;  // Misaligned loads/stores
+localparam ZICOND_SUPPORTED = 0;   // Integer conditional operations
+
+// Multiplication & division extensions
+localparam M_SUPPORTED = 0;
+localparam ZMMUL_SUPPORTED= 0;
+
+// Atomic extensions
+// A extension is Zaamo + Zalrsc
+localparam ZAAMO_SUPPORTED = 0;
+localparam ZALRSC_SUPPORTED = 0;
+
+// Bit manipulation extensions
+// B extension is Zba + Zbb + Zbs
+localparam ZBA_SUPPORTED = 0;
+localparam ZBB_SUPPORTED = 0;
+localparam ZBS_SUPPORTED = 0;
+localparam ZBC_SUPPORTED = 0;
+
+// Scalar crypto extensions
+// Zkn is all 6
+localparam ZBKB_SUPPORTED = 0;
+localparam ZBKC_SUPPORTED = 0;
+localparam ZBKX_SUPPORTED = 0;
+localparam ZKND_SUPPORTED = 0;
+localparam ZKNE_SUPPORTED = 0;
+localparam ZKNH_SUPPORTED = 0;
+
+// Compressed extensions
+// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
+// All compressed extensions require Zca
+localparam ZCA_SUPPORTED = 0;
+localparam ZCB_SUPPORTED = 0;
+localparam ZCF_SUPPORTED = 0; // RV32 only, requires F
+localparam ZCD_SUPPORTED = 0; // requires D
+
+// Floating point extensions
+localparam F_SUPPORTED = 0;
+localparam D_SUPPORTED = 0;
+localparam Q_SUPPORTED = 0;
 localparam ZFH_SUPPORTED = 0;
 localparam ZFA_SUPPORTED = 0;
-localparam SSTC_SUPPORTED = 0;
+
+// Privelege modes
+localparam S_SUPPORTED = 0; // Supervisor mode
+localparam U_SUPPORTED = 0; // User mode
+
+// Supervisor level extensions
+localparam SSTC_SUPPORTED = 0; // Supervisor-mode timer interrupts
+
+// Hardware performance counters
+localparam ZICNTR_SUPPORTED = 0;
+localparam ZIHPM_SUPPORTED = 0;
+localparam COUNTERS = 0;
+
+// Cache-management operation extensions
 localparam ZICBOM_SUPPORTED = 0;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
-localparam ZICCLSM_SUPPORTED = 0;
+
-localparam ZICOND_SUPPORTED = 0;
+// Virtual memory extensions
 localparam SVPBMT_SUPPORTED = 0;
 localparam SVNAPOT_SUPPORTED = 0;
 localparam SVINVAL_SUPPORTED = 0;
-localparam ZAAMO_SUPPORTED = 0;
+localparam SVADU_SUPPORTED = 0;
-localparam ZALRSC_SUPPORTED = 0;
+
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 0;
@@ -152,9 +205,9 @@ localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32);
 localparam PLIC_GPIO_ID = 32'd3;
 localparam PLIC_UART_ID = 32'd10;
 localparam PLIC_SPI_ID = 32'd6;
-
 localparam PLIC_SDC_ID = 32'd9;
 
+// Branch prediction
 localparam BPRED_SUPPORTED = 0;
 localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 localparam BPRED_SIZE = 32'd10;
@@ -163,34 +216,10 @@ localparam BTB_SIZE = 32'd10;
 localparam RAS_SIZE = 32'd16;
 localparam INSTR_CLASS_PRED = 0;
 
-localparam SVADU_SUPPORTED = 0;
-localparam ZMMUL_SUPPORTED = 0;
-
 // FPU division architecture
 localparam RADIX = 32'h4;
 localparam DIVCOPIES = 32'h4;
 
-// bit manipulation
-localparam ZBA_SUPPORTED = 0;
-localparam ZBB_SUPPORTED = 0;
-localparam ZBC_SUPPORTED = 0;
-localparam ZBS_SUPPORTED = 0;
-
-// New compressed instructions
-localparam ZCB_SUPPORTED = 0;
-localparam ZCA_SUPPORTED = 0;
-localparam ZCF_SUPPORTED = 0;
-localparam ZCD_SUPPORTED = 0;
-
-// K extension instructions                                                                
-localparam ZBKB_SUPPORTED = 0;
-localparam ZBKC_SUPPORTED = 0;
-localparam ZBKX_SUPPORTED = 0;
-localparam ZKNE_SUPPORTED = 0;
-localparam ZKND_SUPPORTED = 0;
-localparam ZK_SUPPORTED = 0;
-localparam ZKNH_SUPPORTED = 0;
-
 // Memory synthesis configuration
 localparam USE_SRAM = 0;
 

config/rv32imc/config.vh

@@ -33,25 +33,79 @@ localparam XLEN = 32'd32;
 // IEEE 754 compliance
 localparam IEEE754 = 0;
 
-localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12);
+// RISC-V configuration per specification
-localparam ZICSR_SUPPORTED = 1;
+// Base instruction set (defaults to I if E is not supported)
-localparam ZIFENCEI_SUPPORTED = 1;
+localparam E_SUPPORTED = 0;
-localparam COUNTERS = 12'd32;
+
-localparam ZICNTR_SUPPORTED = 1;
+// Integer instruction set extensions
-localparam ZIHPM_SUPPORTED = 1;
+localparam ZIFENCEI_SUPPORTED = 1; // Instruction-Fetch fence
+localparam ZICSR_SUPPORTED = 1;    // CSR Instructions
+localparam ZICCLSM_SUPPORTED = 0;  // Misaligned loads/stores
+localparam ZICOND_SUPPORTED = 0;   // Integer conditional operations
+
+// Multiplication & division extensions
+localparam M_SUPPORTED = 1;
+localparam ZMMUL_SUPPORTED= 0;
+
+// Atomic extensions
+// A extension is Zaamo + Zalrsc
+localparam ZAAMO_SUPPORTED = 0;
+localparam ZALRSC_SUPPORTED = 0;
+
+// Bit manipulation extensions
+// B extension is Zba + Zbb + Zbs
+localparam ZBA_SUPPORTED = 0;
+localparam ZBB_SUPPORTED = 0;
+localparam ZBS_SUPPORTED = 0;
+localparam ZBC_SUPPORTED = 0;
+
+// Scalar crypto extensions
+// Zkn is all 6
+localparam ZBKB_SUPPORTED = 0;
+localparam ZBKC_SUPPORTED = 0;
+localparam ZBKX_SUPPORTED = 0;
+localparam ZKND_SUPPORTED = 0;
+localparam ZKNE_SUPPORTED = 0;
+localparam ZKNH_SUPPORTED = 0;
+
+// Compressed extensions
+// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
+// All compressed extensions require Zca
+localparam ZCA_SUPPORTED = 1;
+localparam ZCB_SUPPORTED = 0;
+localparam ZCF_SUPPORTED = 0; // RV32 only, requires F
+localparam ZCD_SUPPORTED = 0; // requires D
+
+// Floating point extensions
+localparam F_SUPPORTED = 0;
+localparam D_SUPPORTED = 0;
+localparam Q_SUPPORTED = 0;
 localparam ZFH_SUPPORTED = 0;
 localparam ZFA_SUPPORTED = 0;
-localparam SSTC_SUPPORTED = 0;
+
+// Privelege modes
+localparam S_SUPPORTED = 1; // Supervisor mode
+localparam U_SUPPORTED = 1; // User mode
+
+// Supervisor level extensions
+localparam SSTC_SUPPORTED = 0; // Supervisor-mode timer interrupts
+
+// Hardware performance counters
+localparam ZICNTR_SUPPORTED = 1;
+localparam ZIHPM_SUPPORTED = 1;
+localparam COUNTERS = 12'd32;
+
+// Cache-management operation extensions
 localparam ZICBOM_SUPPORTED = 0;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
-localparam ZICCLSM_SUPPORTED = 0;
+
-localparam ZICOND_SUPPORTED = 0;
+// Virtual memory extensions
 localparam SVPBMT_SUPPORTED = 0;
 localparam SVNAPOT_SUPPORTED = 0;
 localparam SVINVAL_SUPPORTED = 0;
-localparam ZAAMO_SUPPORTED = 0;
+localparam SVADU_SUPPORTED = 0;
-localparam ZALRSC_SUPPORTED = 0;
+
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 1;
@@ -153,6 +207,7 @@ localparam PLIC_UART_ID = 32'd10;
 localparam PLIC_SPI_ID = 32'd6;
 localparam PLIC_SDC_ID = 32'd9;
 
+// Branch prediction
 localparam BPRED_SUPPORTED = 0;
 localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 localparam BPRED_SIZE = 32'd10;
@@ -161,34 +216,10 @@ localparam BTB_SIZE = 32'd10;
 localparam RAS_SIZE = 32'd16;
 localparam INSTR_CLASS_PRED = 0;
 
-localparam SVADU_SUPPORTED = 0;
-localparam ZMMUL_SUPPORTED = 0;
-
 // FPU division architecture
 localparam RADIX = 32'h4;
 localparam DIVCOPIES = 32'h4;
 
-// bit manipulation
-localparam ZBA_SUPPORTED = 0;
-localparam ZBB_SUPPORTED = 0;
-localparam ZBC_SUPPORTED = 0;
-localparam ZBS_SUPPORTED = 0;
-
-// New compressed instructions
-localparam ZCB_SUPPORTED = 0;
-localparam ZCA_SUPPORTED = 0;
-localparam ZCF_SUPPORTED = 0;
-localparam ZCD_SUPPORTED = 0;
-
-// K extension instructions                                                                
-localparam ZBKB_SUPPORTED = 0;
-localparam ZBKC_SUPPORTED = 0;
-localparam ZBKX_SUPPORTED = 0;
-localparam ZKNE_SUPPORTED = 0;
-localparam ZKND_SUPPORTED = 0;
-localparam ZK_SUPPORTED = 0;
-localparam ZKNH_SUPPORTED = 0;
-
 // Memory synthesis configuration
 localparam USE_SRAM = 0;
 

config/rv64gc/config.vh

@@ -33,26 +33,79 @@ localparam XLEN = 32'd64;
 // IEEE 754 compliance
 localparam IEEE754 = 0;
 
-// MISA RISC-V configuration per specification
+// RISC-V configuration per specification
-localparam MISA = (32'h00000104 |  1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0);
+// Base instruction set (defaults to I if E is not supported)
-localparam ZICSR_SUPPORTED = 1;
+localparam E_SUPPORTED = 0;
-localparam ZIFENCEI_SUPPORTED = 1;
+
-localparam COUNTERS = 12'd32;
+// Integer instruction set extensions
-localparam ZICNTR_SUPPORTED = 1;
+localparam ZIFENCEI_SUPPORTED = 1; // Instruction-Fetch fence
-localparam ZIHPM_SUPPORTED = 1;
+localparam ZICSR_SUPPORTED = 1;    // CSR Instructions
+localparam ZICCLSM_SUPPORTED = 1;  // Misaligned loads/stores
+localparam ZICOND_SUPPORTED = 1;   // Integer conditional operations
+
+// Multiplication & division extensions
+localparam M_SUPPORTED = 1;
+localparam ZMMUL_SUPPORTED= 0;
+
+// Atomic extensions
+// A extension is Zaamo + Zalrsc
+localparam ZAAMO_SUPPORTED = 1;
+localparam ZALRSC_SUPPORTED = 1;
+
+// Bit manipulation extensions
+// B extension is Zba + Zbb + Zbs
+localparam ZBA_SUPPORTED = 1;
+localparam ZBB_SUPPORTED = 1;
+localparam ZBS_SUPPORTED = 1;
+localparam ZBC_SUPPORTED = 1;
+
+// Scalar crypto extensions
+// Zkn is all 6
+localparam ZBKB_SUPPORTED = 1;
+localparam ZBKC_SUPPORTED = 1;
+localparam ZBKX_SUPPORTED = 1;
+localparam ZKND_SUPPORTED = 1;
+localparam ZKNE_SUPPORTED = 1;
+localparam ZKNH_SUPPORTED = 1;
+
+// Compressed extensions
+// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
+// All compressed extensions require Zca
+localparam ZCA_SUPPORTED = 1;
+localparam ZCB_SUPPORTED = 1;
+localparam ZCF_SUPPORTED = 0; // RV32 only, requires F
+localparam ZCD_SUPPORTED = 1; // requires D
+
+// Floating point extensions
+localparam F_SUPPORTED = 1;
+localparam D_SUPPORTED = 1;
+localparam Q_SUPPORTED = 0;
 localparam ZFH_SUPPORTED = 1;
 localparam ZFA_SUPPORTED = 1;
-localparam SSTC_SUPPORTED = 1;
+
+// Privelege modes
+localparam S_SUPPORTED = 1; // Supervisor mode
+localparam U_SUPPORTED = 1; // User mode
+
+// Supervisor level extensions
+localparam SSTC_SUPPORTED = 1; // Supervisor-mode timer interrupts
+
+// Hardware performance counters
+localparam ZICNTR_SUPPORTED = 1;
+localparam ZIHPM_SUPPORTED = 1;
+localparam COUNTERS = 12'd32;
+
+// Cache-management operation extensions
 localparam ZICBOM_SUPPORTED = 1;
 localparam ZICBOZ_SUPPORTED = 1;
 localparam ZICBOP_SUPPORTED = 1;
-localparam ZICCLSM_SUPPORTED = 1;
+
-localparam ZICOND_SUPPORTED = 1;
+// Virtual memory extensions
 localparam SVPBMT_SUPPORTED = 1;
 localparam SVNAPOT_SUPPORTED = 1;
 localparam SVINVAL_SUPPORTED = 1;
-localparam ZAAMO_SUPPORTED = 0;
+localparam SVADU_SUPPORTED = 1;
-localparam ZALRSC_SUPPORTED = 0;
+
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 1;
@@ -156,6 +209,7 @@ localparam PLIC_UART_ID = 32'd10;
 localparam PLIC_SPI_ID = 32'd6;
 localparam PLIC_SDC_ID = 32'd9;
 
+// Branch prediction
 localparam BPRED_SUPPORTED = 1;
 localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 localparam BPRED_NUM_LHR = 32'd6;
@@ -164,36 +218,11 @@ localparam BTB_SIZE = 32'd10;
 localparam RAS_SIZE = 32'd16;
 localparam INSTR_CLASS_PRED = 1;
 
-localparam SVADU_SUPPORTED = 1;
-localparam ZMMUL_SUPPORTED = 0;
-
 // FPU division architecture
 localparam RADIX = 32'h4;
 localparam DIVCOPIES = 32'h4;
 
-// bit manipulation
-localparam ZBA_SUPPORTED = 1;
-localparam ZBB_SUPPORTED = 1;
-localparam ZBC_SUPPORTED = 1;
-localparam ZBS_SUPPORTED = 1;
-
-// New compressed instructions
-localparam ZCB_SUPPORTED = 1;
-localparam ZCA_SUPPORTED = 0;
-localparam ZCF_SUPPORTED = 0;
-localparam ZCD_SUPPORTED = 0;
-
-// K extension instructions                                                                
-localparam ZBKB_SUPPORTED = 1;
-localparam ZBKC_SUPPORTED = 1;
-localparam ZBKX_SUPPORTED = 1;
-localparam ZKND_SUPPORTED = 1;
-localparam ZKNE_SUPPORTED = 1;
-localparam ZKNH_SUPPORTED = 1;
-localparam ZK_SUPPORTED = 1;
-
 // Memory synthesis configuration
 localparam USE_SRAM = 0;
 
 `include "config-shared.vh"
-

config/rv64i/config.vh

@@ -33,26 +33,79 @@ localparam XLEN = 32'd64;
 // IEEE 754 compliance
 localparam IEEE754 = 0;
 
-// MISA RISC-V configuration per specification
+// RISC-V configuration per specification
-localparam MISA = (32'h00000100);
+// Base instruction set (defaults to I if E is not supported)
-localparam ZICSR_SUPPORTED = 0;
+localparam E_SUPPORTED = 0;
-localparam ZIFENCEI_SUPPORTED = 0;
+
-localparam COUNTERS = 0;
+// Integer instruction set extensions
-localparam ZICNTR_SUPPORTED = 0;
+localparam ZIFENCEI_SUPPORTED = 0; // Instruction-Fetch fence
-localparam ZIHPM_SUPPORTED = 0;
+localparam ZICSR_SUPPORTED = 0;    // CSR Instructions
+localparam ZICCLSM_SUPPORTED = 0;  // Misaligned loads/stores
+localparam ZICOND_SUPPORTED = 0;   // Integer conditional operations
+
+// Multiplication & division extensions
+localparam M_SUPPORTED = 0;
+localparam ZMMUL_SUPPORTED= 0;
+
+// Atomic extensions
+// A extension is Zaamo + Zalrsc
+localparam ZAAMO_SUPPORTED = 0;
+localparam ZALRSC_SUPPORTED = 0;
+
+// Bit manipulation extensions
+// B extension is Zba + Zbb + Zbs
+localparam ZBA_SUPPORTED = 0;
+localparam ZBB_SUPPORTED = 0;
+localparam ZBS_SUPPORTED = 0;
+localparam ZBC_SUPPORTED = 0;
+
+// Scalar crypto extensions
+// Zkn is all 6
+localparam ZBKB_SUPPORTED = 0;
+localparam ZBKC_SUPPORTED = 0;
+localparam ZBKX_SUPPORTED = 0;
+localparam ZKND_SUPPORTED = 0;
+localparam ZKNE_SUPPORTED = 0;
+localparam ZKNH_SUPPORTED = 0;
+
+// Compressed extensions
+// C extension is Zca + Zcf (if RV32 and F supported) + Zcd (if D supported)
+// All compressed extensions require Zca
+localparam ZCA_SUPPORTED = 0;
+localparam ZCB_SUPPORTED = 0;
+localparam ZCF_SUPPORTED = 0; // RV32 only, requires F
+localparam ZCD_SUPPORTED = 0; // requires D
+
+// Floating point extensions
+localparam F_SUPPORTED = 0;
+localparam D_SUPPORTED = 0;
+localparam Q_SUPPORTED = 0;
 localparam ZFH_SUPPORTED = 0;
 localparam ZFA_SUPPORTED = 0;
-localparam SSTC_SUPPORTED = 0;
+
+// Privelege modes
+localparam S_SUPPORTED = 0; // Supervisor mode
+localparam U_SUPPORTED = 0; // User mode
+
+// Supervisor level extensions
+localparam SSTC_SUPPORTED = 0; // Supervisor-mode timer interrupts
+
+// Hardware performance counters
+localparam ZICNTR_SUPPORTED = 0;
+localparam ZIHPM_SUPPORTED = 0;
+localparam COUNTERS = 0;
+
+// Cache-management operation extensions
 localparam ZICBOM_SUPPORTED = 0;
 localparam ZICBOZ_SUPPORTED = 0;
 localparam ZICBOP_SUPPORTED = 0;
-localparam ZICCLSM_SUPPORTED = 0;
+
-localparam ZICOND_SUPPORTED = 0;
+// Virtual memory extensions
 localparam SVPBMT_SUPPORTED = 0;
 localparam SVNAPOT_SUPPORTED = 0;
 localparam SVINVAL_SUPPORTED = 0;
-localparam ZAAMO_SUPPORTED = 0;
+localparam SVADU_SUPPORTED = 0;
-localparam ZALRSC_SUPPORTED = 0;
+
 
 // LSU microarchitectural Features
 localparam BUS_SUPPORTED = 0;
@@ -156,6 +209,7 @@ localparam PLIC_UART_ID = 32'd10;
 localparam PLIC_SPI_ID = 32'd6;
 localparam PLIC_SDC_ID = 32'd9;
 
+// Branch prediction
 localparam BPRED_SUPPORTED = 0;
 localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 localparam BPRED_SIZE = 32'd10;
@@ -164,34 +218,10 @@ localparam BTB_SIZE = 32'd10;
 localparam RAS_SIZE = 32'd16;
 localparam INSTR_CLASS_PRED = 0;
 
-localparam SVADU_SUPPORTED = 0;
-localparam ZMMUL_SUPPORTED = 0;
-
 // FPU division architecture
 localparam RADIX = 32'h4;
 localparam DIVCOPIES = 32'h4;
 
-// bit manipulation
-localparam ZBA_SUPPORTED = 0;
-localparam ZBB_SUPPORTED = 0;
-localparam ZBC_SUPPORTED = 0;
-localparam ZBS_SUPPORTED = 0;
-
-// New compressed instructions
-localparam ZCB_SUPPORTED = 0;
-localparam ZCA_SUPPORTED = 0;
-localparam ZCF_SUPPORTED = 0;
-localparam ZCD_SUPPORTED = 0;
-
-// K extension instructions                                                                
-localparam ZBKB_SUPPORTED = 0;
-localparam ZBKC_SUPPORTED = 0;
-localparam ZBKX_SUPPORTED = 0;
-localparam ZKNE_SUPPORTED = 0;
-localparam ZKND_SUPPORTED = 0;
-localparam ZK_SUPPORTED = 0;
-localparam ZKNH_SUPPORTED = 0;
-
 // Memory synthesis configuration
 localparam USE_SRAM = 0;
 

config/shared/config-shared.vh

@@ -24,20 +24,14 @@ localparam SV39 = 4'd8;
 localparam SV48 = 4'd9;
 
 // macros to define supported modes
-localparam A_SUPPORTED = ((MISA >> 0) % 2 == 1);
+localparam I_SUPPORTED = (!E_SUPPORTED);
-localparam B_SUPPORTED = ((ZBA_SUPPORTED | ZBB_SUPPORTED | ZBC_SUPPORTED | ZBS_SUPPORTED));// not based on MISA
+localparam A_SUPPORTED = (ZAAMO_SUPPORTED && ZALRSC_SUPPORTED);
-localparam C_SUPPORTED = ((MISA >> 2) % 2 == 1);
+localparam B_SUPPORTED = ((ZBA_SUPPORTED && ZBB_SUPPORTED && ZBS_SUPPORTED));
-localparam COMPRESSED_SUPPORTED = C_SUPPORTED | ZCA_SUPPORTED;
+localparam C_SUPPORTED = ZCA_SUPPORTED && (D_SUPPORTED ? ZCD_SUPPORTED : 1) && (F_SUPPORTED ? ((XLEN == 32) ? ZCF_SUPPORTED : 1) : 1);
-localparam D_SUPPORTED = ((MISA >> 3) % 2 == 1);
+localparam ZKN_SUPPORTED = (ZBKB_SUPPORTED && ZBKC_SUPPORTED && ZBKX_SUPPORTED && ZKND_SUPPORTED && ZKNE_SUPPORTED && ZKNH_SUPPORTED);
-localparam E_SUPPORTED = ((MISA >> 4) % 2 == 1);
+
-localparam F_SUPPORTED = ((MISA >> 5) % 2 == 1);
+// Configure MISA based on supported extensions
-localparam I_SUPPORTED = ((MISA >> 8) % 2 == 1);
+localparam MISA = {6'b0, 5'b0, U_SUPPORTED[0], 1'b0, S_SUPPORTED[0], 1'b0, Q_SUPPORTED[0], 3'b0, M_SUPPORTED[0], 3'b0, I_SUPPORTED[0], 2'b0, F_SUPPORTED[0], E_SUPPORTED[0], D_SUPPORTED[0], C_SUPPORTED[0], B_SUPPORTED[0], A_SUPPORTED[0]};
-localparam K_SUPPORTED = ((ZBKB_SUPPORTED | ZBKC_SUPPORTED | ZBKX_SUPPORTED | ZKND_SUPPORTED | ZKNE_SUPPORTED | ZKNH_SUPPORTED));
-localparam M_SUPPORTED = ((MISA >> 12) % 2 == 1);
-localparam Q_SUPPORTED = ((MISA >> 16) % 2 == 1);
-localparam S_SUPPORTED = ((MISA >> 18) % 2 == 1);
-localparam U_SUPPORTED = ((MISA >> 20) % 2 == 1);
-// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
 
 // logarithm of XLEN, used for number of index bits to select
 localparam LOG_XLEN = (XLEN == 32 ? 32'd5 : 32'd6);

config/shared/parameter-defs.vh

@@ -121,7 +121,7 @@ localparam cvw_t P = '{
   ZKND_SUPPORTED:        ZKND_SUPPORTED,
   ZKNE_SUPPORTED:        ZKNE_SUPPORTED,
   ZKNH_SUPPORTED:        ZKNH_SUPPORTED,
-  ZK_SUPPORTED  :        ZK_SUPPORTED,
+  ZKN_SUPPORTED :        ZKN_SUPPORTED,
   USE_SRAM :        USE_SRAM,
   M_MODE  : M_MODE, 
   S_MODE  : S_MODE, 
@@ -140,12 +140,10 @@ localparam cvw_t P = '{
   A_SUPPORTED : A_SUPPORTED,
   B_SUPPORTED : B_SUPPORTED,
   C_SUPPORTED : C_SUPPORTED,
-  COMPRESSED_SUPPORTED : COMPRESSED_SUPPORTED,
   D_SUPPORTED : D_SUPPORTED,
   E_SUPPORTED : E_SUPPORTED,
   F_SUPPORTED : F_SUPPORTED,
   I_SUPPORTED : I_SUPPORTED,
-  K_SUPPORTED : K_SUPPORTED,
   M_SUPPORTED : M_SUPPORTED,
   Q_SUPPORTED : Q_SUPPORTED,
   S_SUPPORTED : S_SUPPORTED,

src/cvw.sv

@@ -189,7 +189,7 @@ typedef struct packed {
   logic         ZKND_SUPPORTED;
   logic         ZKNE_SUPPORTED;
   logic         ZKNH_SUPPORTED;
-  logic         ZK_SUPPORTED;
+  logic         ZKN_SUPPORTED;
 
 // Memory synthesis configuration
   logic         USE_SRAM;
@@ -220,12 +220,10 @@ typedef struct packed {
   logic A_SUPPORTED;
   logic B_SUPPORTED;
   logic C_SUPPORTED;
-  logic COMPRESSED_SUPPORTED;  // C or ZCA
   logic D_SUPPORTED;
   logic E_SUPPORTED;
   logic F_SUPPORTED;
   logic I_SUPPORTED;
-  logic K_SUPPORTED;
   logic M_SUPPORTED;
   logic Q_SUPPORTED;
   logic S_SUPPORTED;

src/ifu/bpred/icpred.sv

@@ -55,7 +55,7 @@ module icpred import cvw::*;  #(parameter cvw_t P,
     logic     cjal, cj, cjr, cjalr, CJumpF, CBranchF;
     logic     NCJumpF, NCBranchF;
 
-    if(P.COMPRESSED_SUPPORTED) begin
+    if(P.ZCA_SUPPORTED) begin
       logic [4:0] CompressedOpcF;
       assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]};
       assign cjal = CompressedOpcF == 5'h09 & P.XLEN == 32;
@@ -71,13 +71,13 @@ module icpred import cvw::*;  #(parameter cvw_t P,
     assign NCJumpF = PostSpillInstrRawF[6:0] == 7'h67 | PostSpillInstrRawF[6:0] == 7'h6F;
     assign NCBranchF = PostSpillInstrRawF[6:0] == 7'h63;
     
-    assign BPBranchF = NCBranchF | (P.COMPRESSED_SUPPORTED & CBranchF);
+    assign BPBranchF = NCBranchF | (P.ZCA_SUPPORTED & CBranchF);
-    assign BPJumpF = NCJumpF | (P.COMPRESSED_SUPPORTED & (CJumpF));
+    assign BPJumpF = NCJumpF | (P.ZCA_SUPPORTED & (CJumpF));
     assign BPReturnF = (NCJumpF & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 & PostSpillInstrRawF[11:7] == 5'b0) | // return must return to ra or r5
-        (P.COMPRESSED_SUPPORTED & cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
+        (P.ZCA_SUPPORTED & cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
     
     assign BPCallF = (NCJumpF & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // call(r) must link to ra or x5
-        (P.COMPRESSED_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
+        (P.ZCA_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
 
   end else begin
     // This section connects the BTB's instruction class prediction.

src/ifu/decompress.sv

@@ -89,7 +89,7 @@ module decompress import cvw::*;  #(parameter cvw_t P) (
                     IllegalCompInstrD = 1'b1;
                     InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                   end
-        5'b00001: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
+        5'b00001: if (P.ZCD_SUPPORTED)
                     InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld
                   else begin // unsupported instruction
                     IllegalCompInstrD = 1'b1;
@@ -97,7 +97,7 @@ module decompress import cvw::*;  #(parameter cvw_t P) (
                   end
         5'b00010: InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw
         5'b00011: if (P.XLEN==32)
-                    if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED) 
+                    if (P.ZCF_SUPPORTED) 
                       InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw
                     else begin
                       IllegalCompInstrD = 1'b1;
@@ -125,7 +125,7 @@ module decompress import cvw::*;  #(parameter cvw_t P) (
                     IllegalCompInstrD = 1'b1;
                     InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
                   end
-        5'b00101: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
+        5'b00101: if (P.ZCD_SUPPORTED)
                     InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd
                   else begin // unsupported instruction
                     IllegalCompInstrD = 1'b1;
@@ -133,7 +133,7 @@ module decompress import cvw::*;  #(parameter cvw_t P) (
                   end
         5'b00110: InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw
         5'b00111: if (P.XLEN==32)
-                    if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED) 
+                    if (P.ZCF_SUPPORTED) 
                       InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw
                     else begin
                       IllegalCompInstrD = 1'b1;
@@ -197,7 +197,7 @@ module decompress import cvw::*;  #(parameter cvw_t P) (
         5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz
         5'b01111: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez
         5'b10000: InstrD = {6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli
-        5'b10001: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
+        5'b10001: if (P.ZCD_SUPPORTED)
                     InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
                   else begin // unsupported instruction
                     IllegalCompInstrD = 1'b1;
@@ -205,7 +205,7 @@ module decompress import cvw::*;  #(parameter cvw_t P) (
                   end
         5'b10010: InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp
         5'b10011: if (P.XLEN == 32)
-                    if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED) 
+                    if (P.ZCF_SUPPORTED) 
                       InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
                     else begin
                       IllegalCompInstrD = 1'b1;
@@ -226,7 +226,7 @@ module decompress import cvw::*;  #(parameter cvw_t P) (
                         InstrD = {12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr
                     else
                       InstrD = {7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add
-        5'b10101: if (P.C_SUPPORTED & P.D_SUPPORTED | P.ZCD_SUPPORTED)
+        5'b10101: if (P.ZCD_SUPPORTED)
                     InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
                   else begin // unsupported instruction
                     IllegalCompInstrD = 1'b1;
@@ -234,7 +234,7 @@ module decompress import cvw::*;  #(parameter cvw_t P) (
                   end
         5'b10110: InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp
         5'b10111: if (P.XLEN==32)
-                    if (P.C_SUPPORTED & P.F_SUPPORTED | P.ZCF_SUPPORTED) 
+                    if (P.ZCF_SUPPORTED) 
                       InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp
                     else begin
                       IllegalCompInstrD = 1'b1;

src/ifu/ifu.sv

@@ -147,7 +147,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   // Spill Support
   /////////////////////////////////////////////////////////////////////////////////////////////
 
-  if(P.COMPRESSED_SUPPORTED) begin : Spill
+  if(P.ZCA_SUPPORTED) begin : Spill
     spill #(P) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF, .InstrUpdateDAF, .CacheableF, 
       .IFUCacheBusStallF, .ITLBMissF, .PCSpillNextF, .PCSpillF, .SelSpillNextF, .PostSpillInstrRawF, .CompressedF);
   end else begin : NoSpill
@@ -321,7 +321,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   // add 2 or 4 to the PC, based on whether the instruction is 16 bits or 32
   assign PCPlus4F = PCF[P.XLEN-1:2] + 1; // add 4 to PC
 
-  if (P.COMPRESSED_SUPPORTED) begin: pcadd
+  if (P.ZCA_SUPPORTED) begin: pcadd
     // choose PC+2 or PC+4 based on CompressedF, which arrives later. 
     // Speeds up critical path as compared to selecting adder input based on CompressedF
     always_comb
@@ -373,7 +373,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   flopenrc #(P.XLEN) PCDReg(clk, reset, FlushD, ~StallD, PCF, PCD);
    
   // expand 16-bit compressed instructions to 32 bits
-  if (P.COMPRESSED_SUPPORTED) begin: decomp
+  if (P.ZCA_SUPPORTED) begin: decomp
     logic IllegalCompInstrD;
     decompress #(P) decomp(.InstrRawD, .InstrD, .IllegalCompInstrD); 
     assign IllegalIEUInstrD = IllegalBaseInstrD | IllegalCompInstrD; // illegal if bad 32 or 16-bit instr
@@ -393,7 +393,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   // only IALIGN=32, the two low bits (mepc[1:0]) are always zero.
   // Spec 3.1.14
   // Traps: Can’t happen.  The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4.  See 3.1.7 of the privileged spec.
-  assign BranchMisalignedFaultE = (IEUAdrE[1] & ~P.COMPRESSED_SUPPORTED) & PCSrcE;
+  assign BranchMisalignedFaultE = (IEUAdrE[1] & ~P.ZCA_SUPPORTED) & PCSrcE;
   flopenr #(1) InstrMisalignedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM);
 
   // Instruction and PC pipeline registers flush to NOP, not zero
@@ -412,7 +412,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   else assign PCM = '0; 
   
   // If compressed instructions are supported, increment PCLink by 2 or 4 for a jal.  Otherwise, just by 4
-  if (P.COMPRESSED_SUPPORTED) begin
+  if (P.ZCA_SUPPORTED) begin
     logic CompressedD;  // instruction is compressed
     flopenrc #(1) CompressedDReg(clk, reset, FlushD, ~StallD, CompressedF, CompressedD);
     flopenrc #(1) CompressedEReg(clk, reset, FlushE, ~StallE, CompressedD, CompressedE);
@@ -423,7 +423,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
   end
  
   // pipeline original compressed instruction in case it is needed for MTVAL on an illegal instruction exception
-  if (P.ZICSR_SUPPORTED & P.COMPRESSED_SUPPORTED | 1) begin
+  if (P.ZICSR_SUPPORTED & P.ZCA_SUPPORTED | 1) begin
     logic CompressedM; // instruction is compressed
     flopenrc #(16) InstrRawEReg(clk, reset, FlushE, ~StallE, InstrRawD[15:0], InstrRawE);
     flopenrc #(16) InstrRawMReg(clk, reset, FlushM, ~StallM, InstrRawE, InstrRawM);

src/ifu/irom.sv

@@ -52,7 +52,7 @@ module irom import cvw::*;  #(parameter cvw_t P) (
   end
   // If the memory addres is aligned to 2 bytes return the upper 2 bytes in the lower 2 bytes.
   // The spill logic will handle merging the two together.
-  if (P.COMPRESSED_SUPPORTED) begin
+  if (P.ZCA_SUPPORTED) begin
     flopen #(1) AdrReg1(clk, ce, Adr[1], AdrD[1]);
     assign IROMInstrF = AdrD[1] ? {16'b0, RawIROMInstrF[31:16]} : RawIROMInstrF;
   end else

src/privileged/csr.sv

@@ -200,7 +200,7 @@ module csr import cvw::*;  #(parameter cvw_t P) (
 
   assign CSRAdrM = InstrM[31:20];
   assign UnalignedNextEPCM = TrapM ? PCM : CSRWriteValM;
-  assign NextEPCM = P.COMPRESSED_SUPPORTED ? {UnalignedNextEPCM[P.XLEN-1:1], 1'b0} : {UnalignedNextEPCM[P.XLEN-1:2], 2'b00}; // 3.1.15 alignment
+  assign NextEPCM = P.ZCA_SUPPORTED ? {UnalignedNextEPCM[P.XLEN-1:1], 1'b0} : {UnalignedNextEPCM[P.XLEN-1:2], 2'b00}; // 3.1.15 alignment
   assign NextCauseM = TrapM ? {InterruptM, CauseM}: {CSRWriteValM[P.XLEN-1], CSRWriteValM[3:0]};
   assign NextMtvalM = TrapM ? NextFaultMtvalM : CSRWriteValM;
   assign UngatedCSRMWriteM = CSRWriteM & (PrivilegeModeW == P.M_MODE);

src/privileged/csrm.sv

@@ -96,7 +96,7 @@ module csrm  import cvw::*;  #(parameter cvw_t P) (
   // Constants
   localparam ZERO = {(P.XLEN){1'b0}};
   // when compressed instructions are supported, there can't be misaligned instructions
-  localparam MEDELEG_MASK  = P.COMPRESSED_SUPPORTED ? 16'hB3FE : 16'hB3FF;
+  localparam MEDELEG_MASK  = P.ZCA_SUPPORTED ? 16'hB3FE : 16'hB3FF;
   localparam MIDELEG_MASK  = 12'h222; // we choose to not make machine interrupts delegable
 
  // There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop

testbench/common/riscvassertions.sv

@@ -62,12 +62,10 @@ module riscvassertions import cvw::*; #(parameter cvw_t P);
     assert ((P.SVPBMT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $fatal(1, "SVPBMT requires VIRTMEM_SUPPORTED and RV64");
     assert ((P.SVNAPOT_SUPPORTED == 0) || (P.VIRTMEM_SUPPORTED == 1 && P.XLEN==64)) else $fatal(1, "SVNAPOT requires VIRTMEM_SUPPORTED and RV64");
     assert ((P.ZCB_SUPPORTED == 0) || (P.M_SUPPORTED == 1 && (P.ZBA_SUPPORTED == 1 || P.XLEN == 32) && P.ZBB_SUPPORTED == 1)) else $fatal(1, "ZCB requires M and ZBB (and also ZBA for RV64)");
-    assert ((P.C_SUPPORTED == 0) || (P.ZCA_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0 && P.ZCD_SUPPORTED == 0)) else $fatal(1, "C and ZCA/ZCD/ZCF cannot simultaneously be supported");
+    assert ((P.ZCA_SUPPORTED == 1) || (P.ZCD_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0 && P.ZCB_SUPPORTED == 0)) else $fatal(1, "ZCB, ZCF, or ZCD requires ZCA");
-    assert ((P.ZCA_SUPPORTED == 1) || (P.ZCD_SUPPORTED == 0 && P.ZCF_SUPPORTED == 0)) else $fatal(1, "ZCF or ZCD requires ZCA");
+    assert ((P.ZCF_SUPPORTED == 0) || ((P.F_SUPPORTED == 1) && (P.XLEN == 32))) else $fatal(1, "ZCF requires F and XLEN == 32");
-    assert ((P.ZCF_SUPPORTED == 0) || (P.F_SUPPORTED == 1)) else $fatal(1, "ZCF requires F");
     assert ((P.ZCD_SUPPORTED == 0) || (P.D_SUPPORTED == 1)) else $fatal(1, "ZCD requires D");   
     assert ((P.LLEN == P.XLEN) || (P.DCACHE_SUPPORTED)) else $fatal(1, "LLEN > XLEN (D on RV32 or Q on RV64) requires data cache");
-    assert (P.A_SUPPORTED + P.ZAAMO_SUPPORTED + P.ZALRSC_SUPPORTED < 2) else $fatal(1, "At most one of A, Zaamo, or Zalrsc can be supported");
   end
 
 endmodule