More code cleanup

src/generic/aplusbeq0.sv

@@ -34,7 +34,7 @@ module aplusbeq0 #(parameter WIDTH = 8) (
   logic [WIDTH-1:0] orshift;
 
   // The sum is zero if the bitwise XOR is equal to the bitwise OR shifted left by 1, for all columns
-  // *** explain, cite book
+  // See J. A. Prabhu and G. Zyner, "167 MHz radix-8 divide and square root using overlapped radix-2 stages," IEEE Symp. Computer Arithmetic, 1995, pp. 155-162.
 
   assign x = a ^ b;
   assign orshift = {a[WIDTH-2:0] | b[WIDTH-2:0], 1'b0};

src/mmu/hptw.sv

@@ -281,7 +281,6 @@ module hptw import cvw::*;  #(parameter cvw_t P) (
   // 2. If the store would generate an exception don't store to dcache but still write the TLB.  When we go back
   // to LEAF then the PMA/P.  Wait this does not work.  The PMA/P won't be looking a the address in the table, but
   // rather than physical address of the translated instruction/data.  So we must generate the exception.
-  // *** DH 1/1/24 another bug: when the NAPOT bits (PTE[62:61]) are nonzero on a nonleaf PTE, the walker should make a page fault (Issue 546)
   flopenl #(.TYPE(statetype)) WalkerStateReg(clk, reset | FlushW, 1'b1, NextWalkerState, IDLE, WalkerState); 
   always_comb 
     case (WalkerState)

src/mmu/mmu.sv

@@ -95,7 +95,7 @@ module mmu import cvw::*;  #(parameter cvw_t P,
   end else begin:tlb // just pass address through as physical
     assign Translate    = 1'b0;
     assign TLBMiss      = 1'b0;
-    assign TLBHit       = 1'b1; // *** is this necessary
+    assign TLBHit       = 1'b0;
     assign TLBPageFault = 1'b0;
     assign PBMemoryType = 2'b00;
   end

src/uncore/clint_apb.sv

@@ -116,7 +116,6 @@ module clint_apb import cvw::*;  #(parameter cvw_t P) (
       if (~PRESETn) begin
         MSIP <= 1'b0;
         MTIMECMP <= '0;
-        // MTIMECMP is not reset ***?
       end else if (memwrite) begin
         if (entry == 16'h0000) MSIP <= PWDATA[0];
         if (entry == 16'h4000) 
@@ -195,7 +194,7 @@ module timereg  import cvw::*;  #(parameter cvw_t P) (
     // Synchronizing this for a read is safe because we are guaranteed to get either the old or the new value.
     // Writing to the counter requires a request/acknowledge handshake to ensure the write value is held long enough.
     // The handshake signals are synchronized in each direction across the interface
-    // There is no back pressure on instructions, so if multiple counter writes occur ***
+    // There is no back pressure on instructions, so if multiple counter writes occur too close together, the results are unpredictable.
 
     logic req, req_sync, ack, we0_stored, we1_stored, ack_stored, resetn_sync;
     logic [P.XLEN-1:0] wd_stored;
@@ -203,7 +202,7 @@ module timereg  import cvw::*;  #(parameter cvw_t P) (
 
     // When a write enable is asserted for a cycle, sample the enables and data and raise a request until it is acknowledged
     // When the acknowledge falls, the transaction is done and the system is ready for another write.
-    // ***look at redoing this assuming write enable and data are held rather than pulsed.
+    // When adding asynchronous timebase, look at redoing this assuming write enable and data are held rather than pulsed.
     always_ff @(posedge PCLK or negedge PRESETn) 
       if (~PRESETn) 
         req <= 0; // don't bother resetting wd

src/uncore/gpio_apb.sv

@@ -86,7 +86,6 @@ module gpio_apb import cvw::*;  #(parameter cvw_t P) (
     if (~PRESETn) begin // asynch reset
       input_en  <= '0;
       output_en <= '0;
-      // *** synch reset not yet implemented [DH: can we delete this comment?  Check if a sync reset is required]
       output_val <= '0;
       rise_ie    <= '0;
       rise_ip    <= '0;

src/uncore/uartPC16550D.sv

@@ -297,7 +297,7 @@ module uartPC16550D #(parameter UART_PRESCALE) (
 
   // ERROR CONDITIONS
   assign rxparity     = ^rxdata;
-  assign rxparityerr  = (rxparity ^ rxparitybit ^ ~evenparitysel) & LCR[3]; // Check even/odd parity (*** check if LCR needs to be inverted)
+  assign rxparityerr  = (rxparity ^ rxparitybit ^ ~evenparitysel) & LCR[3]; // Check even/odd parity
   assign rxoverrunerr = fifoenabled ? (rxfifoentries == 15) : rxdataready; // overrun if FIFO or receive buffer register full 
   assign rxframingerr = ~rxstopbit; // framing error if no stop bit
   assign rxbreak      = rxframingerr & (rxdata9 == 9'b0); // break when 0 for start + data + parity + stop time

testbench/common/instrTrackerTB.sv

@@ -34,5 +34,5 @@ module instrTrackerTB(
   instrNameDecTB ddec(InstrD, InstrDName);
   instrNameDecTB edec(InstrE, InstrEName);
   instrNameDecTB mdec(InstrM, InstrMName);
-  instrNameDecTB wdec(InstrW, InstrWName); // *** delete this because InstrW is deleted from IFU
+  instrNameDecTB wdec(InstrW, InstrWName);
 endmodule

testbench/testbench.sv

@@ -496,9 +496,17 @@ module testbench;
       if (LoadMem) begin
         if (TEST == "buildroot") begin
           memFile = $fopen(bootmemfilename, "rb");
+          if (memFile == 0) begin
+            $display("Error: Could not open file %s", memfilename);
+            $finish;
+          end
           readResult = $fread(dut.uncoregen.uncore.bootrom.bootrom.memory.ROM, memFile);
           $fclose(memFile);
           memFile = $fopen(memfilename, "rb");
+          if (memFile == 0) begin
+            $display("Error: Could not open file %s", memfilename);
+            $finish;
+          end
           readResult = $fread(dut.uncoregen.uncore.ram.ram.memory.ram.RAM, memFile);
           $fclose(memFile);
         end else 
@@ -725,7 +733,7 @@ end
         $display($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
         $fatal;
       end
-    end else begin // for buildroot use the binary instead to load teh reference model.
+    end else begin // for buildroot use the binary instead to load the reference model.
       if (!rvviRefInit("")) begin // still have to call with nothing
         $display($sformatf("%m @ t=%0t: rvviRefInit failed", $time));
         $fatal;
@@ -955,7 +963,7 @@ task automatic updateProgramAddrLabelArray;
       returncode = $fscanf(ProgramAddrMapFP, "%s\n", adrstr);
       if (ProgramAddrLabelArray.exists(label)) ProgramAddrLabelArray[label] = adrstr.atohex();
     end
-  end
+  end 
 
 //  if(ProgramAddrLabelArray["begin_signature"] == 0) $display("Couldn't find begin_signature in %s", ProgramLabelMapFile);
 //  if(ProgramAddrLabelArray["sig_end_canary"] == 0) $display("Couldn't find sig_end_canary in %s", ProgramLabelMapFile);