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Refactor coverage tests to use assembly instead of machine code where possible

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Jordan Carlin 2024-11-06 15:23:34 -08:00
parent 85404bbc5b
commit 4a14f80527
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3 changed files with 13 additions and 25 deletions
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2
tests/coverage/Makefile
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@ -28,7 +28,7 @@ all: $(OBJDUMPS) $(MEMFILES)
# Assemble into object files # Assemble into object files
%.$(OBJEXT): %.$(AEXT) %.$(OBJEXT): %.$(AEXT)
riscv64-unknown-elf-as -g -o $@ -march=rv64gqc_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh -mabi=lp64 $< riscv64-unknown-elf-as -g -o $@ -march=rv64gqc_zcb_zfa_zba_zbb_zbc_zbs_zfh_zicboz_zicbop_zicbom_zbkb_zbkx_zknd_zkne_zknh_svinval -mabi=lp64 $<
# Preprocess assembly files # Preprocess assembly files
%.$(AEXT): %.$(SRCEXT) WALLY-init-lib.h %.$(AEXT): %.$(SRCEXT) WALLY-init-lib.h

34
tests/coverage/ifu.S
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@ -43,35 +43,23 @@ main:
.hword 0x9C41 // line 134 Illegal compressed instruction .hword 0x9C41 // line 134 Illegal compressed instruction
# Zcb coverage tests # Zcb coverage tests
# could restore assembly language versions when GCC supports Zcb
mv s0, sp mv s0, sp
#c.lbu s1, 0(s0) // exercise c.lbu c.lbu s1, 0(s0) // exercise c.lbu
.hword 0x8004 // c.lbu s1, 0(s0) c.lh s1, 0(s0) // exercise c.lh
#c.lh s1, 0(s0) // exercise c.lh c.lhu s1, 0(s0) // exercise c.lhu
.hword 0x8444 // c.lh s1, 0(s0) c.sb s1, 0(s0) // exercise c.sb
#c.lhu s1, 0(s0) // exercise c.lhu c.sh s1, 0(s0) // exercise c.sh
.hword 0x8404 // c.lhu s1, 0(s0)
#c.sb s1, 0(s0) // exercise c.sb
.hword 0x8804 // c.sb s1, 0(s0)
#c.sh s1, 0(s0) // exercise c.sh
.hword 0x8C04 // c.sh s1, 0(s0)
.hword 0x8C44 // Illegal compressed instruction with op = 00, Instr[15:10] = 100011, Instr[6] = 1 and 0's everywhere else. Line 119 illegal instruction .hword 0x8C44 // Illegal compressed instruction with op = 00, Instr[15:10] = 100011, Instr[6] = 1 and 0's everywhere else. Line 119 illegal instruction
.hword 0x9C00 // Illegal compressed instruction with op = 00, Instr[15:10] = 100111, and 0's everywhere else. Line 119 illegal instruction .hword 0x9C00 // Illegal compressed instruction with op = 00, Instr[15:10] = 100111, and 0's everywhere else. Line 119 illegal instruction
li s0, 0xFF li s0, 0xFF
# c.zext.b s0 // exercise c.zext.b c.zext.b s0 // exercise c.zext.b
.hword 0x9C61 // c.zext.b s0 c.sext.b s0 // exercise c.sext.b
# c.sext.b s0 // exercise c.sext.b c.zext.h s0 // exercise c.zext.h
.hword 0x9C65 // c.sext.b s0 c.sext.h s0 // exercise c.sext.h
# c.zext.h s0 // exercise c.zext.h c.zext.w s0 // exercise c.zext.w
.hword 0x9C69 // c.zext.h s0 c.not s0 // exercise c.not
# c.sext.h s0 // exercise c.sext.h
.hword 0x9C6D // c.sext.h s0
# c.zext.w s0 // exercise c.zext.w
.hword 0x9C71 // c.zext.w s0
# c.not s0 // exercise c.not
.hword 0x9C75 // c.not s0
.hword 0x9C7D // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else .hword 0x9C7D // Reserved instruction from line 187 with op = 01, Instr[15:10] = 100111, Instr[6:5] = 11, and 0's everywhere else

2
tests/coverage/priv.S
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@ -304,7 +304,7 @@ sretdone:
li a0, 3 li a0, 3
ecall ecall
# exercise sfence.inval.ir instruction # exercise sfence.inval.ir instruction
.word 0x18100073 sfence.inval.ir
# exercise sret with rs1 not 0 # exercise sret with rs1 not 0
.word 0x102F8073 .word 0x102F8073