mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Team work on solving the dcache data inconsistency problem.
This commit is contained in:
Ross Thompson
parent
ecc9b5006e
commit
49f6eec579
@ -73,7 +73,7 @@
|
|||||||
`define BOOTTIM_RANGE 56'h00000FFF
|
`define BOOTTIM_RANGE 56'h00000FFF
|
||||||
`define TIM_SUPPORTED 1'b1
|
`define TIM_SUPPORTED 1'b1
|
||||||
`define TIM_BASE 56'h80000000
|
`define TIM_BASE 56'h80000000
|
||||||
`define TIM_RANGE 56'h07FFFFFF
|
`define TIM_RANGE 56'h0007FFFF
|
||||||
`define CLINT_SUPPORTED 1'b1
|
`define CLINT_SUPPORTED 1'b1
|
||||||
`define CLINT_BASE 56'h02000000
|
`define CLINT_BASE 56'h02000000
|
||||||
`define CLINT_RANGE 56'h0000FFFF
|
`define CLINT_RANGE 56'h0000FFFF
|
||||||
|
|||||||
@ -7,37 +7,37 @@ add wave -noupdate -expand -group {Execution Stage} /testbench/FunctionName/Func
|
|||||||
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
|
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/PCE
|
||||||
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
|
add wave -noupdate -expand -group {Execution Stage} /testbench/InstrEName
|
||||||
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
|
add wave -noupdate -expand -group {Execution Stage} /testbench/dut/hart/ifu/InstrE
|
||||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
|
||||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
|
||||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
|
||||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
|
||||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
|
||||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
|
||||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
|
||||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
|
||||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
|
||||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
|
||||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
|
||||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
|
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
|
||||||
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
|
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
|
||||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
|
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/BPPredWrongE
|
||||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
|
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
|
||||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
|
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/RetM
|
||||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
|
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/TrapM
|
||||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
|
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/LoadStallD
|
||||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
|
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/ICacheStallF
|
||||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall
|
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/hzu/DCacheStall
|
||||||
add wave -noupdate -expand -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
|
add wave -noupdate -group HDU -expand -group hazards /testbench/dut/hart/MulDivStallD
|
||||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
|
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
|
||||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
|
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushD
|
||||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
|
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushE
|
||||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
|
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushM
|
||||||
add wave -noupdate -expand -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
|
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/hart/FlushW
|
||||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
|
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
|
||||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
|
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
|
||||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
|
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
|
||||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
|
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
|
||||||
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
|
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
|
||||||
add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
|
add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
|
||||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
|
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
|
||||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
|
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
|
||||||
@ -118,18 +118,18 @@ add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart
|
|||||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
|
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
|
||||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
|
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
|
||||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
|
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
|
||||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a
|
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
|
||||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b
|
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
|
||||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
|
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
|
||||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/result
|
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/result
|
||||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/flags
|
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/flags
|
||||||
add wave -noupdate -expand -group alu -divider internals
|
add wave -noupdate -group alu -divider internals
|
||||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/overflow
|
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/overflow
|
||||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/carry
|
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/carry
|
||||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/zero
|
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/zero
|
||||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/neg
|
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/neg
|
||||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/lt
|
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/lt
|
||||||
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/ltu
|
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/ltu
|
||||||
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
|
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1D
|
||||||
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
|
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs2D
|
||||||
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
|
add wave -noupdate -group Forward /testbench/dut/hart/ieu/fw/Rs1E
|
||||||
@ -258,31 +258,29 @@ add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cach
|
|||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -expand -group Way0Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[0]/MemWay/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirtyWay
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimDirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/MemRWM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/DTLBMissM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/MemAdrM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/MemAdrM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/MemAdrM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/PCF
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/pagetablewalker/PCF
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct3M
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/Funct7M
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/AtomicM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemAdrE
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} -expand -group adr /testbench/dut/hart/lsu/dcache/MemPAdrM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/WriteDataM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/ReadDataW
|
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {CPU side} /testbench/dut/hart/lsu/dcache/DCacheStall
|
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/WayHit
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/WayHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status -color {Medium Orchid} /testbench/dut/hart/lsu/dcache/CacheHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW
|
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group status /testbench/dut/hart/lsu/dcache/SRAMWordWriteEnableW
|
||||||
@ -392,11 +390,34 @@ add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/TLBHit
|
|||||||
add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress
|
add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/VirtualAddress
|
||||||
add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
|
add wave -noupdate -group dtlb /testbench/dut/hart/lsu/dmmu/PhysicalAddress
|
||||||
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
add wave -noupdate -group itlb /testbench/dut/hart/ifu/ITLBMissF
|
||||||
|
add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268436996]}
|
||||||
|
add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268436997]}
|
||||||
|
add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268436998]}
|
||||||
|
add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268436999]}
|
||||||
|
add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268437000]}
|
||||||
|
add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268437011]}
|
||||||
|
add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268437012]}
|
||||||
|
add wave -noupdate {/testbench/dut/uncore/dtim/RAM[268437268]}
|
||||||
|
add wave -noupdate /testbench/dut/uncore/dtim/RAM
|
||||||
|
add wave -noupdate /testbench/dut/uncore/dtim/A
|
||||||
|
add wave -noupdate /testbench/dut/uncore/dtim/HWDATA
|
||||||
|
add wave -noupdate /testbench/dut/uncore/dtim/memwrite
|
||||||
|
add wave -noupdate /testbench/dut/uncore/dtim/memread
|
||||||
|
add wave -noupdate /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
|
||||||
|
add wave -noupdate /testbench/dut/uncore/dtim/HCLK
|
||||||
|
add wave -noupdate /testbench/dut/hart/clk
|
||||||
|
add wave -noupdate /testbench/DCacheFlushFSM/CacheData
|
||||||
|
add wave -noupdate /testbench/DCacheFlushFSM/ShadowRAM
|
||||||
|
add wave -noupdate /testbench/DCacheFlushFSM/CacheAdr
|
||||||
|
add wave -noupdate /testbench/DCacheFlushFSM/CacheData
|
||||||
|
add wave -noupdate /testbench/DCacheFlushFSM/CacheDirty
|
||||||
|
add wave -noupdate /testbench/DCacheFlushFSM/CacheTag
|
||||||
|
add wave -noupdate /testbench/DCacheFlushFSM/CacheValid
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 12} {57781 ns} 0} {{Cursor 13} {7061 ns} 0}
|
WaveRestoreCursors {{Cursor 12} {63874 ns} 0} {{Cursor 13} {4851 ns} 0} {{Cursor 3} {58080 ns} 0}
|
||||||
quietly wave cursor active 1
|
quietly wave cursor active 1
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 273
|
configure wave -valuecolwidth 297
|
||||||
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
||||||
configure wave -signalnamewidth 1
|
configure wave -signalnamewidth 1
|
||||||
configure wave -snapdistance 10
|
configure wave -snapdistance 10
|
||||||
@ -409,4 +430,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {57704 ns} {58248 ns}
|
WaveRestoreZoom {0 ns} {67394 ns}
|
||||||
|
|||||||
1
wally-pipelined/src/cache/dcache.sv
vendored
1
wally-pipelined/src/cache/dcache.sv
vendored
@ -516,6 +516,7 @@ module dcache
|
|||||||
DCacheStall = 1'b1;
|
DCacheStall = 1'b1;
|
||||||
PreCntEn = 1'b1;
|
PreCntEn = 1'b1;
|
||||||
AHBWrite = 1'b1;
|
AHBWrite = 1'b1;
|
||||||
|
SelAdrM = 1'b1;
|
||||||
if( FetchCountFlag & AHBAck) begin
|
if( FetchCountFlag & AHBAck) begin
|
||||||
NextState = STATE_MISS_WRITE_CACHE_BLOCK;
|
NextState = STATE_MISS_WRITE_CACHE_BLOCK;
|
||||||
end else begin
|
end else begin
|
||||||
|
|||||||
@ -630,10 +630,14 @@ string tests32f[] = '{
|
|||||||
// check results
|
// check results
|
||||||
always @(negedge clk)
|
always @(negedge clk)
|
||||||
begin
|
begin
|
||||||
if (DCacheFlushDone) begin
|
if (dut.hart.priv.EcallFaultM &&
|
||||||
|
(dut.hart.ieu.dp.regf.rf[3] == 1 ||
|
||||||
|
(dut.hart.ieu.dp.regf.we3 &&
|
||||||
|
dut.hart.ieu.dp.regf.a3 == 3 &&
|
||||||
|
dut.hart.ieu.dp.regf.wd3 == 1))) begin
|
||||||
$display("Code ended with ecall with gp = 1");
|
$display("Code ended with ecall with gp = 1");
|
||||||
|
|
||||||
#60; // give time for instructions in pipeline to finish
|
#600; // give time for instructions in pipeline to finish
|
||||||
// clear signature to prevent contamination from previous tests
|
// clear signature to prevent contamination from previous tests
|
||||||
for(i=0; i<SIGNATURESIZE; i=i+1) begin
|
for(i=0; i<SIGNATURESIZE; i=i+1) begin
|
||||||
sig32[i] = 'bx;
|
sig32[i] = 'bx;
|
||||||
@ -666,13 +670,16 @@ string tests32f[] = '{
|
|||||||
/* verilator lint_off INFINITELOOP */
|
/* verilator lint_off INFINITELOOP */
|
||||||
while (signature[i] !== 'bx) begin
|
while (signature[i] !== 'bx) begin
|
||||||
//$display("signature[%h] = %h", i, signature[i]);
|
//$display("signature[%h] = %h", i, signature[i]);
|
||||||
if (signature[i] !== dut.uncore.dtim.RAM[testadr+i]) begin
|
if (signature[i] !== dut.uncore.dtim.RAM[testadr+i] &&
|
||||||
|
(signature[i] !== DCacheFlushFSM.ShadowRAM[testadr+i])) begin
|
||||||
if (signature[i+4] !== 'bx || signature[i] !== 32'hFFFFFFFF) begin
|
if (signature[i+4] !== 'bx || signature[i] !== 32'hFFFFFFFF) begin
|
||||||
// report errors unless they are garbage at the end of the sim
|
// report errors unless they are garbage at the end of the sim
|
||||||
// kind of hacky test for garbage right now
|
// kind of hacky test for garbage right now
|
||||||
errors = errors+1;
|
errors = errors+1;
|
||||||
$display(" Error on test %s result %d: adr = %h sim = %h, signature = %h",
|
$display(" Error on test %s result %d: adr = %h sim = %h, signature = %h",
|
||||||
tests[test], i, (testadr+i)*(`XLEN/8), dut.uncore.dtim.RAM[testadr+i], signature[i]);
|
tests[test], i, (testadr+i)*(`XLEN/8), dut.uncore.dtim.RAM[testadr+i], signature[i]);
|
||||||
|
$display(" Error on test %s result %d: adr = %h sim = %h, signature = %h",
|
||||||
|
tests[test], i, (testadr+i)*(`XLEN/8), DCacheFlushFSM.ShadowRAM[testadr+i], signature[i]);
|
||||||
$stop;//***debug
|
$stop;//***debug
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
@ -996,83 +1003,47 @@ module DCacheFlushFSM
|
|||||||
localparam integer tagstart = lognumlines + logblockbytelen;
|
localparam integer tagstart = lognumlines + logblockbytelen;
|
||||||
|
|
||||||
|
|
||||||
typedef enum {IDLE,
|
|
||||||
READ,
|
|
||||||
DONE} statetype;
|
|
||||||
|
|
||||||
statetype CurrState, NextState;
|
genvar index, way, cacheWord;
|
||||||
|
logic [`XLEN-1:0] CacheData [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||||
|
logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0];
|
||||||
|
logic CacheValid [numways-1:0] [numlines-1:0];
|
||||||
|
logic CacheDirty [numways-1:0] [numlines-1:0];
|
||||||
|
|
||||||
logic CountFlag;
|
logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0];
|
||||||
logic CntEn;
|
genvar adr;
|
||||||
|
|
||||||
logic [lognumways + lognumlines - 1 : 0] count, countNext;
|
logic [`XLEN-1:0] ShadowRAM[`TIM_BASE>>(1+`XLEN/32):(`TIM_RANGE+`TIM_BASE)>>1+(`XLEN/32)];
|
||||||
|
|
||||||
flopenr #(lognumlines + lognumways)
|
generate
|
||||||
FetchCountReg(.clk(clk),
|
for(index = 0; index < numlines; index++) begin
|
||||||
.reset(reset),
|
for(way = 0; way < numways; way++) begin
|
||||||
.en(CntEn),
|
assign CacheTag[way][index] = testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.CacheTagMem.StoredData[index];
|
||||||
.d(countNext),
|
assign CacheValid[way][index] = testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.ValidBits[index];
|
||||||
.q(count));
|
assign CacheDirty[way][index] = testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.DirtyBits[index];
|
||||||
|
for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
|
||||||
assign countNext = count + 1;
|
assign CacheData[way][index][cacheWord] = testbench.dut.hart.lsu.dcache.CacheWays[way].MemWay.word[cacheWord].CacheDataMem.StoredData[index];
|
||||||
assign CountFlag = count == '1;
|
assign CacheAdr[way][index][cacheWord] = ((CacheTag[way][index] << tagstart) + (index << logblockbytelen) + (cacheWord << $clog2(`XLEN/8)));
|
||||||
|
|
||||||
always_ff @(posedge clk, posedge reset) begin
|
|
||||||
if(reset) CurrState = IDLE;
|
|
||||||
else CurrState = NextState;
|
|
||||||
end
|
|
||||||
|
|
||||||
integer adr;
|
|
||||||
integer tag;
|
|
||||||
integer index;
|
|
||||||
integer way;
|
|
||||||
integer word;
|
|
||||||
logic dirty, valid;
|
|
||||||
logic [`XLEN-1:0] data;
|
|
||||||
|
|
||||||
always_comb begin
|
|
||||||
case (CurrState)
|
|
||||||
IDLE: if(start) NextState = READ;
|
|
||||||
else NextState = IDLE;
|
|
||||||
READ: begin
|
|
||||||
force testbench.dut.hart.lsu.dcache.SRAMAdr = count;
|
|
||||||
index = count / numways;
|
|
||||||
way = count % numways;
|
|
||||||
tag = testbench.dut.hart.lsu.dcache.ReadTag[way];
|
|
||||||
dirty = testbench.dut.hart.lsu.dcache.Dirty[way];
|
|
||||||
valid = testbench.dut.hart.lsu.dcache.Valid[way];
|
|
||||||
adr = (tag << tagstart) + (index << logblockbytelen);
|
|
||||||
data = testbench.dut.hart.lsu.dcache.FinalReadDataWordM;
|
|
||||||
if (valid & dirty) begin
|
|
||||||
$display("Index Way Tag V D %03x %d %016x %d %d %016x %016x", index, way, tag, valid, dirty, adr, data);
|
|
||||||
force dut.uncore.dtim.A = adr;
|
|
||||||
force dut.uncore.dtim.HWDATA = data;
|
|
||||||
force dut.uncore.dtim.memwrite = 1;
|
|
||||||
force dut.uncore.dtim.risingHREADYTim = 1;
|
|
||||||
end
|
|
||||||
|
|
||||||
if(CountFlag) begin
|
|
||||||
NextState = DONE;
|
|
||||||
end else begin
|
|
||||||
NextState = READ;
|
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
DONE: begin
|
end
|
||||||
release testbench.dut.hart.lsu.dcache.SRAMAdr;
|
endgenerate
|
||||||
release dut.uncore.dtim.A;
|
|
||||||
release dut.uncore.dtim.HWDATA;
|
integer i, j, k;
|
||||||
release dut.uncore.dtim.memwrite;
|
|
||||||
release dut.uncore.dtim.risingHREADYTim;
|
always @(posedge clk) begin
|
||||||
NextState = DONE;
|
if (start) begin #1
|
||||||
|
for(i = 0; i < numlines; i++) begin
|
||||||
|
for(j = 0; j < numways; j++) begin
|
||||||
|
for(k = 0; k < numwords; k++) begin
|
||||||
|
$display("Help me!")
|
||||||
|
ShadowRAM[CacheAdr[j][i][k]] = CacheData[j][i][k];
|
||||||
|
end
|
||||||
|
end
|
||||||
end
|
end
|
||||||
default: NextState = IDLE;
|
end
|
||||||
endcase
|
|
||||||
end
|
end
|
||||||
|
|
||||||
assign done = CurrState == DONE;
|
|
||||||
assign CntEn = CurrState == READ;
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
endmodule
|
endmodule
|
||||||
@ -1168,19 +1139,19 @@ task FlushDCache;
|
|||||||
|
|
||||||
assign value = testbench.dut.hart.lsu.dcache.CacheWays[0].MemWay.word[0].CacheDataMem.StoredData[0];
|
assign value = testbench.dut.hart.lsu.dcache.CacheWays[0].MemWay.word[0].CacheDataMem.StoredData[0];
|
||||||
|
|
||||||
for(index = 0; index < numlines; index++) begin
|
for(index = 0; index < numlines; index++) begin
|
||||||
for(way = 0; way < numways; way++) begin
|
for(way = 0; way < numways; way++) begin
|
||||||
for(word = 0; word < numwords; word++) begin
|
for(word = 0; word < numwords; word++) begin
|
||||||
assign CacheData = testbench.dut.hart.lsu.dcache.CacheWays[0].MemWay.word[0].CacheDataMem.StoredData[index];
|
assign CacheData = testbench.dut.hart.lsu.dcache.CacheWays[0].MemWay.word[0].CacheDataMem.StoredData[index];
|
||||||
|
|
||||||
path = $sformatf(GenericCacheDataMem, way, word, index);
|
path = $sformatf(GenericCacheDataMem, way, word, index);
|
||||||
// I guess you cannot do this conversion.
|
// I guess you cannot do this conversion.
|
||||||
//assign CacheData = path;
|
//assign CacheData = path;
|
||||||
$display("%x", path);
|
$display("%x", path);
|
||||||
$display(CacheData);
|
$display(CacheData);
|
||||||
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
end
|
|
||||||
|
|
||||||
$display("%x", value);
|
$display("%x", value);
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user