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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Set associate icache working, but way 0 is never written.
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05455f8392
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@ -57,10 +57,10 @@
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// Cache configuration. Sizes should be a power of two
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// Cache configuration. Sizes should be a power of two
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// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks
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// typical configuration 4 ways, 4096 bytes per way, 256 bit or more blocks
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`define DCACHE_NUMWAYS 4
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`define DCACHE_NUMWAYS 4
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`define DCACHE_WAYSIZEINBYTES 2048
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`define DCACHE_WAYSIZEINBYTES 4096
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`define DCACHE_BLOCKLENINBITS 256
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`define DCACHE_BLOCKLENINBITS 256
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`define DCACHE_REPLBITS 3
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`define DCACHE_REPLBITS 3
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`define ICACHE_NUMWAYS 1
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`define ICACHE_NUMWAYS 4
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`define ICACHE_WAYSIZEINBYTES 4096
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`define ICACHE_WAYSIZEINBYTES 4096
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`define ICACHE_BLOCKLENINBITS 256
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`define ICACHE_BLOCKLENINBITS 256
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13
wally-pipelined/src/cache/icache.sv
vendored
13
wally-pipelined/src/cache/icache.sv
vendored
@ -70,7 +70,7 @@ module icache
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localparam OFFSETWIDTH = $clog2(BlockByteLength);
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localparam OFFSETWIDTH = $clog2(BlockByteLength);
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localparam integer PA_WIDTH = `PA_BITS - 2;
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localparam integer PA_WIDTH = `PA_BITS - 2;
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localparam integer NUMWAYS = 4;
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localparam integer NUMWAYS = `ICACHE_NUMWAYS;
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// Input signals to cache memory
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// Input signals to cache memory
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@ -118,6 +118,8 @@ module icache
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logic [OFFSETLEN-1:0] BasePAdrOffsetF;
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logic [OFFSETLEN-1:0] BasePAdrOffsetF;
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logic [NUMWAYS-1:0] SRAMWayWriteEnable;
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// on spill we want to get the first 2 bytes of the next cache block.
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// on spill we want to get the first 2 bytes of the next cache block.
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// the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can
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// the spill only occurs if the PCPF mod BlockByteLength == -2. Therefore we can
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@ -139,9 +141,9 @@ module icache
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.reset,
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.reset,
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.RAdr(RAdr),
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.RAdr(RAdr),
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.PAdr(PCTagF),
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.PAdr(PCTagF),
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.WriteEnable(ICacheMemWriteEnable), // *** connect
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.WriteEnable(SRAMWayWriteEnable),
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.WriteWordEnable('1),
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.WriteWordEnable('1),
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.TagWriteEnable(ICacheMemWriteEnable), // *** connect
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.TagWriteEnable(SRAMWayWriteEnable),
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.WriteData(ICacheMemWriteData),
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.WriteData(ICacheMemWriteData),
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.SetValid(ICacheMemWriteEnable),
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.SetValid(ICacheMemWriteEnable),
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.ClearValid(1'b0),
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.ClearValid(1'b0),
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@ -274,6 +276,8 @@ module icache
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// truncate the offset from PCPF for memory address generation
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// truncate the offset from PCPF for memory address generation
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assign SRAMWayWriteEnable = ICacheMemWriteEnable ? VictimWay : '0;
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icachefsm #(.BLOCKLEN(BLOCKLEN))
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icachefsm #(.BLOCKLEN(BLOCKLEN))
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controller(.clk,
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controller(.clk,
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.reset,
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.reset,
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@ -293,7 +297,8 @@ module icache
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.CntEn,
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.CntEn,
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.CntReset,
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.CntReset,
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.SelAdr,
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.SelAdr,
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.SavePC
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.SavePC,
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.LRUWriteEn
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);
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);
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// For now, assume no writes to executable memory
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// For now, assume no writes to executable memory
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17
wally-pipelined/src/cache/icachefsm.sv
vendored
17
wally-pipelined/src/cache/icachefsm.sv
vendored
@ -61,7 +61,8 @@ module icachefsm #(parameter BLOCKLEN = 256)
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output logic CntEn,
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output logic CntEn,
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output logic CntReset,
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output logic CntReset,
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output logic [1:0] SelAdr,
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output logic [1:0] SelAdr,
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output logic SavePC
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output logic SavePC,
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output logic LRUWriteEn
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);
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);
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// FSM states
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// FSM states
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@ -134,7 +135,7 @@ module icachefsm #(parameter BLOCKLEN = 256)
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ICacheReadEn = 1'b0;
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ICacheReadEn = 1'b0;
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SavePC = 1'b0;
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SavePC = 1'b0;
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ICacheStallF = 1'b1;
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ICacheStallF = 1'b1;
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LRUWriteEn = 1'b0;
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case (CurrState)
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case (CurrState)
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STATE_READY: begin
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STATE_READY: begin
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SelAdr = 2'b00;
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SelAdr = 2'b00;
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@ -144,6 +145,7 @@ module icachefsm #(parameter BLOCKLEN = 256)
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end else if (hit & ~spill) begin
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end else if (hit & ~spill) begin
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SavePC = 1'b1;
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SavePC = 1'b1;
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ICacheStallF = 1'b0;
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ICacheStallF = 1'b0;
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LRUWriteEn = 1'b1;
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if(StallF) begin
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if(StallF) begin
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NextState = STATE_CPU_BUSY;
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NextState = STATE_CPU_BUSY;
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SelAdr = 2'b01;
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SelAdr = 2'b01;
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@ -153,7 +155,8 @@ module icachefsm #(parameter BLOCKLEN = 256)
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end else if (hit & spill) begin
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end else if (hit & spill) begin
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spillSave = 1'b1;
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spillSave = 1'b1;
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SelAdr = 2'b10;
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SelAdr = 2'b10;
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NextState = STATE_HIT_SPILL;
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LRUWriteEn = 1'b1;
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NextState = STATE_HIT_SPILL;
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end else if (~hit & ~spill) begin
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end else if (~hit & ~spill) begin
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CntReset = 1'b1;
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CntReset = 1'b1;
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NextState = STATE_MISS_FETCH_WDV;
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NextState = STATE_MISS_FETCH_WDV;
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@ -209,6 +212,8 @@ module icachefsm #(parameter BLOCKLEN = 256)
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UnalignedSelect = 1'b1;
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UnalignedSelect = 1'b1;
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SavePC = 1'b1;
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SavePC = 1'b1;
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ICacheStallF = 1'b0;
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ICacheStallF = 1'b0;
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LRUWriteEn = 1'b1;
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if(StallF) begin
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if(StallF) begin
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NextState = STATE_CPU_BUSY_SPILL;
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NextState = STATE_CPU_BUSY_SPILL;
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SelAdr = 2'b10;
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SelAdr = 2'b10;
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@ -242,6 +247,7 @@ module icachefsm #(parameter BLOCKLEN = 256)
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//SelAdr = 2'b01;
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//SelAdr = 2'b01;
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ICacheReadEn = 1'b1;
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ICacheReadEn = 1'b1;
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ICacheStallF = 1'b0;
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ICacheStallF = 1'b0;
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LRUWriteEn = 1'b1;
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if(StallF) begin
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if(StallF) begin
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SelAdr = 2'b01;
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SelAdr = 2'b01;
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NextState = STATE_CPU_BUSY;
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NextState = STATE_CPU_BUSY;
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@ -268,7 +274,8 @@ module icachefsm #(parameter BLOCKLEN = 256)
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end
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end
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STATE_MISS_SPILL_READ1: begin // always be a hit as we just wrote that cache block.
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STATE_MISS_SPILL_READ1: begin // always be a hit as we just wrote that cache block.
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SelAdr = 2'b01; // there is a 1 cycle delay after setting the address before the date arrives.
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SelAdr = 2'b01; // there is a 1 cycle delay after setting the address before the date arrives.
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ICacheReadEn = 1'b1;
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ICacheReadEn = 1'b1;
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LRUWriteEn = 1'b1;
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NextState = STATE_MISS_SPILL_2;
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NextState = STATE_MISS_SPILL_2;
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end
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end
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STATE_MISS_SPILL_2: begin
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STATE_MISS_SPILL_2: begin
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@ -288,6 +295,7 @@ module icachefsm #(parameter BLOCKLEN = 256)
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UnalignedSelect = 1'b1;
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UnalignedSelect = 1'b1;
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SavePC = 1'b1;
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SavePC = 1'b1;
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ICacheStallF = 1'b0;
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ICacheStallF = 1'b0;
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LRUWriteEn = 1'b1;
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if(StallF) begin
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if(StallF) begin
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NextState = STATE_CPU_BUSY;
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NextState = STATE_CPU_BUSY;
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SelAdr = 2'b01;
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SelAdr = 2'b01;
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@ -323,6 +331,7 @@ module icachefsm #(parameter BLOCKLEN = 256)
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UnalignedSelect = 1'b1;
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UnalignedSelect = 1'b1;
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SavePC = 1'b1;
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SavePC = 1'b1;
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ICacheStallF = 1'b0;
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ICacheStallF = 1'b0;
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LRUWriteEn = 1'b1;
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if(StallF) begin
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if(StallF) begin
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NextState = STATE_CPU_BUSY_SPILL;
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NextState = STATE_CPU_BUSY_SPILL;
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SelAdr = 2'b10;
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SelAdr = 2'b10;
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