From 498388c63699996f069d015aee7bfb05c372bd25 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Tue, 8 Feb 2022 17:52:09 -0600 Subject: [PATCH] Cache cleanup write enables. --- pipelined/src/cache/cache.sv | 46 ++++++++++++++------------------- pipelined/src/cache/cachefsm.sv | 19 +++++++++----- pipelined/src/cache/cacheway.sv | 30 +++++++++++++++------ 3 files changed, 53 insertions(+), 42 deletions(-) diff --git a/pipelined/src/cache/cache.sv b/pipelined/src/cache/cache.sv index f70467f4a..1ddb53f23 100644 --- a/pipelined/src/cache/cache.sv +++ b/pipelined/src/cache/cache.sv @@ -62,7 +62,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( localparam LINEBYTELEN = LINELEN/8; localparam OFFSETLEN = $clog2(LINEBYTELEN); localparam SETLEN = $clog2(NUMLINES); - localparam SETTOP = SETLEN+OFFSETLEN; + localparam SETTOP = SETLEN+OFFSETLEN; localparam TAGLEN = `PA_BITS - SETTOP; localparam WORDSPERLINE = LINELEN/`XLEN; localparam LOGWPL = $clog2(WORDSPERLINE); @@ -77,12 +77,9 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( logic [LINELEN-1:0] ReadDataLineWay [NUMWAYS-1:0]; logic [NUMWAYS-1:0] WayHit; logic CacheHit; - logic [WORDSPERLINE-1:0] SRAMWordEnable; - logic SRAMWordWriteEnable; - logic SRAMLineWriteEnable; + logic FSMWordWriteEn; + logic FSMLineWriteEn; logic [NUMWAYS-1:0] SRAMLineWayWriteEnable; - logic [NUMWAYS-1:0] SRAMWayWriteEnable; - logic [NUMWAYS-1:0] SRAMWordWayWriteEnable; logic [NUMWAYS-1:0] VictimWay; logic [NUMWAYS-1:0] VictimDirtyWay; logic VictimDirty; @@ -106,7 +103,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( logic [NUMWAYS-1:0] WayHitSaved, WayHitRaw; logic [LINELEN-1:0] ReadDataLineRaw, ReadDataLineSaved; logic [NUMWAYS-1:0] SelectedWay; - logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay; + logic [NUMWAYS-1:0] SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay; + logic [NUMWAYS-1:0] WriteWordWayEn, WriteLineWayEn; ///////////////////////////////////////////////////////////////////////////////////////////// // Read Path @@ -121,9 +119,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN) CacheWays[NUMWAYS-1:0]( .clk, .reset, .RAdr, .PAdr, - .SRAMWayWriteEnable, - .SRAMWordEnable, - .TagWriteEnable(SRAMLineWayWriteEnable), + .WriteWordEn(WriteWordWayEn), + .WriteLineEn(WriteLineWayEn), .WriteData(SRAMWriteData), .SetValid(SetValidWay), .ClearValid(ClearValidWay), .SetDirty(SetDirtyWay), .ClearDirty(ClearDirtyWay), .SelEvict, .Victim(VictimWay), .Flush(FlushWay), @@ -153,22 +150,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( end else assign WayHit = WayHitRaw; ///////////////////////////////////////////////////////////////////////////////////////////// - // Write Path: Write Enables + // Write Path: Write data and address. Muxes between writes from bus and writes from CPU. ///////////////////////////////////////////////////////////////////////////////////////////// - - // *** Ross considering restructuring - // move decoder and wordwritenable into cacheway. - onehotdecoder #(LOGWPL) adrdec( - .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded)); - assign SRAMWordEnable = SRAMLineWriteEnable ? '1 : MemPAdrDecoded; // OR - - assign SRAMLineWayWriteEnable = SRAMLineWriteEnable ? VictimWay : '0; // AND - assign SRAMWordWayWriteEnable = SRAMWordWriteEnable ? WayHit : '0; // AND - mux2 #(NUMWAYS) WriteEnableMux(.d0(SRAMWordWayWriteEnable), .d1(VictimWay), - .s(SRAMLineWriteEnable), .y(SRAMWayWriteEnable)); mux2 #(LINELEN) WriteDataMux(.d0({WORDSPERLINE{FinalWriteData}}), - .d1(CacheMemWriteData), .s(SRAMLineWriteEnable), .y(SRAMWriteData)); + .d1(CacheMemWriteData), .s(FSMLineWriteEn), .y(SRAMWriteData)); mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d1({VictimTag, PAdr[SETTOP-1:OFFSETLEN], {{OFFSETLEN}{1'b0}}}), .d2({VictimTag, FlushAdr, {{OFFSETLEN}{1'b0}}}), @@ -192,11 +178,17 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( assign FlushWayFlag = FlushWay[NUMWAYS-1]; assign NextFlushWay = {FlushWay[NUMWAYS-2:0], FlushWay[NUMWAYS-1]}; - assign SelectedWay = SelFlush ? FlushWay : (SRAMLineWriteEnable ? VictimWay : WayHit); + ///////////////////////////////////////////////////////////////////////////////////////////// + // Write Path: Write Enables + ///////////////////////////////////////////////////////////////////////////////////////////// + + assign SelectedWay = SelFlush ? FlushWay : (FSMLineWriteEn ? VictimWay : WayHit); assign SetValidWay = SetValid ? SelectedWay : '0; assign ClearValidWay = ClearValid ? SelectedWay : '0; assign SetDirtyWay = SetDirty ? SelectedWay : '0; - assign ClearDirtyWay = ClearDirty ? SelectedWay : '0; + assign ClearDirtyWay = ClearDirty ? SelectedWay : '0; + assign WriteWordWayEn = FSMWordWriteEn ? SelectedWay : '0; + assign WriteLineWayEn = FSMLineWriteEn ? SelectedWay : '0; ///////////////////////////////////////////////////////////////////////////////////////////// @@ -207,8 +199,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, DCACHE = 1) ( .RW, .Atomic, .CPUBusy, .IgnoreRequest, .CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, .CacheMiss, .CacheAccess, .SelAdr, .SetValid, - .ClearValid, .SetDirty, .ClearDirty, .SRAMWordWriteEnable, - .SRAMLineWriteEnable, .SelEvict, .SelFlush, + .ClearValid, .SetDirty, .ClearDirty, .FSMWordWriteEn, + .FSMLineWriteEn, .SelEvict, .SelFlush, .FlushAdrCntEn, .FlushWayCntEn, .FlushAdrCntRst, .FlushWayCntRst, .FlushAdrFlag, .FlushWayFlag, .FlushCache, .save, .restore, diff --git a/pipelined/src/cache/cachefsm.sv b/pipelined/src/cache/cachefsm.sv index 63c452862..3947309bf 100644 --- a/pipelined/src/cache/cachefsm.sv +++ b/pipelined/src/cache/cachefsm.sv @@ -65,8 +65,8 @@ module cachefsm output logic ClearValid, output logic SetDirty, output logic ClearDirty, - output logic SRAMWordWriteEnable, - output logic SRAMLineWriteEnable, + output logic FSMWordWriteEn, + output logic FSMLineWriteEn, output logic SelEvict, output logic LRUWriteEn, output logic SelFlush, @@ -174,6 +174,7 @@ module cachefsm endcase end + // com back to CPU assign CacheCommitted = CurrState != STATE_READY; assign CacheStall = (CurrState == STATE_READY & (DoFlush | DoAMOMiss | DoReadMiss | DoWriteMiss)) | (CurrState == STATE_MISS_FETCH_WDV) | @@ -186,6 +187,7 @@ module cachefsm (CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK) | (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag)); + // write enables internal to cache assign SetValid = CurrState == STATE_MISS_WRITE_CACHE_LINE; assign ClearValid = '0; assign SetDirty = (CurrState == STATE_READY & DoAMO) | @@ -194,14 +196,15 @@ module cachefsm (CurrState == STATE_MISS_WRITE_WORD); assign ClearDirty = (CurrState == STATE_MISS_WRITE_CACHE_LINE) | (CurrState == STATE_FLUSH_CLEAR_DIRTY); - assign SRAMWordWriteEnable = (CurrState == STATE_READY & (DoAMOHit | DoWriteHit)) | - (CurrState == STATE_MISS_READ_WORD_DELAY & DoAMO) | - (CurrState == STATE_MISS_WRITE_WORD); - assign SRAMLineWriteEnable = (CurrState == STATE_MISS_WRITE_CACHE_LINE); - assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY); + assign FSMWordWriteEn = (CurrState == STATE_READY & (DoAMOHit | DoWriteHit)) | + (CurrState == STATE_MISS_READ_WORD_DELAY & DoAMO) | + (CurrState == STATE_MISS_WRITE_WORD); + assign FSMLineWriteEn = (CurrState == STATE_MISS_WRITE_CACHE_LINE); assign LRUWriteEn = (CurrState == STATE_READY & (DoAMOHit | DoReadHit | DoWriteHit)) | (CurrState == STATE_MISS_READ_WORD_DELAY) | (CurrState == STATE_MISS_WRITE_WORD); + // Flush and eviction controls + assign SelEvict = (CurrState == STATE_MISS_EVICT_DIRTY); assign SelFlush = (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_CHECK) | (CurrState == STATE_FLUSH_INCR) | (CurrState == STATE_FLUSH_WRITE_BACK) | (CurrState == STATE_FLUSH_CLEAR_DIRTY); @@ -211,9 +214,11 @@ module cachefsm (CurrState == STATE_FLUSH_CLEAR_DIRTY & ~(FlushFlag)); assign FlushAdrCntRst = (CurrState == STATE_READY & DoFlush); assign FlushWayCntRst = (CurrState == STATE_READY & DoFlush) | (CurrState == STATE_FLUSH_INCR); + // Bus interface controls assign CacheFetchLine = (CurrState == STATE_READY & (DoAMOMiss | DoWriteMiss | DoReadMiss)); assign CacheWriteLine = (CurrState == STATE_MISS_FETCH_DONE & VictimDirty) | (CurrState == STATE_FLUSH_CHECK & VictimDirty); + // handle cpu stall. assign restore = ((CurrState == STATE_CPU_BUSY) | (CurrState == STATE_CPU_BUSY_FINISH_AMO)) & ~`REPLAY; assign save = ((CurrState == STATE_READY & (DoAMOHit | DoReadHit | DoWriteHit) & CPUBusy) | (CurrState == STATE_MISS_READ_WORD_DELAY & (DoAMO | DoRead) & CPUBusy) | diff --git a/pipelined/src/cache/cacheway.sv b/pipelined/src/cache/cacheway.sv index 09fcbfa29..cb53a8160 100644 --- a/pipelined/src/cache/cacheway.sv +++ b/pipelined/src/cache/cacheway.sv @@ -37,9 +37,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, input logic [$clog2(NUMLINES)-1:0] RAdr, input logic [`PA_BITS-1:0] PAdr, - input logic SRAMWayWriteEnable, - input logic [LINELEN/`XLEN-1:0] SRAMWordEnable, - input logic TagWriteEnable, + input logic WriteWordEn, + input logic WriteLineEn, input logic [LINELEN-1:0] WriteData, input logic SetValid, input logic ClearValid, @@ -56,6 +55,10 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, output logic VictimDirty, output logic [TAGLEN-1:0] VictimTag); + localparam WORDSPERLINE = LINELEN/`XLEN; + localparam LOGWPL = $clog2(WORDSPERLINE); + localparam LOGXLENBYTES = $clog2(`XLEN/8); + logic [NUMLINES-1:0] ValidBits; logic [NUMLINES-1:0] DirtyBits; logic [LINELEN-1:0] ReadDataLine; @@ -68,7 +71,18 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, logic [$clog2(NUMLINES)-1:0] RAdrD; logic SetValidD, ClearValidD; logic SetDirtyD, ClearDirtyD; - logic SRAMWayWriteEnableD; + + logic [2**LOGWPL-1:0] MemPAdrDecoded; + logic [LINELEN/`XLEN-1:0] SelectedWriteWordEn; + + + ///////////////////////////////////////////////////////////////////////////////////////////// + // Write Enable demux + ///////////////////////////////////////////////////////////////////////////////////////////// + onehotdecoder #(LOGWPL) adrdec( + .bin(PAdr[LOGWPL+LOGXLENBYTES-1:LOGXLENBYTES]), .decoded(MemPAdrDecoded)); + // If writing the whole line set all write enables to 1, else only set the correct word. + assign SelectedWriteWordEn = WriteLineEn ? '1 : WriteWordEn ? MemPAdrDecoded : '0; // OR-AND ///////////////////////////////////////////////////////////////////////////////////////////// // Tag Array @@ -76,7 +90,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, sram1rw #(.DEPTH(NUMLINES), .WIDTH(TAGLEN)) CacheTagMem(.clk(clk), .Adr(RAdr), .ReadData(ReadTag), - .WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(TagWriteEnable)); + .WriteData(PAdr[`PA_BITS-1:OFFSETLEN+INDEXLEN]), .WriteEnable(WriteLineEn)); // AND portion of distributed tag multiplexer assign SelTag = SelFlush ? Flush : Victim; @@ -93,7 +107,7 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, sram1rw #(.DEPTH(NUMLINES), .WIDTH(`XLEN)) CacheDataMem(.clk(clk), .Adr(RAdr), .ReadData(ReadDataLine[(words+1)*`XLEN-1:words*`XLEN] ), .WriteData(WriteData[(words+1)*`XLEN-1:words*`XLEN]), - .WriteEnable(SRAMWayWriteEnable & SRAMWordEnable[words])); + .WriteEnable(SelectedWriteWordEn[words])); end // AND portion of distributed read multiplexers @@ -112,8 +126,8 @@ module cacheway #(parameter NUMLINES=512, parameter LINELEN = 256, TAGLEN = 26, end // *** consider revisiting whether these delays are the best option? flop #($clog2(NUMLINES)) RAdrDelayReg(clk, RAdr, RAdrD); - flop #(3) ValidCtrlDelayReg(clk, {SetValid, ClearValid, SRAMWayWriteEnable}, - {SetValidD, ClearValidD, SRAMWayWriteEnableD}); + flop #(2) ValidCtrlDelayReg(clk, {SetValid, ClearValid}, + {SetValidD, ClearValidD}); assign Valid = ValidBits[RAdrD]; /////////////////////////////////////////////////////////////////////////////////////////////