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Commenting, attribution for sim, minor log changes

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Limnanthes Serafini 2023-04-05 02:43:02 -07:00
parent 0aadbd8492
commit 49226a1eb2
2 changed files with 70 additions and 38 deletions
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84
bin/CacheSim.py
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@ -1,15 +1,46 @@
#!/usr/bin/env python3 #!/usr/bin/env python3
# Authors: Limnanthes Serafini (lserafini@hmc.edu) and Alec Vercruysse (avercruysse@hmc.edu) ###########################################
# TODO: add better (more formal?) attribution, commenting, improve output ## testcount.pl
##
## Written: lserafini@hmc.edu
## Created: 27 March 2023
## Modified: 5 April 2023
##
## Purpose: Simulate a L1 D$ or I$ for comparison with Wally
##
## A component of the CORE-V-WALLY configurable RISC-V project.
##
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
##
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
##
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
## may obtain a copy of the License at
##
## https:##solderpad.org/licenses/SHL-2.1/
##
## Unless required by applicable law or agreed to in writing, any work distributed under the
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
## either express or implied. See the License for the specific language governing permissions
## and limitations under the License.
################################################################################################
# how to invoke this simulator:
# CacheSim.py <number of lines> <number of ways> <length of physical address> <length of tag> -f <log file> (-v)
# so the default invocation for rv64gc is 'CacheSim.py 64 4 56 44 -f <log file>'
# the log files to run this simulator on can be generated from testbench.sv
# by setting I_CACHE_ADDR_LOGGER and/or D_CACHE_ADDR_LOGGER to 1 before running tests.
# I (Lim) recommend logging a single set of tests (such as wally64priv) at a time.
# with verbose mode off, the simulator only reports mismatches between its and Wally's behavior.
# with verbose mode on, the simulator logs each access into the cache.
import sys import sys
import math import math
import argparse import argparse
import os import os
fulltrace = False
class CacheLine: class CacheLine:
def __init__(self): def __init__(self):
self.tag = 0 self.tag = 0
@ -44,21 +75,25 @@ class Cache:
for i in range(self.numsets): for i in range(self.numsets):
self.pLRU.append([0]*(self.numways-1)) self.pLRU.append([0]*(self.numways-1))
# flushes the cache by setting all dirty bits to False
def flush(self): def flush(self):
for way in self.ways: for way in self.ways:
for line in way: for line in way:
line.dirty = False line.dirty = False
# invalidates the cache by setting all valid bits to False
def invalidate(self): def invalidate(self):
for way in self.ways: for way in self.ways:
for line in way: for line in way:
line.valid = False line.valid = False
# resets the pLRU to a fresh 2-D array of 0s
def clear_pLRU(self): def clear_pLRU(self):
self.pLRU = [] self.pLRU = []
for i in range(self.numsets): for i in range(self.numsets):
self.pLRU.append([0]*(self.numways-1)) self.pLRU.append([0]*(self.numways-1))
# splits the given address into tag, set, and offset
def splitaddr(self, addr): def splitaddr(self, addr):
# no need for offset in the sim, but it's here for debug # no need for offset in the sim, but it's here for debug
tag = addr >> (self.setlen + self.offsetlen) & int('1'*self.taglen, 2) tag = addr >> (self.setlen + self.offsetlen) & int('1'*self.taglen, 2)
@ -66,6 +101,9 @@ class Cache:
offset = addr & int('1'*self.offsetlen, 2) offset = addr & int('1'*self.offsetlen, 2)
return tag, setnum, offset return tag, setnum, offset
# performs a cache access with the given address.
# returns a character representing the outcome:
# H/M/E/D - hit, miss, eviction, or eviction with writeback
def cacheaccess(self, addr, write=False): def cacheaccess(self, addr, write=False):
tag, setnum, _ = self.splitaddr(addr) tag, setnum, _ = self.splitaddr(addr)
@ -73,8 +111,7 @@ class Cache:
for waynum in range(self.numways): for waynum in range(self.numways):
line = self.ways[waynum][setnum] line = self.ways[waynum][setnum]
if line.tag == tag and line.valid: if line.tag == tag and line.valid:
if write: line.dirty = line.dirty or write
line.dirty = True
self.update_pLRU(waynum, setnum) self.update_pLRU(waynum, setnum)
return 'H' return 'H'
@ -85,10 +122,7 @@ class Cache:
if not line.valid: if not line.valid:
line.tag = tag line.tag = tag
line.valid = True line.valid = True
if write: line.dirty = write
line.dirty = True
else:
line.dirty = False
self.update_pLRU(waynum, setnum) self.update_pLRU(waynum, setnum)
return 'M' return 'M'
@ -96,17 +130,14 @@ class Cache:
victim = self.getvictimway(setnum) victim = self.getvictimway(setnum)
line = self.ways[victim][setnum] line = self.ways[victim][setnum]
prevdirty = line.dirty prevdirty = line.dirty
#print("Evicting tag", line.tag, "from set", setnum, "way", victim)
#print("replacing with", tag)
line.tag = tag line.tag = tag
line.valid = True # technically redundant line.valid = True # technically redundant
if write: line.dirty = write
line.dirty = True
else:
line.dirty = False
self.update_pLRU(victim, setnum) self.update_pLRU(victim, setnum)
return 'D' if prevdirty else 'E' return 'D' if prevdirty else 'E'
# updates the psuedo-LRU tree for the given set
# with an access to the given way
def update_pLRU(self, waynum, setnum): def update_pLRU(self, waynum, setnum):
if self.numways == 1: if self.numways == 1:
return return
@ -115,13 +146,14 @@ class Cache:
bottomrow = (self.numways - 1)//2 bottomrow = (self.numways - 1)//2
index = (waynum // 2) + bottomrow index = (waynum // 2) + bottomrow
tree[index] = int(not (waynum % 2)) tree[index] = int(not (waynum % 2))
#print("changing index", index, "to", int(not (waynum % 2)))
while index > 0: while index > 0:
parent = (index-1) // 2 parent = (index-1) // 2
tree[parent] = index % 2 tree[parent] = index % 2
#print("changing index", parent, "to", index%2)
index = parent index = parent
# uses the psuedo-LRU tree to select
# a victim way from the given set
# returns the victim way as an integer
def getvictimway(self, setnum): def getvictimway(self, setnum):
if self.numways == 1: if self.numways == 1:
return 0 return 0
@ -163,12 +195,12 @@ if __name__ == "__main__":
parser.add_argument('addrlen', type=int, help="Length of the address in bits (a power of 2)", metavar="A") parser.add_argument('addrlen', type=int, help="Length of the address in bits (a power of 2)", metavar="A")
parser.add_argument('taglen', type=int, help="Length of the tag in bits", metavar="T") parser.add_argument('taglen', type=int, help="Length of the tag in bits", metavar="T")
parser.add_argument('-f', "--file", required=True, help="Log file to simulate from") parser.add_argument('-f', "--file", required=True, help="Log file to simulate from")
parser.add_argument('-v', "--verbose", action='store_true', help="verbose/full-trace mode")
args = parser.parse_args() args = parser.parse_args()
cache = Cache(args.numlines, args.numways, args.addrlen, args.taglen) cache = Cache(args.numlines, args.numways, args.addrlen, args.taglen)
#numtests = -1
extfile = os.path.expanduser(args.file) extfile = os.path.expanduser(args.file)
with open(extfile, "r") as f: with open(extfile, "r") as f:
for ln in f: for ln in f:
ln = ln.strip() ln = ln.strip()
@ -179,26 +211,28 @@ if __name__ == "__main__":
# trying TRAIN clears instead # trying TRAIN clears instead
cache.invalidate() # a new test is starting, so 'empty' the cache cache.invalidate() # a new test is starting, so 'empty' the cache
cache.clear_pLRU() cache.clear_pLRU()
if fulltrace: #numtests +=1
if args.verbose:
print("New Test") print("New Test")
else: else:
if lninfo[1] == 'F': if lninfo[1] == 'F':
cache.flush() cache.flush()
if fulltrace: if args.verbose:
print("F") print("F")
elif lninfo[1] == 'I': elif lninfo[1] == 'I':
cache.invalidate() cache.invalidate()
if fulltrace: if args.verbose:
print("I") print("I")
else: else:
addr = int(lninfo[0], 16) addr = int(lninfo[0], 16)
iswrite = lninfo[1] == 'W' or lninfo[1] == 'A' iswrite = lninfo[1] == 'W' or lninfo[1] == 'A'
result = cache.cacheaccess(addr, iswrite) result = cache.cacheaccess(addr, iswrite)
if fulltrace: if args.verbose:
tag, setnum, offset = cache.splitaddr(addr) tag, setnum, offset = cache.splitaddr(addr)
print(hex(addr), hex(tag), hex(setnum), hex(offset), lninfo[2], result) print(hex(addr), hex(tag), hex(setnum), hex(offset), lninfo[2], result)
if not result == lninfo[2]: if not result == lninfo[2]:
print("Result mismatch at address", lninfo[0], ". Wally:", lninfo[2],", Sim:", result) print("Result mismatch at address", lninfo[0], ". Wally:", lninfo[2],", Sim:", result) #, "in test", numtests)

24
testbench/testbench.sv
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@ -30,8 +30,8 @@
`define PrintHPMCounters 0 `define PrintHPMCounters 0
`define BPRED_LOGGER 0 `define BPRED_LOGGER 0
`define I_CACHE_ADDR_LOGGER 1 `define I_CACHE_ADDR_LOGGER 0
`define D_CACHE_ADDR_LOGGER 1 `define D_CACHE_ADDR_LOGGER 0
module testbench; module testbench;
parameter DEBUG=0; parameter DEBUG=0;
@ -562,11 +562,9 @@ if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger
logic Enable; logic Enable;
// assign Enable = ~dut.core.StallD & ~dut.core.FlushD & dut.core.ifu.bus.icache.CacheRWF[1] & ~reset; // assign Enable = ~dut.core.StallD & ~dut.core.FlushD & dut.core.ifu.bus.icache.CacheRWF[1] & ~reset;
// this version of enable does create repeated instructions (i.e, when there's a stall) // this version of Enable allows for accurate eviction logging.
// but! it allows us to correctly log evictions // Likely needs further improvement.
// and re-accessing the same portion of memory just generates another hit, so the duplicates are OK assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn & ~reset;
// for now at least
assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn;
flop #(1) ResetDReg(clk, reset, resetD); flop #(1) ResetDReg(clk, reset, resetD);
assign resetEdge = ~reset & resetD; assign resetEdge = ~reset & resetD;
initial begin initial begin
@ -588,7 +586,7 @@ if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger
end end
end end
// old version
if (`DCACHE_SUPPORTED && `D_CACHE_ADDR_LOGGER) begin : DCacheLogger if (`DCACHE_SUPPORTED && `D_CACHE_ADDR_LOGGER) begin : DCacheLogger
int file; int file;
string LogFile; string LogFile;
@ -610,11 +608,11 @@ if (`ICACHE_SUPPORTED && `I_CACHE_ADDR_LOGGER) begin : ICacheLogger
// ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage & // ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
// (AccessTypeString != "NULL"); // (AccessTypeString != "NULL");
// this version of enable does create repeated instructions (i.e, when there's a stall) // This version of enable allows for accurate eviction logging.
// but! it allows us to correctly log evictions // Likely needs further improvement.
// and re-accessing the same portion of memory just generates another hit, so the duplicates are OK assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn &
// for now at least ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn; (AccessTypeString != "NULL");
initial begin initial begin
LogFile = $psprintf("DCache.log"); LogFile = $psprintf("DCache.log");