diff --git a/pipelined/src/ifu/ifu.sv b/pipelined/src/ifu/ifu.sv
index aab3ad00d..012e67a98 100644
--- a/pipelined/src/ifu/ifu.sv
+++ b/pipelined/src/ifu/ifu.sv
@@ -203,7 +203,7 @@ module ifu (
     busdp(.clk, .reset,
           .HRDATA(HRDATA), .BusAck(IFUBusAck), .BusInit(IFUBusInit), .BusWrite(), .SelLSUBusWord(),
           .BusRead(IFUBusRead), .HSIZE(), .HBURST(IFUHBURST), .HTRANS(IFUHTRANS), .BusTransComplete(IFUTransComplete),
-          .LSUFunct3M(3'b010), .HADDR(IFUHADDR), .CacheBusAdr(ICacheBusAdr),
+          .Funct3(3'b010), .HADDR(IFUHADDR), .CacheBusAdr(ICacheBusAdr),
           .WordCount(), 
           .CacheFetchLine(ICacheFetchLine),
           .CacheWriteLine(1'b0), .CacheBusAck(ICacheBusAck), 
diff --git a/pipelined/src/lsu/busdp.sv b/pipelined/src/lsu/busdp.sv
index 8da148abb..658438093 100644
--- a/pipelined/src/lsu/busdp.sv
+++ b/pipelined/src/lsu/busdp.sv
@@ -65,7 +65,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
   input logic [1:0]           RWM,
   input logic                 CPUBusy,
   input logic                 CacheableM,
-  input logic [2:0]           LSUFunct3M,
+  input logic [2:0]           Funct3,
   output logic                SelLSUBusWord,
   output logic                BusStall,
   output logic                BusCommittedM);
@@ -86,7 +86,7 @@ module busdp #(parameter WORDSPERLINE, LINELEN, LOGWPL, CACHE_ENABLED)
   mux2 #(`PA_BITS) localadrmux(CacheBusAdr, PAdrM, SelUncachedAdr, LocalHADDR);
   assign HADDR = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalHADDR;
 
-  mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(LSUFunct3M), .s(SelUncachedAdr), .y(HSIZE));
+  mux2 #(3) sizemux(.d0(`XLEN == 32 ? 3'b010 : 3'b011), .d1(Funct3), .s(SelUncachedAdr), .y(HSIZE));
 
   busfsm #(WordCountThreshold, LOGWPL, CACHE_ENABLED) busfsm(
     .clk, .reset, .IgnoreRequest, .RWM, .CacheFetchLine, .CacheWriteLine,
diff --git a/pipelined/src/lsu/lsu.sv b/pipelined/src/lsu/lsu.sv
index 92b82d817..1028a1e7a 100644
--- a/pipelined/src/lsu/lsu.sv
+++ b/pipelined/src/lsu/lsu.sv
@@ -227,7 +227,7 @@ module lsu (
       .HRDATA, .BusAck(LSUBusAck), .BusInit(LSUBusInit), .BusWrite(LSUBusWrite), 
       .BusRead(LSUBusRead), .HSIZE(LSUHSIZE), .HBURST(LSUHBURST), .HTRANS(LSUHTRANS), .BusTransComplete(LSUTransComplete),
       .WordCount, .SelLSUBusWord,
-      .LSUFunct3M, .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine),
+      .Funct3(LSUFunct3M), .HADDR(LSUHADDR), .CacheBusAdr(DCacheBusAdr), .CacheFetchLine(DCacheFetchLine),
       .CacheWriteLine(DCacheWriteLine), .CacheBusAck(DCacheBusAck), .FetchBuffer, .PAdrM(LSUPAdrM),
       .SelUncachedAdr, .IgnoreRequest, .RWM(LSURWM), .CPUBusy, .CacheableM,
       .BusStall, .BusCommittedM);