diff --git a/src/uncore/ahbapbbridge.sv b/src/uncore/ahbapbbridge.sv
index 381297f00..454f4d5df 100644
--- a/src/uncore/ahbapbbridge.sv
+++ b/src/uncore/ahbapbbridge.sv
@@ -88,7 +88,6 @@ module ahbapbbridge import cvw::*;  #(parameter cvw_t P,
   int i;
   always_comb begin
     // default: no peripheral selected: read 0, indicate ready during access phase so bus doesn't hang
-    // *** also could assert ready right away
     HRDATA = 0;
     PREADYOUT = 1'b1; 
     for (i=0; i<PERIPHS; i++)  begin
diff --git a/src/uncore/gpio_apb.sv b/src/uncore/gpio_apb.sv
index baab83088..4ba3e1ccf 100644
--- a/src/uncore/gpio_apb.sv
+++ b/src/uncore/gpio_apb.sv
@@ -59,14 +59,9 @@ module gpio_apb import cvw::*;  #(parameter cvw_t P) (
 
   // account for subword read/write circuitry
   // -- Note GPIO registers are 32 bits no matter what; access them with LW SW.
-  //    (At least that's what I think when FE310 spec says "only naturally aligned 32-bit accesses are supported")
-  if (P.XLEN == 64) begin
-    assign Din    = entry[2] ? PWDATA[63:32] : PWDATA[31:0];
-    assign PRDATA = entry[2] ? {Dout,32'b0}  : {32'b0,Dout};
-  end else begin // 32-bit
-    assign Din    = PWDATA[31:0];
-    assign PRDATA = Dout;
-  end
+  assign Din = PWDATA[31:0]; 
+  if (P.XLEN == 64) assign PRDATA = {Dout, Dout}; 
+  else              assign PRDATA = Dout;    
 
   // register access
   always_ff @(posedge PCLK, negedge PRESETn)
diff --git a/src/uncore/plic_apb.sv b/src/uncore/plic_apb.sv
index f2a643101..96f3eb6eb 100644
--- a/src/uncore/plic_apb.sv
+++ b/src/uncore/plic_apb.sv
@@ -94,13 +94,9 @@ module plic_apb import cvw::*;  #(parameter cvw_t P) (
 
   // account for subword read/write circuitry
   // -- Note PLIC registers are 32 bits no matter what; access them with LW SW.
-  if (P.XLEN == 64) begin
-    assign Din    = entry[2] ? PWDATA[63:32] : PWDATA[31:0];
-    assign PRDATA = entry[2] ? {Dout,32'b0}  : {32'b0,Dout};
-  end else begin // 32-bit
-    assign PRDATA = Dout;
-    assign Din    = PWDATA[31:0];
-  end
+  assign Din = PWDATA[31:0]; 
+  if (P.XLEN == 64) assign PRDATA = {Dout, Dout}; 
+  else              assign PRDATA = Dout;    
 
   // ==================
   // Register Interface
diff --git a/src/uncore/uart_apb.sv b/src/uncore/uart_apb.sv
index 130d7503e..6fab04189 100644
--- a/src/uncore/uart_apb.sv
+++ b/src/uncore/uart_apb.sv
@@ -54,31 +54,9 @@ module uart_apb import cvw::*; #(parameter cvw_t P) (
   assign MEMRb    = ~memread;
   assign MEMWb    = ~memwrite;
 
-  if (P.XLEN == 64) begin:uart
-    always_comb begin
-      PRDATA = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};
-      case (entry)
-        3'b000: Din = PWDATA[7:0];
-        3'b001: Din = PWDATA[15:8];
-        3'b010: Din = PWDATA[23:16];
-        3'b011: Din = PWDATA[31:24];
-        3'b100: Din = PWDATA[39:32];
-        3'b101: Din = PWDATA[47:40];
-        3'b110: Din = PWDATA[55:48];
-        3'b111: Din = PWDATA[63:56];
-      endcase 
-    end 
-  end else begin:uart // 32-bit
-    always_comb begin
-      PRDATA = {Dout, Dout, Dout, Dout};
-      case (entry[1:0])
-        2'b00: Din = PWDATA[7:0];
-        2'b01: Din = PWDATA[15:8];
-        2'b10: Din = PWDATA[23:16];
-        2'b11: Din = PWDATA[31:24];
-      endcase
-    end
-  end
+  assign Din = PWDATA[7:0]; 
+  if (P.XLEN == 64) assign PRDATA = {Dout, Dout, Dout, Dout, Dout, Dout, Dout, Dout};
+  else              assign PRDATA = {Dout, Dout, Dout, Dout};   
   
   logic BAUDOUTb;  // loop tx clock BAUDOUTb back to rx clock RCLK
   uartPC16550D #(P.UART_PRESCALE) u(