From 48a8dc7738cc523612e3cb1c44316edf1dc27ce7 Mon Sep 17 00:00:00 2001 From: Jacob Pease Date: Wed, 16 Aug 2023 13:05:37 -0500 Subject: [PATCH] Added SPDX header to probe script. --- fpga/probe | 43 ++++++++++++++++++++++++------------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/fpga/probe b/fpga/probe index 5067a2cf6..21e5d8240 100755 --- a/fpga/probe +++ b/fpga/probe @@ -1,4 +1,28 @@ #!/usr/bin/python3 +########################################### +## probe.sh +## +## Written: Jacob Pease jacobpease@protonmail.com +## Created: 16 August 2023 +## Modified: 16 August 2023 +## +## A component of the CORE-V-WALLY configurable RISC-V project. +## +## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +## +## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +## +## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +## except in compliance with the License, or, at your option, the Apache License version 2.0. You +## may obtain a copy of the License at +## +## https:##solderpad.org#licenses#SHL-2.1# +## +## Unless required by applicable law or agreed to in writing, any work distributed under the +## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +## either express or implied. See the License for the specific language governing permissions +## and limitations under the License. +################################################################################################ import sys @@ -6,25 +30,6 @@ def usage(): print("Usage: ./probes name width probenum") exit(1) -def header(): - return """create_debug_core u_ila_0 ila - -set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0] -set_property C_TRIGIN_EN false [get_debug_cores u_ila_0] -set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0] -set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0] -set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0] -set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0] -set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0] -set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0] -startgroup -set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ] -set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ] -set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ] -set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ] -endgroup -connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]""" - def convertLine(x): temp = x.split() temp[1] = int(temp[1])