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minor tweak

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This commit is contained in:
James E. Stine 2024-02-20 18:42:34 -06:00
parent 0cc0cdeae2
commit 488583aed9
6 changed files with 54 additions and 72 deletions
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2
src/ieu/aes_common/aes_inv_sbox_word.sv
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@ -1,5 +1,5 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// aes_inv_sbox.sv // aes_inv_sbox_word.sv
// //
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024 // Created: 20 February 2024

23
src/ieu/aes_common/aes_inv_shiftrow.sv
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@ -30,28 +30,28 @@
module aes_inv_shiftrow(input logic [127:0] dataIn, module aes_inv_shiftrow(input logic [127:0] dataIn,
output logic [127:0] dataOut); output logic [127:0] dataOut);
//Seperate the first (Least Significant) word into bytes // Seperate the first (Least Significant) word into bytes
logic [7:0] w0_b0 = dataIn[7:0]; logic [7:0] w0_b0 = dataIn[7:0];
logic [7:0] w0_b1 = dataIn[15:8]; logic [7:0] w0_b1 = dataIn[15:8];
logic [7:0] w0_b2 = dataIn[23:16]; logic [7:0] w0_b2 = dataIn[23:16];
logic [7:0] w0_b3 = dataIn[31:24]; logic [7:0] w0_b3 = dataIn[31:24];
//Seperate the second word into bytes // Seperate the second word into bytes
logic [7:0] w1_b0 = dataIn[39:32]; logic [7:0] w1_b0 = dataIn[39:32];
logic [7:0] w1_b1 = dataIn[47:40]; logic [7:0] w1_b1 = dataIn[47:40];
logic [7:0] w1_b2 = dataIn[55:48]; logic [7:0] w1_b2 = dataIn[55:48];
logic [7:0] w1_b3 = dataIn[63:56]; logic [7:0] w1_b3 = dataIn[63:56];
//Seperate the third word into bytes // Seperate the third word into bytes
logic [7:0] w2_b0 = dataIn[71:64]; logic [7:0] w2_b0 = dataIn[71:64];
logic [7:0] w2_b1 = dataIn[79:72]; logic [7:0] w2_b1 = dataIn[79:72];
logic [7:0] w2_b2 = dataIn[87:80]; logic [7:0] w2_b2 = dataIn[87:80];
logic [7:0] w2_b3 = dataIn[95:88]; logic [7:0] w2_b3 = dataIn[95:88];
//Seperate the fourth (Most significant) word into bytes // Seperate the fourth (Most significant) word into bytes
logic [7:0] w3_b0 = dataIn[103:96]; logic [7:0] w3_b0 = dataIn[103:96];
logic [7:0] w3_b1 = dataIn[111:104]; logic [7:0] w3_b1 = dataIn[111:104];
logic [7:0] w3_b2 = dataIn[119:112]; logic [7:0] w3_b2 = dataIn[119:112];
logic [7:0] w3_b3 = dataIn[127:120]; logic [7:0] w3_b3 = dataIn[127:120];
//The output words are composed of sets of the input bytes. // The output words are composed of sets of the input bytes.
logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0}; logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0};
logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0}; logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0};
logic [31:0] out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0}; logic [31:0] out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0};
@ -70,8 +70,7 @@ endmodule
input selection. input selection.
*/ */
module aes_shiftword(input logic[1:0] shiftAmt, module aes_shiftword(input logic[1:0] shiftAmt, input logic [31:0] dataIn,
input logic [31:0] dataIn,
output logic [31:0] dataOut); output logic [31:0] dataOut);
@ -83,15 +82,15 @@ module aes_shiftword(input logic[1:0] shiftAmt,
always_comb always_comb
begin begin
case(shiftAmt) case(shiftAmt)
//00 : Barrel Shift no bytes // 00 : Barrel Shift no bytes
2'b00 : dataOut = {b3, b2, b1, b0}; 2'b00 : dataOut = {b3, b2, b1, b0};
//01 : Barrel Shift one byte // 01 : Barrel Shift one byte
2'b01 : dataOut = {b0, b3, b2, b1}; 2'b01 : dataOut = {b0, b3, b2, b1};
//10 : Barrel Shift two bytes // 10 : Barrel Shift two bytes
2'b10 : dataOut = {b1, b0, b3, b2}; 2'b10 : dataOut = {b1, b0, b3, b2};
//11 : Barrel Shift three bytes // 11 : Barrel Shift three bytes
default : dataOut = {b2, b1, b0, b3}; default : dataOut = {b2, b1, b0, b3};
endcase endcase
end // always_comb end
endmodule endmodule

26
src/ieu/aes_common/aes_mixcolumns.sv
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@ -67,7 +67,7 @@ module aes_mixcolumns(data, mixedcols);
endmodule // mixcolumns endmodule // mixcolumns
//This applies the Galois field operations to an individual 32 bit word. // This applies the Galois field operations to an individual 32 bit word.
module mixword (word, mixed_word); module mixword (word, mixed_word);
// Declare Inputs/Outputs // Declare Inputs/Outputs
@ -97,28 +97,20 @@ module mixword (word, mixed_word);
assign b3 = word[7:0]; assign b3 = word[7:0];
// mb0 Galois components // mb0 Galois components
gm2 gm2_0(.gm2_in(b0), gm2 gm2_0(.gm2_in(b0), .gm2_out(gm2_0_out));
.gm2_out(gm2_0_out)); gm3 gm3_0(.gm3_in(b3), .gm3_out(gm3_0_out));
gm3 gm3_0(.gm3_in(b3),
.gm3_out(gm3_0_out));
// mb1 Galois components // mb1 Galois components
gm2 gm2_1(.gm2_in(b1), gm2 gm2_1(.gm2_in(b1), .gm2_out(gm2_1_out));
.gm2_out(gm2_1_out)); gm3 gm3_1(.gm3_in(b0), .gm3_out(gm3_1_out));
gm3 gm3_1(.gm3_in(b0),
.gm3_out(gm3_1_out));
// mb2 Galois components // mb2 Galois components
gm2 gm2_2(.gm2_in(b2), gm2 gm2_2(.gm2_in(b2), .gm2_out(gm2_2_out));
.gm2_out(gm2_2_out)); gm3 gm3_2(.gm3_in(b1), .gm3_out(gm3_2_out));
gm3 gm3_2(.gm3_in(b1),
.gm3_out(gm3_2_out));
// mb3 Galois components // mb3 Galois components
gm2 gm2_3(.gm2_in(b3), gm2 gm2_3(.gm2_in(b3), .gm2_out(gm2_3_out));
.gm2_out(gm2_3_out)); gm3 gm3_3(.gm3_in(b2), .gm3_out(gm3_3_out));
gm3 gm3_3(.gm3_in(b2),
.gm3_out(gm3_3_out));
// Combine Componenets into mixed word // Combine Componenets into mixed word
assign mb0 = gm2_0_out ^ gm3_0_out ^ b1 ^ b2; assign mb0 = gm2_0_out ^ gm3_0_out ^ b1 ^ b2;

12
src/ieu/aes_common/aes_sbox_word.sv
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@ -31,16 +31,12 @@ module aes_sbox_word(input logic [31:0] in,
output logic [31:0] out); output logic [31:0] out);
// Declare the SBOX for (least significant) byte 0 of the input // Declare the SBOX for (least significant) byte 0 of the input
aes_sbox sbox_b0(.in(in[7:0]), aes_sbox sbox_b0(.in(in[7:0]), .out(out[7:0]));
.out(out[7:0]));
// Declare the SBOX for byte 1 of the input // Declare the SBOX for byte 1 of the input
aes_sbox sbox_b1(.in(in[15:8]), aes_sbox sbox_b1(.in(in[15:8]), .out(out[15:8]));
.out(out[15:8]));
// Declare the SBOX for byte 2 of the input // Declare the SBOX for byte 2 of the input
aes_sbox sbox_b2(.in(in[23:16]), aes_sbox sbox_b2(.in(in[23:16]), .out(out[23:16]));
.out(out[23:16]));
// Declare the SBOX for byte 3 of the input // Declare the SBOX for byte 3 of the input
aes_sbox sbox_b3(.in(in[31:24]), aes_sbox sbox_b3(.in(in[31:24]), .out(out[31:24]));
.out(out[31:24]));
endmodule endmodule

29
src/ieu/aes_common/aes_shiftrow.sv
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@ -33,32 +33,31 @@ module aes_shiftrow(input logic [127:0] dataIn,
// (This form of writing it may seem like more effort but I feel // (This form of writing it may seem like more effort but I feel
// like it is more self-explanatory this way without losing efficiency) // like it is more self-explanatory this way without losing efficiency)
//Seperate the first (Least Significant) word into bytes // Seperate the first (Least Significant) word into bytes
logic [7:0] w0_b0 = dataIn[7:0]; logic [7:0] w0_b0 = dataIn[7:0];
logic [7:0] w0_b1 = dataIn[79:72]; logic [7:0] w0_b1 = dataIn[79:72];
logic [7:0] w0_b2 = dataIn[23:16]; logic [7:0] w0_b2 = dataIn[23:16];
logic [7:0] w0_b3 = dataIn[95:88]; logic [7:0] w0_b3 = dataIn[95:88];
//Seperate the second word into bytes // Seperate the second word into bytes
logic [7:0] w1_b0 = dataIn[39:32]; logic [7:0] w1_b0 = dataIn[39:32];
logic [7:0] w1_b1 = dataIn[111:104]; logic [7:0] w1_b1 = dataIn[111:104];
logic [7:0] w1_b2 = dataIn[55:48]; logic [7:0] w1_b2 = dataIn[55:48];
logic [7:0] w1_b3 = dataIn[127:120]; logic [7:0] w1_b3 = dataIn[127:120];
//Seperate the third word into bytes // Seperate the third word into bytes
logic [7:0] w2_b0 = dataIn[71:64]; logic [7:0] w2_b0 = dataIn[71:64];
logic [7:0] w2_b1 = dataIn[15:8]; logic [7:0] w2_b1 = dataIn[15:8];
logic [7:0] w2_b2 = dataIn[87:80]; logic [7:0] w2_b2 = dataIn[87:80];
logic [7:0] w2_b3 = dataIn[31:24]; logic [7:0] w2_b3 = dataIn[31:24];
//Seperate the fourth (Most significant) word into bytes // Seperate the fourth (Most significant) word into bytes
logic [7:0] w3_b0 = dataIn[103:96]; logic [7:0] w3_b0 = dataIn[103:96];
logic [7:0] w3_b1 = dataIn[47:40]; logic [7:0] w3_b1 = dataIn[47:40];
logic [7:0] w3_b2 = dataIn[119:112]; logic [7:0] w3_b2 = dataIn[119:112];
logic [7:0] w3_b3 = dataIn[63:56]; logic [7:0] w3_b3 = dataIn[63:56];
// The output words are composed of sets of the input bytes.
//The output words are composed of sets of the input bytes. logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0};
logic [31:0] out_w0 = {w0_b3, w1_b2, w2_b1, w3_b0}; logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0};
logic [31:0] out_w1 = {w3_b3, w0_b2, w1_b1, w2_b0}; logic [31:0] out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0};
logic [31:0] out_w2 = {w2_b3, w3_b2, w0_b1, w1_b0}; logic [31:0] out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0};
logic [31:0] out_w3 = {w1_b3, w2_b2, w3_b1, w0_b0};
assign dataOut = {out_w0, out_w1, out_w2, out_w3}; assign dataOut = {out_w0, out_w1, out_w2, out_w3};
@ -84,13 +83,13 @@ module aes_shiftwordbrutherr(input logic[1:0] shiftAmt,
always_comb always_comb
begin begin
case(shiftAmt) case(shiftAmt)
//00 : Barrel Shift no bytes // 00 : Barrel Shift no bytes
2'b00 : dataOut = {b3, b2, b1, b0}; 2'b00 : dataOut = {b3, b2, b1, b0};
//01 : Barrel Shift one byte // 01 : Barrel Shift one byte
2'b01 : dataOut = {b2, b1, b0, b3}; 2'b01 : dataOut = {b2, b1, b0, b3};
//10 : Barrel Shift two bytes // 10 : Barrel Shift two bytes
2'b10 : dataOut = {b1, b0, b2, b3}; 2'b10 : dataOut = {b1, b0, b2, b3};
//11 : Barrel Shift three bytes // 11 : Barrel Shift three bytes
default : dataOut = {b0, b1, b2, b3}; default : dataOut = {b0, b1, b2, b3};
endcase endcase
end end

34
src/ieu/aes_common/galois_func.sv
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@ -1,5 +1,5 @@
/////////////////////////////////////////// ///////////////////////////////////////////
// galois_func.sv // Galois_func.sv
// //
// Written: ryan.swann@okstate.edu, james.stine@okstate.edu // Written: ryan.swann@okstate.edu, james.stine@okstate.edu
// Created: 20 February 2024 // Created: 20 February 2024
@ -35,7 +35,7 @@ module gm2 (gm2_in, gm2_out);
// Set output to Galois Mult 2 // Set output to Galois Mult 2
assign gm2_out = {gm2_in[6:0], 1'b0} ^ (8'h1b & {8{gm2_in[7]}}); assign gm2_out = {gm2_in[6:0], 1'b0} ^ (8'h1b & {8{gm2_in[7]}});
endmodule // gm2 endmodule
module gm3 (gm3_in, gm3_out); module gm3 (gm3_in, gm3_out);
@ -63,10 +63,8 @@ module gm4 (gm4_in, gm4_out);
logic [7:0] gm2_1_out; logic [7:0] gm2_1_out;
// Sub-Modules for multiple gm2 multiplications // Sub-Modules for multiple gm2 multiplications
gm2 gm2_0 (.gm2_in(gm4_in), gm2 gm2_0 (.gm2_in(gm4_in), .gm2_out(gm2_0_out));
.gm2_out(gm2_0_out)); gm2 gm2_1 (.gm2_in(gm2_0_out), .gm2_out(gm2_1_out));
gm2 gm2_1 (.gm2_in(gm2_0_out),
.gm2_out(gm2_1_out));
// Assign output to second gm2 output // Assign output to second gm2 output
assign gm4_out = gm2_1_out; assign gm4_out = gm2_1_out;
@ -82,16 +80,14 @@ module gm8 (gm8_in, gm8_out);
logic [7:0] gm2_0_out; logic [7:0] gm2_0_out;
logic [7:0] gm4_0_out; logic [7:0] gm4_0_out;
// Sub-Modules for sub-galois operations // Sub-Modules for sub-Galois operations
gm4 gm4_0 (.gm4_in(gm8_in), gm4 gm4_0 (.gm4_in(gm8_in), .gm4_out(gm4_0_out));
.gm4_out(gm4_0_out)); gm2 gm2_0 (.gm2_in(gm4_0_out), .gm2_out(gm2_0_out));
gm2 gm2_0 (.gm2_in(gm4_0_out),
.gm2_out(gm2_0_out));
// Assign output to gm2 output // Assign output to gm2 output
assign gm8_out = gm2_0_out; assign gm8_out = gm2_0_out;
endmodule // gm8 endmodule
module gm9 (gm9_in, gm9_out); module gm9 (gm9_in, gm9_out);
@ -101,7 +97,7 @@ module gm9 (gm9_in, gm9_out);
// Internal Logic // Internal Logic
logic [7:0] gm8_0_out; logic [7:0] gm8_0_out;
// Sub-Modules for sub-galois operations // Sub-Modules for sub-Galois operations
gm8 gm8_0 (.gm8_in(gm9_in), .gm8_out(gm8_0_out)); gm8 gm8_0 (.gm8_in(gm9_in), .gm8_out(gm8_0_out));
// Set output to gm8(in) ^ in // Set output to gm8(in) ^ in
@ -118,14 +114,14 @@ module gm11 (gm11_in, gm11_out);
logic [7:0] gm8_0_out; logic [7:0] gm8_0_out;
logic [7:0] gm2_0_out; logic [7:0] gm2_0_out;
// Sub-Modules for sub-galois operations // Sub-Modules for sub-Galois operations
gm8 gm8_0 (.gm8_in(gm11_in), .gm8_out(gm8_0_out)); gm8 gm8_0 (.gm8_in(gm11_in), .gm8_out(gm8_0_out));
gm2 gm2_0 (.gm2_in(gm11_in), .gm2_out(gm2_0_out)); gm2 gm2_0 (.gm2_in(gm11_in), .gm2_out(gm2_0_out));
// Set output to gm8(in) ^ gm2(in) ^ in // Set output to gm8(in) ^ gm2(in) ^ in
assign gm11_out = gm8_0_out ^ gm2_0_out ^ gm11_in; assign gm11_out = gm8_0_out ^ gm2_0_out ^ gm11_in;
endmodule // gm11 endmodule
module gm13 (gm13_in, gm13_out); module gm13 (gm13_in, gm13_out);
@ -136,14 +132,14 @@ module gm13 (gm13_in, gm13_out);
logic [7:0] gm8_0_out; logic [7:0] gm8_0_out;
logic [7:0] gm4_0_out; logic [7:0] gm4_0_out;
// Sub-Modules for sub-galois operations // Sub-Modules for sub-Galois operations
gm8 gm8_0 (.gm8_in(gm13_in), .gm8_out(gm8_0_out)); gm8 gm8_0 (.gm8_in(gm13_in), .gm8_out(gm8_0_out));
gm4 gm4_0 (.gm4_in(gm13_in), .gm4_out(gm4_0_out)); gm4 gm4_0 (.gm4_in(gm13_in), .gm4_out(gm4_0_out));
// Set output to gm8(in) ^ gm4(in) ^ in // Set output to gm8(in) ^ gm4(in) ^ in
assign gm13_out = gm8_0_out ^ gm4_0_out ^ gm13_in; assign gm13_out = gm8_0_out ^ gm4_0_out ^ gm13_in;
endmodule // gm13 endmodule
module gm14 (gm14_in, gm14_out); module gm14 (gm14_in, gm14_out);
@ -155,7 +151,7 @@ module gm14 (gm14_in, gm14_out);
logic [7:0] gm4_0_out; logic [7:0] gm4_0_out;
logic [7:0] gm2_0_out; logic [7:0] gm2_0_out;
// Sub-Modules for sub-galois operations // Sub-Modules for sub-Galois operations
gm8 gm8_0 (.gm8_in(gm14_in), .gm8_out(gm8_0_out)); gm8 gm8_0 (.gm8_in(gm14_in), .gm8_out(gm8_0_out));
gm4 gm4_0 (.gm4_in(gm14_in), .gm4_out(gm4_0_out)); gm4 gm4_0 (.gm4_in(gm14_in), .gm4_out(gm4_0_out));
gm2 gm2_0 (.gm2_in(gm14_in), .gm2_out(gm2_0_out)); gm2 gm2_0 (.gm2_in(gm14_in), .gm2_out(gm2_0_out));
@ -163,5 +159,5 @@ module gm14 (gm14_in, gm14_out);
//Assign output to gm8(in) ^ gm4(in) ^ gm2(in) //Assign output to gm8(in) ^ gm4(in) ^ gm2(in)
assign gm14_out = gm8_0_out ^ gm4_0_out ^ gm2_0_out; assign gm14_out = gm8_0_out ^ gm4_0_out ^ gm2_0_out;
endmodule // gm14 endmodule