From 482e4e6e92471d472aee5863a9a3356d72d31193 Mon Sep 17 00:00:00 2001 From: David Harris Date: Sun, 2 Jul 2023 09:35:05 -0700 Subject: [PATCH] Enhanced decoder to produce individual CMOpE output for the 4 CMO instructions --- src/ieu/controller.sv | 26 +++++++++++++++++++++----- src/ieu/ieu.sv | 4 ++-- src/wally/wallypipelinedcore.sv | 4 ++-- 3 files changed, 25 insertions(+), 9 deletions(-) diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 55a2d7bac..d87a43b4c 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -62,7 +62,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( output logic [2:0] BALUControlE, // ALU Control signals for B instructions in Execute Stage output logic BMUActiveE, // Bit manipulation instruction being executed output logic MDUActiveE, // Mul/Div instruction being executed - output logic CMOE, // Cache Management operation being executed + output logic [3:0] CMOpE, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero // Memory stage control signals input logic StallM, FlushM, // Stall, flush Memory stage @@ -83,6 +83,7 @@ module controller import cvw::*; #(parameter cvw_t P) ( output logic StoreStallD // Store (memory write) causes stall ); + logic [6:0] OpD; // Opcode in Decode stage logic [2:0] Funct3D; // Funct3 field in Decode stage logic [6:0] Funct7D; // Funct7 field in Decode stage @@ -133,13 +134,14 @@ module controller import cvw::*; #(parameter cvw_t P) ( logic FLSFunctD; // Detect floating-point loads and stores logic JRFunctD; // detect jalr instruction logic FenceFunctD; // Detect fence instruction - logic CMOFunctD; + logic CMOFunctD; // Detect CMO instruction logic AFunctD, AMOFunctD; // Detect atomic instructions logic RWFunctD, MWFunctD; // detect RW/MW instructions logic PFunctD, CSRFunctD; // detect privileged / CSR instruction logic FenceM; // Fence.I or sfence.VMA instruction in memory stage logic [2:0] ALUSelectD; // ALU Output selection mux control logic IWValidFunct3D; // Detects if Funct3 is valid for IW instructions + logic [3:0] CMOpD; // which CMO instruction 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero // Extract fields assign OpD = InstrD[6:0]; @@ -349,14 +351,28 @@ module controller import cvw::*; #(parameter cvw_t P) ( assign InvalidateICacheD = 0; assign FlushDCacheD = 0; end + + // Cache Management instructions + if (P.ZICBOM_SUPPORTED | P.ZICBOZ_SUPPORTED) begin:cmo + always_comb + if (CMOD) begin + CMOpD[3] = (InstrD[31:20] == 12'd4); // cbo.zero + CMOpD[2] = (InstrD[31:20] == 12'd2); // cbo.clean + CMOpD[1] = (InstrD[31:20] == 12'd1) | ((InstrD[31:20] == 12'd0) & (ENVCFG_CBE[1:0] == 2'b01)); // cbo.flush + CMOpD[0] = (InstrD[31:20] == 12'd0) & (ENVCFG_CBE[1:0] == 2'b11); // cbo.inval + end else + CMOpD = 4'b0000; // not a cbo instruction + end else begin:cmo + assign CMOpD = 4'b0000; // cbo instructions not supported + end // Decode stage pipeline control register flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); // Execute stage pipeline control register and logic - flopenrc #(30) controlregE(clk, reset, FlushE, ~StallE, - {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOD, InstrValidD}, - {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOE, InstrValidE}); + flopenrc #(33) controlregE(clk, reset, FlushE, ~StallE, + {ALUSelectD, RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, SubArithD, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, CMOpD, InstrValidD}, + {ALUSelectE, IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, SubArithE, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, CMOpE, InstrValidE}); // Branch Logic // The comparator handles both signed and unsigned branches using BranchSignedE diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index f930b1103..9b653001f 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -45,7 +45,7 @@ module ieu import cvw::*; #(parameter cvw_t P) ( output logic [P.XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU src inputs before the mux choosing between them and PCE to put in srcA/B output logic [4:0] RdE, // Destination register output logic MDUActiveE, // Mul/Div instruction being executed - output logic CMOE, // Cache management instruction being executed + output logic [3:0] CMOpE, // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero // Memory stage signals input logic SquashSCW, // Squash store conditional, from LSU output logic [1:0] MemRWM, // Read/write control goes to LSU @@ -104,7 +104,7 @@ module ieu import cvw::*; #(parameter cvw_t P) ( .IllegalIEUFPUInstrD, .IllegalBaseInstrD, .StallE, .FlushE, .FlagsE, .FWriteIntE, .PCSrcE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, .Funct3E, .IntDivE, .MDUE, .W64E, .SubArithE, .BranchD, .BranchE, .JumpD, .JumpE, .SCE, - .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .MDUActiveE, .CMOE, + .BranchSignedE, .BSelectE, .ZBBSelectE, .BALUControlE, .BMUActiveE, .MDUActiveE, .CMOpE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, .StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .InvalidateICacheM, .StoreStallD); diff --git a/src/wally/wallypipelinedcore.sv b/src/wally/wallypipelinedcore.sv index 563e4f987..a6b463d61 100644 --- a/src/wally/wallypipelinedcore.sv +++ b/src/wally/wallypipelinedcore.sv @@ -78,7 +78,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD; logic SquashSCW; logic MDUActiveE; // Mul/Div instruction being executed - logic CMOE; // Cache management instruction being executed + logic [3:0] CMOpE; // 1: cbo.inval; 2: cbo.flush; 4: cbo.clean; 8: cbo.zero logic [3:0] ENVCFG_CBE; // Cache block operation enables // floating point unit signals @@ -193,7 +193,7 @@ module wallypipelinedcore import cvw::*; #(parameter cvw_t P) ( .InstrD, .STATUS_FS, .ENVCFG_CBE, .IllegalIEUFPUInstrD, .IllegalBaseInstrD, // Execute Stage interface .PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E, - .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .MDUActiveE, .CMOE, + .Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .MDUActiveE, .CMOpE, // Memory stage interface .SquashSCW, // from LSU .MemRWM, // read/write control goes to LSU