From 482529394a7df5c15db28cc66edb19794564553e Mon Sep 17 00:00:00 2001
From: Rose Thompson <ross1728@gmail.com>
Date: Fri, 29 Dec 2023 09:53:22 -0600
Subject: [PATCH] Fixed some of the uncached ifu bugs.

---
 src/ifu/ifu.sv | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv
index f6f688a89..e6e4de78a 100644
--- a/src/ifu/ifu.sv
+++ b/src/ifu/ifu.sv
@@ -223,6 +223,7 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
     // **** must fix words per line vs beats per line as in lsu.
     localparam   WORDSPERLINE = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS/P.XLEN : 1;
     localparam   LOGBWPL = P.ICACHE_SUPPORTED ? $clog2(WORDSPERLINE) : 1;
+    
     if(P.ICACHE_SUPPORTED) begin : icache
       localparam            LINELEN = P.ICACHE_SUPPORTED ? P.ICACHE_LINELENINBITS : P.XLEN;
       localparam            LLENPOVERAHBW = P.LLEN / P.AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
@@ -263,7 +264,12 @@ module ifu import cvw::*;  #(parameter cvw_t P) (
             .BusRW, .Stall(GatedStallD),
             .BusStall, .BusCommitted(BusCommittedF));
 
-      mux3 #(32) UnCachedDataMux(.d0(ICacheInstrF), .d1(FetchBuffer[32-1:0]), .d2(IROMInstrF),
+    logic [31:0]          ShiftUncachedInstr;
+
+    if(P.XLEN == 64) mux4 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], FetchBuffer[48-1:16], FetchBuffer[64-1:32], {16'b0, FetchBuffer[64-1:48]},
+                                                      PCSpillF[2:1], ShiftUncachedInstr);
+    else mux2 #(32) UncachedShiftInstrMux(FetchBuffer[32-1:0], {16'b0, FetchBuffer[32-1:16]}, PCSpillF[1], ShiftUncachedInstr);
+      mux3 #(32) UnCachedDataMux(.d0(ICacheInstrF), .d1(ShiftUncachedInstr), .d2(IROMInstrF),
                                  .s({SelIROM, ~CacheableF}), .y(InstrRawF[31:0]));
     end else begin : passthrough
       assign IFUHADDR = PCPF;