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https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Fixed back to back store issue.
Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
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parent
224e3b2991
commit
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15
wally-pipelined/src/cache/dcache.sv
vendored
15
wally-pipelined/src/cache/dcache.sv
vendored
@ -34,9 +34,11 @@ module dcache
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input logic FlushW,
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input logic FlushW,
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// cpu side
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// cpu side
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input logic [1:0] MemRWE,
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input logic [1:0] MemRWM,
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input logic [1:0] MemRWM,
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input logic [2:0] Funct3M,
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input logic [2:0] Funct3M,
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input logic [6:0] Funct7M,
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input logic [6:0] Funct7M,
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input logic [1:0] AtomicE,
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input logic [1:0] AtomicM,
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input logic [1:0] AtomicM,
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input logic [`XLEN-1:0] MemAdrE, // virtual address, but we only use the lower 12 bits.
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input logic [`XLEN-1:0] MemAdrE, // virtual address, but we only use the lower 12 bits.
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input logic [`PA_BITS-1:0] MemPAdrM, // physical address
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input logic [`PA_BITS-1:0] MemPAdrM, // physical address
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@ -299,6 +301,7 @@ module dcache
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// control path *** eventually move to own module.
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// control path *** eventually move to own module.
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logic AnyCPUReqM;
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logic AnyCPUReqM;
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logic AnyCPUReqE;
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logic FetchCountFlag;
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logic FetchCountFlag;
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logic PreCntEn;
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logic PreCntEn;
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logic CntEn;
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logic CntEn;
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@ -349,6 +352,7 @@ module dcache
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assign AnyCPUReqM = |MemRWM | (|AtomicM);
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assign AnyCPUReqM = |MemRWM | (|AtomicM);
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assign AnyCPUReqE = |MemRWE | (|AtomicE);
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assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL:0]);
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assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL:0]);
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flopenr #(LOGWPL+1)
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flopenr #(LOGWPL+1)
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@ -406,7 +410,7 @@ module dcache
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case (CurrState)
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case (CurrState)
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STATE_READY: begin
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STATE_READY: begin
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// sram busy
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// sram busy
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if (AnyCPUReqM & SRAMWordWriteEnableW) begin
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if (AnyCPUReqE & SRAMWordWriteEnableM) begin
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NextState = STATE_SRAM_BUSY;
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NextState = STATE_SRAM_BUSY;
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DCacheStall = 1'b1;
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DCacheStall = 1'b1;
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end
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end
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@ -505,11 +509,16 @@ module dcache
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end
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end
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STATE_MISS_WRITE_WORD: begin
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STATE_MISS_WRITE_WORD: begin
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DCacheStall = 1'b0;
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SRAMWordWriteEnableM = 1'b1;
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SRAMWordWriteEnableM = 1'b1;
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SetDirtyM = 1'b1;
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SetDirtyM = 1'b1;
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NextState = STATE_READY;
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SelAdrM = 1'b1;
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SelAdrM = 1'b1;
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if (AnyCPUReqE & SRAMWordWriteEnableM) begin
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NextState = STATE_SRAM_BUSY;
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DCacheStall = 1'b1;
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end else begin
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NextState = STATE_READY;
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DCacheStall = 1'b0;
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end
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end
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end
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STATE_MISS_EVICT_DIRTY: begin
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STATE_MISS_EVICT_DIRTY: begin
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@ -52,6 +52,7 @@ module controller(
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output logic [1:0] MemRWM,
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output logic [1:0] MemRWM,
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output logic CSRReadM, CSRWriteM, PrivilegedM,
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output logic CSRReadM, CSRWriteM, PrivilegedM,
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output logic SCE,
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output logic SCE,
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output logic [1:0] AtomicE,
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output logic [1:0] AtomicM,
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output logic [1:0] AtomicM,
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output logic [2:0] Funct3M,
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output logic [2:0] Funct3M,
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output logic RegWriteM, // for Hazard Unit
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output logic RegWriteM, // for Hazard Unit
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@ -84,7 +85,7 @@ module controller(
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logic TargetSrcD, W64D, MulDivD;
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logic TargetSrcD, W64D, MulDivD;
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logic CSRZeroSrcD;
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logic CSRZeroSrcD;
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logic CSRReadD;
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logic CSRReadD;
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logic [1:0] AtomicD, AtomicE;
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logic [1:0] AtomicD;
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logic CSRWriteD, CSRWriteE;
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logic CSRWriteD, CSRWriteE;
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logic InstrValidD, InstrValidE;
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logic InstrValidD, InstrValidE;
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logic PrivilegedD, PrivilegedE;
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logic PrivilegedD, PrivilegedE;
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@ -47,7 +47,9 @@ module ieu (
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// Memory stage interface
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// Memory stage interface
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input logic DataMisalignedM, // from LSU
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input logic DataMisalignedM, // from LSU
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input logic SquashSCW, // from LSU
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input logic SquashSCW, // from LSU
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output logic [1:0] MemRWE, // read/write control goes to LSU
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output logic [1:0] MemRWM, // read/write control goes to LSU
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output logic [1:0] MemRWM, // read/write control goes to LSU
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output logic [1:0] AtomicE, // atomic control goes to LSU
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output logic [1:0] AtomicM, // atomic control goes to LSU
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output logic [1:0] AtomicM, // atomic control goes to LSU
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output logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM, // Address and write data to LSU
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output logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM, // Address and write data to LSU
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@ -86,7 +88,6 @@ module ieu (
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logic RegWriteM, RegWriteW;
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logic RegWriteM, RegWriteW;
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logic MemReadE, CSRReadE;
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logic MemReadE, CSRReadE;
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logic JumpE;
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logic JumpE;
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logic [1:0] MemRWE;
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controller c(.*);
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controller c(.*);
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datapath dp(.*);
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datapath dp(.*);
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@ -37,9 +37,11 @@ module lsu
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// connected to cpu (controls)
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// connected to cpu (controls)
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input logic [1:0] MemRWM,
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input logic [1:0] MemRWM,
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input logic [1:0] MemRWE,
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input logic [2:0] Funct3M,
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input logic [2:0] Funct3M,
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input logic [6:0] Funct7M,
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input logic [6:0] Funct7M,
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input logic [1:0] AtomicM,
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input logic [1:0] AtomicM,
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input logic [1:0] AtomicE,
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output logic CommittedM,
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output logic CommittedM,
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output logic SquashSCW,
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output logic SquashSCW,
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output logic DataMisalignedM,
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output logic DataMisalignedM,
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@ -299,10 +301,12 @@ module lsu
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.StallW(StallW),
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.StallW(StallW),
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.FlushM(FlushM),
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.FlushM(FlushM),
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.FlushW(FlushW),
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.FlushW(FlushW),
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.MemRWE(MemRWE), // *** add to arb
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.MemRWM(MemRWMtoDCache),
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.MemRWM(MemRWMtoDCache),
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.Funct3M(Funct3MtoDCache),
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.Funct3M(Funct3MtoDCache),
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.Funct7M(Funct7M),
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.Funct7M(Funct7M),
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.AtomicM(AtomicMtoDCache),
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.AtomicM(AtomicMtoDCache),
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.AtomicE(AtomicE), // *** add to arb
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.MemAdrE(MemAdrEtoDCache), // *** add to arb
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.MemAdrE(MemAdrEtoDCache), // *** add to arb
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.MemPAdrM(MemPAdrM),
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.MemPAdrM(MemPAdrM),
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.WriteDataM(WriteDataM),
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.WriteDataM(WriteDataM),
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@ -63,6 +63,7 @@ module wallypipelinedhart
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// new signals that must connect through DP
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// new signals that must connect through DP
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logic MulDivE, W64E;
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logic MulDivE, W64E;
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logic CSRReadM, CSRWriteM, PrivilegedM;
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logic CSRReadM, CSRWriteM, PrivilegedM;
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logic [1:0] AtomicE;
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logic [1:0] AtomicM;
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logic [1:0] AtomicM;
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logic [`XLEN-1:0] SrcAE, SrcBE;
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logic [`XLEN-1:0] SrcAE, SrcBE;
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logic [`XLEN-1:0] SrcAM;
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logic [`XLEN-1:0] SrcAM;
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@ -73,6 +74,7 @@ module wallypipelinedhart
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logic [`XLEN-1:0] PCTargetE;
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logic [`XLEN-1:0] PCTargetE;
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logic [`XLEN-1:0] CSRReadValW, MulDivResultW;
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logic [`XLEN-1:0] CSRReadValW, MulDivResultW;
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logic [`XLEN-1:0] PrivilegedNextPCM;
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logic [`XLEN-1:0] PrivilegedNextPCM;
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logic [1:0] MemRWE;
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logic [1:0] MemRWM;
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logic [1:0] MemRWM;
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logic InstrValidM, InstrValidW;
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logic InstrValidM, InstrValidW;
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logic InstrMisalignedFaultM;
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logic InstrMisalignedFaultM;
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@ -174,9 +176,11 @@ module wallypipelinedhart
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.StallW(StallW),
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.StallW(StallW),
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.FlushW(FlushW),
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.FlushW(FlushW),
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// CPU interface
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// CPU interface
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.MemRWE(MemRWE),
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.MemRWM(MemRWM),
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.MemRWM(MemRWM),
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.Funct3M(Funct3M),
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.Funct3M(Funct3M),
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.Funct7M(InstrM[31:25]),
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.Funct7M(InstrM[31:25]),
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.AtomicE(AtomicE),
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.AtomicM(AtomicM),
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.AtomicM(AtomicM),
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.CommittedM(CommittedM),
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.CommittedM(CommittedM),
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.SquashSCW(SquashSCW),
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.SquashSCW(SquashSCW),
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