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mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00

Fixed back to back store issue.

Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
This commit is contained in:
Ross Thompson 2021-07-13 12:46:20 -05:00
parent 224e3b2991
commit 47e16f5629
5 changed files with 24 additions and 5 deletions

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@ -34,9 +34,11 @@ module dcache
input logic FlushW, input logic FlushW,
// cpu side // cpu side
input logic [1:0] MemRWE,
input logic [1:0] MemRWM, input logic [1:0] MemRWM,
input logic [2:0] Funct3M, input logic [2:0] Funct3M,
input logic [6:0] Funct7M, input logic [6:0] Funct7M,
input logic [1:0] AtomicE,
input logic [1:0] AtomicM, input logic [1:0] AtomicM,
input logic [`XLEN-1:0] MemAdrE, // virtual address, but we only use the lower 12 bits. input logic [`XLEN-1:0] MemAdrE, // virtual address, but we only use the lower 12 bits.
input logic [`PA_BITS-1:0] MemPAdrM, // physical address input logic [`PA_BITS-1:0] MemPAdrM, // physical address
@ -299,6 +301,7 @@ module dcache
// control path *** eventually move to own module. // control path *** eventually move to own module.
logic AnyCPUReqM; logic AnyCPUReqM;
logic AnyCPUReqE;
logic FetchCountFlag; logic FetchCountFlag;
logic PreCntEn; logic PreCntEn;
logic CntEn; logic CntEn;
@ -349,6 +352,7 @@ module dcache
assign AnyCPUReqM = |MemRWM | (|AtomicM); assign AnyCPUReqM = |MemRWM | (|AtomicM);
assign AnyCPUReqE = |MemRWE | (|AtomicE);
assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL:0]); assign FetchCountFlag = (FetchCount == FetchCountThreshold[LOGWPL:0]);
flopenr #(LOGWPL+1) flopenr #(LOGWPL+1)
@ -406,7 +410,7 @@ module dcache
case (CurrState) case (CurrState)
STATE_READY: begin STATE_READY: begin
// sram busy // sram busy
if (AnyCPUReqM & SRAMWordWriteEnableW) begin if (AnyCPUReqE & SRAMWordWriteEnableM) begin
NextState = STATE_SRAM_BUSY; NextState = STATE_SRAM_BUSY;
DCacheStall = 1'b1; DCacheStall = 1'b1;
end end
@ -505,11 +509,16 @@ module dcache
end end
STATE_MISS_WRITE_WORD: begin STATE_MISS_WRITE_WORD: begin
DCacheStall = 1'b0;
SRAMWordWriteEnableM = 1'b1; SRAMWordWriteEnableM = 1'b1;
SetDirtyM = 1'b1; SetDirtyM = 1'b1;
NextState = STATE_READY;
SelAdrM = 1'b1; SelAdrM = 1'b1;
if (AnyCPUReqE & SRAMWordWriteEnableM) begin
NextState = STATE_SRAM_BUSY;
DCacheStall = 1'b1;
end else begin
NextState = STATE_READY;
DCacheStall = 1'b0;
end
end end
STATE_MISS_EVICT_DIRTY: begin STATE_MISS_EVICT_DIRTY: begin

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@ -52,6 +52,7 @@ module controller(
output logic [1:0] MemRWM, output logic [1:0] MemRWM,
output logic CSRReadM, CSRWriteM, PrivilegedM, output logic CSRReadM, CSRWriteM, PrivilegedM,
output logic SCE, output logic SCE,
output logic [1:0] AtomicE,
output logic [1:0] AtomicM, output logic [1:0] AtomicM,
output logic [2:0] Funct3M, output logic [2:0] Funct3M,
output logic RegWriteM, // for Hazard Unit output logic RegWriteM, // for Hazard Unit
@ -84,7 +85,7 @@ module controller(
logic TargetSrcD, W64D, MulDivD; logic TargetSrcD, W64D, MulDivD;
logic CSRZeroSrcD; logic CSRZeroSrcD;
logic CSRReadD; logic CSRReadD;
logic [1:0] AtomicD, AtomicE; logic [1:0] AtomicD;
logic CSRWriteD, CSRWriteE; logic CSRWriteD, CSRWriteE;
logic InstrValidD, InstrValidE; logic InstrValidD, InstrValidE;
logic PrivilegedD, PrivilegedE; logic PrivilegedD, PrivilegedE;

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@ -47,7 +47,9 @@ module ieu (
// Memory stage interface // Memory stage interface
input logic DataMisalignedM, // from LSU input logic DataMisalignedM, // from LSU
input logic SquashSCW, // from LSU input logic SquashSCW, // from LSU
output logic [1:0] MemRWE, // read/write control goes to LSU
output logic [1:0] MemRWM, // read/write control goes to LSU output logic [1:0] MemRWM, // read/write control goes to LSU
output logic [1:0] AtomicE, // atomic control goes to LSU
output logic [1:0] AtomicM, // atomic control goes to LSU output logic [1:0] AtomicM, // atomic control goes to LSU
output logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM, // Address and write data to LSU output logic [`XLEN-1:0] MemAdrM, MemAdrE, WriteDataM, // Address and write data to LSU
@ -86,7 +88,6 @@ module ieu (
logic RegWriteM, RegWriteW; logic RegWriteM, RegWriteW;
logic MemReadE, CSRReadE; logic MemReadE, CSRReadE;
logic JumpE; logic JumpE;
logic [1:0] MemRWE;
controller c(.*); controller c(.*);
datapath dp(.*); datapath dp(.*);

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@ -37,9 +37,11 @@ module lsu
// connected to cpu (controls) // connected to cpu (controls)
input logic [1:0] MemRWM, input logic [1:0] MemRWM,
input logic [1:0] MemRWE,
input logic [2:0] Funct3M, input logic [2:0] Funct3M,
input logic [6:0] Funct7M, input logic [6:0] Funct7M,
input logic [1:0] AtomicM, input logic [1:0] AtomicM,
input logic [1:0] AtomicE,
output logic CommittedM, output logic CommittedM,
output logic SquashSCW, output logic SquashSCW,
output logic DataMisalignedM, output logic DataMisalignedM,
@ -299,10 +301,12 @@ module lsu
.StallW(StallW), .StallW(StallW),
.FlushM(FlushM), .FlushM(FlushM),
.FlushW(FlushW), .FlushW(FlushW),
.MemRWE(MemRWE), // *** add to arb
.MemRWM(MemRWMtoDCache), .MemRWM(MemRWMtoDCache),
.Funct3M(Funct3MtoDCache), .Funct3M(Funct3MtoDCache),
.Funct7M(Funct7M), .Funct7M(Funct7M),
.AtomicM(AtomicMtoDCache), .AtomicM(AtomicMtoDCache),
.AtomicE(AtomicE), // *** add to arb
.MemAdrE(MemAdrEtoDCache), // *** add to arb .MemAdrE(MemAdrEtoDCache), // *** add to arb
.MemPAdrM(MemPAdrM), .MemPAdrM(MemPAdrM),
.WriteDataM(WriteDataM), .WriteDataM(WriteDataM),

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@ -63,6 +63,7 @@ module wallypipelinedhart
// new signals that must connect through DP // new signals that must connect through DP
logic MulDivE, W64E; logic MulDivE, W64E;
logic CSRReadM, CSRWriteM, PrivilegedM; logic CSRReadM, CSRWriteM, PrivilegedM;
logic [1:0] AtomicE;
logic [1:0] AtomicM; logic [1:0] AtomicM;
logic [`XLEN-1:0] SrcAE, SrcBE; logic [`XLEN-1:0] SrcAE, SrcBE;
logic [`XLEN-1:0] SrcAM; logic [`XLEN-1:0] SrcAM;
@ -73,6 +74,7 @@ module wallypipelinedhart
logic [`XLEN-1:0] PCTargetE; logic [`XLEN-1:0] PCTargetE;
logic [`XLEN-1:0] CSRReadValW, MulDivResultW; logic [`XLEN-1:0] CSRReadValW, MulDivResultW;
logic [`XLEN-1:0] PrivilegedNextPCM; logic [`XLEN-1:0] PrivilegedNextPCM;
logic [1:0] MemRWE;
logic [1:0] MemRWM; logic [1:0] MemRWM;
logic InstrValidM, InstrValidW; logic InstrValidM, InstrValidW;
logic InstrMisalignedFaultM; logic InstrMisalignedFaultM;
@ -174,9 +176,11 @@ module wallypipelinedhart
.StallW(StallW), .StallW(StallW),
.FlushW(FlushW), .FlushW(FlushW),
// CPU interface // CPU interface
.MemRWE(MemRWE),
.MemRWM(MemRWM), .MemRWM(MemRWM),
.Funct3M(Funct3M), .Funct3M(Funct3M),
.Funct7M(InstrM[31:25]), .Funct7M(InstrM[31:25]),
.AtomicE(AtomicE),
.AtomicM(AtomicM), .AtomicM(AtomicM),
.CommittedM(CommittedM), .CommittedM(CommittedM),
.SquashSCW(SquashSCW), .SquashSCW(SquashSCW),