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Update trap.sv

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Program clean up
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Harshini Srinath 2023-06-12 20:31:44 -07:00 committed by GitHub
parent e2af1fabd2
commit 475e11e03f
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1 changed files with 8 additions and 8 deletions
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src/privileged/trap.sv
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@ -63,13 +63,13 @@ module trap import cvw::*; #(parameter cvw_t P) (
assign MIntGlobalEnM = (PrivilegeModeW != P.M_MODE) | STATUS_MIE; // if M ints enabled or lower priv 3.1.9 assign MIntGlobalEnM = (PrivilegeModeW != P.M_MODE) | STATUS_MIE; // if M ints enabled or lower priv 3.1.9
assign SIntGlobalEnM = (PrivilegeModeW == P.U_MODE) | ((PrivilegeModeW == P.S_MODE) & STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9 assign SIntGlobalEnM = (PrivilegeModeW == P.U_MODE) | ((PrivilegeModeW == P.S_MODE) & STATUS_SIE); // if in lower priv mode, or if S ints enabled and not in higher priv mode 3.1.9
assign PendingIntsM = MIP_REGW & MIE_REGW; assign PendingIntsM = MIP_REGW & MIE_REGW;
assign IntPendingM = |PendingIntsM; assign IntPendingM = |PendingIntsM;
assign Committed = CommittedM | CommittedF; assign Committed = CommittedM | CommittedF;
assign EnabledIntsM = ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW); assign EnabledIntsM = ({12{MIntGlobalEnM}} & PendingIntsM & ~MIDELEG_REGW | {12{SIntGlobalEnM}} & PendingIntsM & MIDELEG_REGW);
assign ValidIntsM = {12{~Committed}} & EnabledIntsM; assign ValidIntsM = {12{~Committed}} & EnabledIntsM;
assign InterruptM = (|ValidIntsM) & InstrValidM; // suppress interrupt if the memory system has partially processed a request. assign InterruptM = (|ValidIntsM) & InstrValidM; // suppress interrupt if the memory system has partially processed a request.
assign DelegateM = P.S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM] : MEDELEG_REGW[CauseM]) & assign DelegateM = P.S_SUPPORTED & (InterruptM ? MIDELEG_REGW[CauseM] : MEDELEG_REGW[CauseM]) &
(PrivilegeModeW == P.U_MODE | PrivilegeModeW == P.S_MODE); (PrivilegeModeW == P.U_MODE | PrivilegeModeW == P.S_MODE);
/////////////////////////////////////////// ///////////////////////////////////////////
@ -88,7 +88,7 @@ module trap import cvw::*; #(parameter cvw_t P) (
LoadAccessFaultM | StoreAmoAccessFaultM; LoadAccessFaultM | StoreAmoAccessFaultM;
// coverage on // coverage on
assign TrapM = ExceptionM | InterruptM; assign TrapM = ExceptionM | InterruptM;
assign RetM = mretM | sretM; assign RetM = mretM | sretM;
/////////////////////////////////////////// ///////////////////////////////////////////
// Cause priority defined in table 3.7 of 20190608 privileged spec // Cause priority defined in table 3.7 of 20190608 privileged spec