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Getting closer to figuring out the lost ethernet frame bugs.

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This commit is contained in:
Ross Thompson 2024-06-13 15:46:54 -07:00
parent c9f51df34a
commit 47523c97ac
4 changed files with 31 additions and 14 deletions
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2
fpga/rvvidaemon/Makefile
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@ -1,7 +1,7 @@
all: rvvidaemon all: rvvidaemon
rvvidaemon: rvvidaemon.o rvvidaemon: rvvidaemon.o
gcc $^ -o rvvidaemon gcc $^ /opt/riscv/ImperasDV-OpenHW/Imperas/lib/Linux64/ImperasLib/imperas.com/verification/riscv/1.0/model.so -o rvvidaemon
%.o:%.c %.o:%.c
gcc -c $^ -o $@ gcc -c $^ -o $@

8
fpga/src/fpgaTopArtyA7.sv
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@ -1122,9 +1122,9 @@ module fpgaTop
rvvisynth #(P, MAX_CSRS) rvvisynth(.clk(CPUCLK), .reset(bus_struct_reset), .valid, .rvvi); rvvisynth #(P, MAX_CSRS) rvvisynth(.clk(CPUCLK), .reset(bus_struct_reset), .valid, .rvvi);
// axi 4 write data channel // axi 4 write data channel
logic [31:0] RvviAxiWdata; (* mark_debug = "true" *) logic [31:0] RvviAxiWdata;
logic [3:0] RvviAxiWstrb; (* mark_debug = "true" *) logic [3:0] RvviAxiWstrb;
logic RvviAxiWlast; (* mark_debug = "true" *) logic RvviAxiWlast;
(* mark_debug = "true" *) logic RvviAxiWvalid; (* mark_debug = "true" *) logic RvviAxiWvalid;
(* mark_debug = "true" *) logic RvviAxiWready; (* mark_debug = "true" *) logic RvviAxiWready;
@ -1134,7 +1134,7 @@ module fpgaTop
packetizer #(P, MAX_CSRS) packetizer(.rvvi, .valid, .m_axi_aclk(CPUCLK), .m_axi_aresetn(~bus_struct_reset), .RVVIStall, packetizer #(P, MAX_CSRS) packetizer(.rvvi, .valid, .m_axi_aclk(CPUCLK), .m_axi_aresetn(~bus_struct_reset), .RVVIStall,
.RvviAxiWdata, .RvviAxiWstrb, .RvviAxiWlast, .RvviAxiWvalid, .RvviAxiWready); .RvviAxiWdata, .RvviAxiWstrb, .RvviAxiWlast, .RvviAxiWvalid, .RvviAxiWready);
eth_mac_mii_fifo #("GENERIC", "BUFG", 32) ethernet(.rst(bus_struct_reset), .logic_clk(CPUCLK), .logic_rst(bus_struct_reset), eth_mac_mii_fifo #(.TARGET("GENERIC"), .CLOCK_INPUT_STYLE("BUFG"), .AXIS_DATA_WIDTH(32), .TX_FIFO_DEPTH(1024)) ethernet(.rst(bus_struct_reset), .logic_clk(CPUCLK), .logic_rst(bus_struct_reset),
.tx_axis_tdata(RvviAxiWdata), .tx_axis_tkeep(RvviAxiWstrb), .tx_axis_tvalid(RvviAxiWvalid), .tx_axis_tready(RvviAxiWready), .tx_axis_tdata(RvviAxiWdata), .tx_axis_tkeep(RvviAxiWstrb), .tx_axis_tvalid(RvviAxiWvalid), .tx_axis_tready(RvviAxiWready),
.tx_axis_tlast(RvviAxiWlast), .tx_axis_tuser('0), .rx_axis_tdata(), .rx_axis_tkeep(), .rx_axis_tvalid(), .rx_axis_tready(1'b1), .tx_axis_tlast(RvviAxiWlast), .tx_axis_tuser('0), .rx_axis_tdata(), .rx_axis_tkeep(), .rx_axis_tvalid(), .rx_axis_tready(1'b1),
.rx_axis_tlast(), .rx_axis_tuser(), .rx_axis_tlast(), .rx_axis_tuser(),

4
src/rvvi/mii_phy_if.sv
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@ -53,8 +53,8 @@ module mii_phy_if #
output wire mac_mii_rx_er, output wire mac_mii_rx_er,
output wire mac_mii_tx_clk, output wire mac_mii_tx_clk,
output wire mac_mii_tx_rst, output wire mac_mii_tx_rst,
input wire [3:0] mac_mii_txd, (* mark_debug = "true" *) input wire [3:0] mac_mii_txd,
input wire mac_mii_tx_en, (* mark_debug = "true" *) input wire mac_mii_tx_en,
input wire mac_mii_tx_er, input wire mac_mii_tx_er,
/* /*

25
src/rvvi/packetizer.sv
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@ -59,23 +59,32 @@ module packetizer import cvw::*; #(parameter cvw_t P,
logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvviDelay; logic [187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)-1:0] rvviDelay;
typedef enum {STATE_RDY, STATE_WAIT, STATE_TRANS, STATE_TRANS_DONE} statetype; typedef enum {STATE_RST, STATE_COUNT, STATE_RDY, STATE_WAIT, STATE_TRANS, STATE_TRANS_INSERT_DELAY} statetype;
statetype CurrState, NextState; (* mark_debug = "true" *) statetype CurrState, NextState;
logic [31:0] RstCount;
logic RstCountRst, RstCountEn, CountFlag, DelayFlag;
always_ff @(posedge m_axi_aclk) begin always_ff @(posedge m_axi_aclk) begin
if(~m_axi_aresetn) CurrState <= STATE_RDY; if(~m_axi_aresetn) CurrState <= STATE_RST;
else CurrState <= NextState; else CurrState <= NextState;
end end
always_comb begin always_comb begin
case(CurrState) case(CurrState)
STATE_RST: NextState = STATE_COUNT;
STATE_COUNT: if (CountFlag) NextState = STATE_RDY;
else NextState = STATE_COUNT;
STATE_RDY: if (TransReady & valid) NextState = STATE_TRANS; STATE_RDY: if (TransReady & valid) NextState = STATE_TRANS;
else if(~TransReady & valid) NextState = STATE_WAIT; else if(~TransReady & valid) NextState = STATE_WAIT;
else NextState = STATE_RDY; else NextState = STATE_RDY;
STATE_WAIT: if(TransReady) NextState = STATE_TRANS; STATE_WAIT: if(TransReady) NextState = STATE_TRANS;
else NextState = STATE_WAIT; else NextState = STATE_WAIT;
STATE_TRANS: if(BurstDone) NextState = STATE_RDY; STATE_TRANS: if(BurstDone) NextState = STATE_TRANS_INSERT_DELAY;
else NextState = STATE_TRANS; else NextState = STATE_TRANS;
STATE_TRANS_INSERT_DELAY: if(DelayFlag) NextState = STATE_RDY;
else NextState = STATE_TRANS_INSERT_DELAY;
default: NextState = STATE_RDY; default: NextState = STATE_RDY;
endcase endcase
end end
@ -84,6 +93,14 @@ module packetizer import cvw::*; #(parameter cvw_t P,
assign TransReady = RvviAxiWready; assign TransReady = RvviAxiWready;
assign WordCountEnable = (CurrState == STATE_RDY & valid) | (CurrState == STATE_TRANS & TransReady); assign WordCountEnable = (CurrState == STATE_RDY & valid) | (CurrState == STATE_TRANS & TransReady);
assign WordCountReset = CurrState == STATE_RDY; assign WordCountReset = CurrState == STATE_RDY;
assign RstCountEn = CurrState == STATE_COUNT | CurrState == STATE_TRANS_INSERT_DELAY;
assign RstCountRst = CurrState == STATE_RST | CurrState == STATE_TRANS;
// have to count at least 250 ms after reset pulled to wait for the phy to actually be ready
// at 20MHz 250 ms is 250e-3 / (1/20e6) = 5,000,000.
counter #(32) rstcounter(m_axi_aclk, RstCountRst, RstCountEn, RstCount);
assign CountFlag = RstCount == 32'd100000000;
assign DelayFlag = RstCount == 32'd48;
flopenr #(187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)) rvvireg(m_axi_aclk, ~m_axi_aresetn, valid, rvvi, rvviDelay); flopenr #(187+(3*P.XLEN) + MAX_CSRS*(P.XLEN+12)) rvvireg(m_axi_aclk, ~m_axi_aresetn, valid, rvvi, rvviDelay);