From 0e08c4393de324e0c3d12c7f4042670106af035f Mon Sep 17 00:00:00 2001 From: Noah Limpert Date: Wed, 29 Mar 2023 13:07:34 -0700 Subject: [PATCH 01/40] access of 4KiB spaced mem locations, aim to fill + evict a line of all 4 ways --- tests/coverage/lsu.S | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 tests/coverage/lsu.S diff --git a/tests/coverage/lsu.S b/tests/coverage/lsu.S new file mode 100644 index 000000000..92d01b196 --- /dev/null +++ b/tests/coverage/lsu.S @@ -0,0 +1,34 @@ +//lsu.S +// A set of tests meant to stress the LSU to increase coverage +// Manuel Alejandro Mendoza Manriquez mmendozamanriquez@g.hmc.edu +// Noah Limpert nlimpert@g.hmc.edu +// March 28 2023 + + +// Test 1 +// Cache ways 1,2,3 do not have SelFlush = 0 +// To make SelFlush = 0 we must evict lines from ways 1,2,3 +// Will load 4 words with same tags, filling 4 ways of cache +// edit and store these words so that dirty bit is set ( is this necessary?) +// Will then load 4 more words, evicting the previous 4 words +// will make SelFlush = 0 for all 4 ways. + +// Load code to initialize stack, handle interrupts, terminate +#include "WALLY-init-lib.h" + +main: + li t0, 4096 //offset such that set will be same + li t1, 0 #t1 = i = 0 + li t2, 8 # n = 8 + add t3, sp, 0 // what our offset for loads and stores will be + +for1: bge t1, t2, done + add t3, t3, t0 + lw t4, 0(t3) + addi t4, t4, 1 + sw t4, 0(t3) + addi t1, t1, 1 + j for1 + + + From 0fea40282ad829a7823ab286ab02a070ab574fa6 Mon Sep 17 00:00:00 2001 From: Noah Limpert Date: Wed, 29 Mar 2023 13:08:33 -0700 Subject: [PATCH 02/40] instantiate 5 4KiB arrays, aim to thrash all 4 ways --- tests/coverage/lsuGB.S | 99 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 tests/coverage/lsuGB.S diff --git a/tests/coverage/lsuGB.S b/tests/coverage/lsuGB.S new file mode 100644 index 000000000..8a902ba7f --- /dev/null +++ b/tests/coverage/lsuGB.S @@ -0,0 +1,99 @@ +//lsuGB.S +// A set of tests meant to stress the LSU to increase coverage +// Manuel Alejandro Mendoza Manriquez mmendozamanriquez@g.hmc.edu +// Noah Limpert nlimpert@g.hmc.edu +// March 28 2023 + + +// Test 2 +//Try to thrash ! used godbolt! +// Cache ways 1,2,3 do not have SelFlush = 0 +// To make SelFlush = 0 we must evict lines from ways 1,2,3 +// Will load 4 words with same tags, filling 4 ways of cache +// edit and store these words so that dirty bit is set ( is this necessary?) +// Will then load 4 more words, evicting the previous 4 words +// will make SelFlush = 0 for all 4 ways. + +// Load code to initialize stack, handle interrupts, terminate +#include "WALLY-init-lib.h" + +main: + addi sp,sp,-32 + sd s0,24(sp) + addi s0,sp,32 + li t1,-20480 + add sp,sp,t1 + sw zero,-20(s0) + j .L2 +.L3: + li a5,-4096 + addi a4,s0,-16 + add a4,a4,a5 + lw a5,-20(s0) + slli a5,a5,2 + add a5,a4,a5 + lw a4,-8(a5) + li a5,-8192 + addi a3,s0,-16 + add a3,a3,a5 + lw a5,-20(s0) + slli a5,a5,2 + add a5,a3,a5 + sw a4,-8(a5) + li a5,-8192 + addi a4,s0,-16 + add a4,a4,a5 + lw a5,-20(s0) + slli a5,a5,2 + add a5,a4,a5 + lw a4,-8(a5) + li a5,-12288 + addi a3,s0,-16 + add a3,a3,a5 + lw a5,-20(s0) + slli a5,a5,2 + add a5,a3,a5 + sw a4,-8(a5) + li a5,-12288 + addi a4,s0,-16 + add a4,a4,a5 + lw a5,-20(s0) + slli a5,a5,2 + add a5,a4,a5 + lw a4,-8(a5) + li a5,-16384 + addi a3,s0,-16 + add a3,a3,a5 + lw a5,-20(s0) + slli a5,a5,2 + add a5,a3,a5 + sw a4,-8(a5) + li a5,-16384 + addi a4,s0,-16 + add a4,a4,a5 + lw a5,-20(s0) + slli a5,a5,2 + add a5,a4,a5 + lw a4,-8(a5) + li a5,-20480 + addi a3,s0,-16 + add a3,a3,a5 + lw a5,-20(s0) + slli a5,a5,2 + add a5,a3,a5 + sw a4,-8(a5) + lw a5,-20(s0) + addiw a5,a5,1 + sw a5,-20(s0) +.L2: + lw a5,-20(s0) + sext.w a4,a5 + li a5,1023 + ble a4,a5,.L3 + nop + nop + li t1,20480 + add sp,sp,t1 + ld s0,24(sp) + addi sp,sp,32 + j done \ No newline at end of file From f7702436896f88b9cd921ac95e241a32ffb6499f Mon Sep 17 00:00:00 2001 From: Noah Limpert Date: Mon, 3 Apr 2023 21:54:27 -0700 Subject: [PATCH 03/40] Test File for Pull Request, Attempt to fill all four ways --- tests/coverage/lsu_test1.S | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 tests/coverage/lsu_test1.S diff --git a/tests/coverage/lsu_test1.S b/tests/coverage/lsu_test1.S new file mode 100644 index 000000000..92d01b196 --- /dev/null +++ b/tests/coverage/lsu_test1.S @@ -0,0 +1,34 @@ +//lsu.S +// A set of tests meant to stress the LSU to increase coverage +// Manuel Alejandro Mendoza Manriquez mmendozamanriquez@g.hmc.edu +// Noah Limpert nlimpert@g.hmc.edu +// March 28 2023 + + +// Test 1 +// Cache ways 1,2,3 do not have SelFlush = 0 +// To make SelFlush = 0 we must evict lines from ways 1,2,3 +// Will load 4 words with same tags, filling 4 ways of cache +// edit and store these words so that dirty bit is set ( is this necessary?) +// Will then load 4 more words, evicting the previous 4 words +// will make SelFlush = 0 for all 4 ways. + +// Load code to initialize stack, handle interrupts, terminate +#include "WALLY-init-lib.h" + +main: + li t0, 4096 //offset such that set will be same + li t1, 0 #t1 = i = 0 + li t2, 8 # n = 8 + add t3, sp, 0 // what our offset for loads and stores will be + +for1: bge t1, t2, done + add t3, t3, t0 + lw t4, 0(t3) + addi t4, t4, 1 + sw t4, 0(t3) + addi t1, t1, 1 + j for1 + + + From 3fc6bb0c40a44c50eaba12d96dedec5fc1c098ec Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Tue, 11 Apr 2023 16:59:11 -0700 Subject: [PATCH 04/40] Exclude (FlushStage & SetValidWay) condition for RO caches Spent a long time trying to find a way to see if this condition was possible, only to become relativly convinced that it isn't. Basically, since RO cache writes only happen after a long period of stall for the bus access, there's no way a flushD can be active at the same time as a RO cache write. TrapM causes a FlushD, but interrupts are gated by the "commited" logic and the exception pipeline stalls. I feel like its worth keeping the logic to be safe so I've chosen to exclude it rather than explicitely remove it. --- src/cache/cacheway.sv | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 174b82c59..568e626e5 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -101,14 +101,21 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, if (!READ_ONLY_CACHE) begin assign SetDirtyWay = SetDirty & SelData; assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage; + assign SetValidEN = SetValidWay & ~FlushStage; end else begin + // Don't cover FlushStage assertion during SetValidWay. + // it's not explicitely gated anywhere, but for read-only caches, + // there's no way that a FlushD can happen during the write stage + // of a fetch. + // coverage off -item e 1 -fecexprrow 4 assign SelectedWriteWordEn = SetValidWay & ~FlushStage; + // coverage off -item e 1 -fecexprrow 4 + assign SetValidEN = SetValidWay & ~FlushStage; end // If writing the whole line set all write enables to 1, else only set the correct word. assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR - assign SetValidEN = SetValidWay & ~FlushStage; ///////////////////////////////////////////////////////////////////////////////////////////// // Tag Array From 6dce58125b6c7459b627071711cf6885deaa1b9b Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Tue, 11 Apr 2023 17:10:09 -0700 Subject: [PATCH 05/40] Remove FlushStage Logic from CacheLRU For coverage. LRUWriteEn is gated by FlushStage in cache.sv, so removing the signal completely avoids future confusion. Update cache.sv to reflect cacheLRU edit. --- src/cache/cache.sv | 2 +- src/cache/cacheLRU.sv | 9 +++------ 2 files changed, 4 insertions(+), 7 deletions(-) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index c01c714b1..9854152e2 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -122,7 +122,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE // Select victim way for associative caches if(NUMWAYS > 1) begin:vict cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU( - .clk, .reset, .CacheEn, .FlushStage, .HitWay, .ValidWay, .VictimWay, .CacheSet, .LRUWriteEn(LRUWriteEn & ~FlushStage), + .clk, .reset, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSet, .LRUWriteEn(LRUWriteEn & ~FlushStage), .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache, .FlushCache); end else assign VictimWay = 1'b1; // one hot. diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index 1e7101365..d8de983f7 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -32,8 +32,7 @@ module cacheLRU #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128) ( input logic clk, - input logic reset, - input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations) + input logic reset, input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant input logic [NUMWAYS-1:0] HitWay, // Which way is valid and matches PAdr's tag input logic [NUMWAYS-1:0] ValidWay, // Which ways for a particular set are valid, ignores tag @@ -134,11 +133,9 @@ module cacheLRU always_ff @(posedge clk) begin if (reset) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0; if(CacheEn) begin - // if((InvalidateCache | FlushCache) & ~FlushStage) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0; - if (LRUWriteEn & ~FlushStage) begin + if(LRUWriteEn) LRUMemory[PAdr] <= NextLRU; - end - if(LRUWriteEn & ~FlushStage & (PAdr == CacheSet)) + if(LRUWriteEn & (PAdr == CacheSet)) CurrLRU <= #1 NextLRU; else CurrLRU <= #1 LRUMemory[CacheSet]; From 214abc7006e48eb2340aa56f00a088354d0c6bcb Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Tue, 11 Apr 2023 23:05:04 -0700 Subject: [PATCH 06/40] Make AdrSelMux and CacheBusAdrMux mux2 if READ_ONLY_CACHE Some address options are only used in the D$ case. --- src/cache/cache.sv | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 9854152e2..19cc84c51 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -73,7 +73,6 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE logic SelAdr; - logic [1:0] AdrSelMuxSel; logic [SETLEN-1:0] CacheSet; logic [LINELEN-1:0] LineWriteData; logic ClearDirty, SetDirty, SetValid; @@ -109,10 +108,18 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE // and FlushAdr when handling D$ flushes // The icache must update to the newest PCNextF on flush as it is probably a trap. Trap // sets PCNextF to XTVEC and the icache must start reading the instruction. - assign AdrSelMuxSel = {SelFlush, ((SelAdr | SelHPTW) & ~((READ_ONLY_CACHE == 1) & FlushStage))}; - mux3 #(SETLEN) AdrSelMux(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr, + if (!READ_ONLY_CACHE) begin + logic [1:0] AdrSelMuxSel; + assign AdrSelMuxSel = {SelFlush, SelAdr | SelHPTW}; + mux3 #(SETLEN) AdrSelMux(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr, AdrSelMuxSel, CacheSet); - + end + else begin + logic AdrSelMuxSel; + assign AdrSelMuxSel = ((SelAdr | SelHPTW) & ~FlushStage); + mux2 #(SETLEN) AdrSelMux(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], + AdrSelMuxSel, CacheSet); + end // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0]( .clk, .reset, .CacheEn, .CacheSet, .PAdr, .LineWriteData, .LineByteMask, @@ -152,11 +159,14 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE .PAdr(WordOffsetAddr), .ReadDataLine, .ReadDataWord); // Bus address for fetch, writeback, or flush writeback - mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), - .d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), - .d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}), - .s({SelFlush, SelWriteback}), .y(CacheBusAdr)); - + if (!READ_ONLY_CACHE) + mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), + .d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), + .d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}), + .s({SelFlush, SelWriteback}), .y(CacheBusAdr)); + else + assign CacheBusAdr = {PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}; + ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path ///////////////////////////////////////////////////////////////////////////////////////////// From 1ce2ab5daa7cd8d7b708894d6443bc00916c6905 Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Tue, 11 Apr 2023 23:05:56 -0700 Subject: [PATCH 07/40] Coverage and readability improvements to LRUUpdate logic The genvar stuff was switched to readable names to make it easier to understand for the first time. In the LRUUpdate logic for loop, a special case was added for simpler logic in the case of the root node, to hit coverage. --- src/cache/cacheLRU.sv | 40 +++++++++++++++++++++++++--------------- 1 file changed, 25 insertions(+), 15 deletions(-) diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index d8de983f7..5f1c199a9 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -89,16 +89,26 @@ module cacheLRU assign WayExpanded[StartIndex : EndIndex] = {{DuplicationFactor}{WayEncoded[row]}}; end - genvar r, a, s; + genvar node; assign LRUUpdate[NUMWAYS-2] = '1; - for(s = NUMWAYS-2; s >= NUMWAYS/2; s--) begin : enables - localparam p = NUMWAYS - s - 1; - localparam g = log2(p); - localparam t0 = s - p; - localparam t1 = t0 - 1; - localparam r = LOGNUMWAYS - g; - assign LRUUpdate[t0] = LRUUpdate[s] & ~WayEncoded[r]; - assign LRUUpdate[t1] = LRUUpdate[s] & WayEncoded[r]; + for(node = NUMWAYS-2; node >= NUMWAYS/2; node--) begin : enables + localparam ctr = NUMWAYS - node - 1; + localparam ctr_depth = log2(ctr); + localparam lchild = node - ctr; + localparam rchild = lchild - 1; + localparam r = LOGNUMWAYS - ctr_depth; + + // the child node will be updated if its parent was updated and + // the WayEncoded bit was the correct value. + // The if statement is only there for coverage since LRUUpdate[root] is always 1. + if (node == NUMWAYS-2) begin + assign LRUUpdate[lchild] = ~WayEncoded[r]; + assign LRUUpdate[rchild] = WayEncoded[r]; + end + else begin + assign LRUUpdate[lchild] = LRUUpdate[node] & ~WayEncoded[r]; + assign LRUUpdate[rchild] = LRUUpdate[node] & WayEncoded[r]; + end end // The root node of the LRU tree will always be selected in LRUUpdate. No mux needed. @@ -106,15 +116,15 @@ module cacheLRU mux2 #(1) LRUMuxes[NUMWAYS-3:0](CurrLRU[NUMWAYS-3:0], ~WayExpanded[NUMWAYS-3:0], LRUUpdate[NUMWAYS-3:0], NextLRU[NUMWAYS-3:0]); // Compute next victim way. - for(s = NUMWAYS-2; s >= NUMWAYS/2; s--) begin - localparam t0 = 2*s - NUMWAYS; + for(node = NUMWAYS-2; node >= NUMWAYS/2; node--) begin + localparam t0 = 2*node - NUMWAYS; localparam t1 = t0 + 1; - assign Intermediate[s] = CurrLRU[s] ? Intermediate[t0] : Intermediate[t1]; + assign Intermediate[node] = CurrLRU[node] ? Intermediate[t0] : Intermediate[t1]; end - for(s = NUMWAYS/2-1; s >= 0; s--) begin - localparam int0 = (NUMWAYS/2-1-s)*2; + for(node = NUMWAYS/2-1; node >= 0; node--) begin + localparam int0 = (NUMWAYS/2-1-node)*2; localparam int1 = int0 + 1; - assign Intermediate[s] = CurrLRU[s] ? int1[LOGNUMWAYS-1:0] : int0[LOGNUMWAYS-1:0]; + assign Intermediate[node] = CurrLRU[node] ? int1[LOGNUMWAYS-1:0] : int0[LOGNUMWAYS-1:0]; end logic [NUMWAYS-1:0] FirstZero; From 729f81a0df9de145ec82ac3780809d2ff8fdead2 Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Wed, 12 Apr 2023 00:48:06 -0700 Subject: [PATCH 08/40] refactor cachefsm to get full coverage I had to exclude i$ states in coverage-exclusions-rv64gc.do, but it's referred to by scope, which should be pretty robust --- sim/coverage-exclusions-rv64gc.do | 6 + src/cache/cachefsm.sv | 195 +++++++++++++++++++----------- 2 files changed, 128 insertions(+), 73 deletions(-) diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index d58e4c514..3e880b502 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -32,6 +32,12 @@ # This is ugly to exlcude the whole file - is there a better option? // coverage off isn't working coverage exclude -srcfile lzc.sv +# Exclude D$ states from coverage in the I$ instance of cachefsm. +# This is cleaner than trying to set an I$-specific pragma in cachefsm.sv +# Also exclude the write line to ready transition for the I$ since we can't get a flush +# during this operation. +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -fstate CurrState STATE_FLUSH STATE_FLUSH_WRITEBACK STATE_FLUSH_WRITEBACK +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -ftrans CurrState STATE_WRITE_LINE->STATE_READY ###################### # Toggle exclusions diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index d1d54097e..a42176325 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -86,18 +86,25 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( statetype CurrState, NextState; - assign AMO = CacheAtomic[1] & (&CacheRW); - assign StoreAMO = AMO | CacheRW[0]; + // no atomic operations on i$ + if (!READ_ONLY_CACHE) begin + assign AMO = CacheAtomic[1] & (&CacheRW); + assign StoreAMO = AMO | CacheRW[0]; + assign AnyMiss = (StoreAMO | CacheRW[1]) & ~CacheHit & ~InvalidateCache; + assign AnyUpdateHit = StoreAMO & CacheHit; + assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit); + assign CacheAccess = (AMO | CacheRW[1] | CacheRW[0]) & CurrState == STATE_READY; // for performance counter + end + else begin + assign AnyMiss = CacheRW[1] & ~CacheHit & ~InvalidateCache; + assign AnyUpdateHit = 0; // todo clear all RO cache of usage of this logic + assign AnyHit = CacheRW[1] & CacheHit; + assign CacheAccess = CacheRW[1] & CurrState == STATE_READY; // for performance counter + end - assign AnyMiss = (StoreAMO | CacheRW[1]) & ~CacheHit & ~InvalidateCache; - assign AnyUpdateHit = (StoreAMO) & CacheHit; - assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit); + assign CacheMiss = CacheAccess & ~CacheHit; // for performance counter assign FlushFlag = FlushAdrFlag & FlushWayFlag; - // outputs for the performance counters. - assign CacheAccess = (AMO | CacheRW[1] | CacheRW[0]) & CurrState == STATE_READY; - assign CacheMiss = CacheAccess & ~CacheHit; - // special case on reset. When the fsm first exists reset the // PCNextF will no longer be pointing to the correct address. // But PCF will be the reset vector. @@ -106,77 +113,119 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( always_ff @(posedge clk) if (reset | FlushStage) CurrState <= #1 STATE_READY; else CurrState <= #1 NextState; - - always_comb begin - NextState = STATE_READY; - case (CurrState) - STATE_READY: if(InvalidateCache) NextState = STATE_READY; - else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH; - else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH; - else if(AnyMiss & LineDirty) NextState = STATE_WRITEBACK; - else NextState = STATE_READY; - STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE; - else NextState = STATE_FETCH; - STATE_WRITE_LINE: NextState = STATE_READ_HOLD; - STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD; - else NextState = STATE_READY; - STATE_WRITEBACK: if(CacheBusAck) NextState = STATE_FETCH; - else NextState = STATE_WRITEBACK; - // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack. - STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK; - else if (FlushFlag) NextState = STATE_READ_HOLD; - else NextState = STATE_FLUSH; - STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH; - else if(CacheBusAck) NextState = STATE_READ_HOLD; - else NextState = STATE_FLUSH_WRITEBACK; - default: NextState = STATE_READY; - endcase - end + + // seperating NextState logic by ro vs rw cache results in code duplication but this is needed to hit coverage. + if (!READ_ONLY_CACHE) + always_comb begin + NextState = STATE_READY; + case (CurrState) + STATE_READY: if(InvalidateCache) NextState = STATE_READY; + else if(FlushCache) NextState = STATE_FLUSH; + else if(AnyMiss & ~LineDirty) NextState = STATE_FETCH; + else if(AnyMiss & LineDirty) NextState = STATE_WRITEBACK; + else NextState = STATE_READY; + STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE; + else NextState = STATE_FETCH; + STATE_WRITE_LINE: NextState = STATE_READ_HOLD; + STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD; + else NextState = STATE_READY; + STATE_WRITEBACK: if(CacheBusAck) NextState = STATE_FETCH; + else NextState = STATE_WRITEBACK; + // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same + // time as getting back the bus ack. + STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK; + else if (FlushFlag) NextState = STATE_READ_HOLD; + else NextState = STATE_FLUSH; + STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH; + else if(CacheBusAck) NextState = STATE_READ_HOLD; + else NextState = STATE_FLUSH_WRITEBACK; + default: NextState = STATE_READY; + endcase + end // always_comb + else // READ_ONLY_CACHE + always_comb begin + NextState = STATE_READY; + case (CurrState) + STATE_READY: if(InvalidateCache) NextState = STATE_READY; + else if(AnyMiss) NextState = STATE_FETCH; + else NextState = STATE_READY; + STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE; + else NextState = STATE_FETCH; + STATE_WRITE_LINE: NextState = STATE_READ_HOLD; + STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD; + else NextState = STATE_READY; + default: NextState = STATE_READY; + endcase // case (CurrState) + end // always_comb // com back to CPU - assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & CurrState == STATE_READ_HOLD); - assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) | - (CurrState == STATE_FETCH) | - (CurrState == STATE_WRITEBACK) | - (CurrState == STATE_WRITE_LINE) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write. - (CurrState == STATE_FLUSH) | + if (!READ_ONLY_CACHE) begin + assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) | + (CurrState == STATE_FETCH) | + (CurrState == STATE_WRITEBACK) | + (CurrState == STATE_WRITE_LINE) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write. + (CurrState == STATE_FLUSH) | + (CurrState == STATE_FLUSH_WRITEBACK); + assign CacheCommitted = CurrState != STATE_READY; + assign SelAdr = (CurrState == STATE_READY & (StoreAMO | AnyMiss)) | // changes if store delay hazard removed + (CurrState == STATE_FETCH) | + (CurrState == STATE_WRITEBACK) | + (CurrState == STATE_WRITE_LINE) | + resetDelay; + assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) | + (CurrState == STATE_WRITE_LINE & (StoreAMO)); + assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(StoreAMO)) | + (CurrState == STATE_FLUSH & LineDirty); // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set. + + // Flush and eviction controls + assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) | + (CurrState == STATE_READY & AnyMiss & LineDirty); + + assign SelFlush = (CurrState == STATE_READY & FlushCache) | + (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_WRITEBACK); + assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITEBACK & FlushWayFlag & CacheBusAck) | + (CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty); + assign FlushWayCntEn = (CurrState == STATE_FLUSH & ~LineDirty) | + (CurrState == STATE_FLUSH_WRITEBACK & CacheBusAck); + assign FlushCntRst = (CurrState == STATE_FLUSH & FlushFlag & ~LineDirty) | + (CurrState == STATE_FLUSH_WRITEBACK & FlushFlag & CacheBusAck); + // Bus interface controls + assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) | + (CurrState == STATE_FETCH & ~CacheBusAck) | + (CurrState == STATE_WRITEBACK & CacheBusAck); + assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) | + (CurrState == STATE_WRITEBACK & ~CacheBusAck) | + (CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck); + // write enable internal to cache + assign CacheEn = (~Stall | FlushCache | AnyMiss) | (CurrState != STATE_READY) | reset | InvalidateCache; + end + else begin + assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) | + (CurrState == STATE_FETCH) | + (CurrState == STATE_WRITE_LINE); // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write. + assign CacheCommitted = (CurrState != STATE_READY) & ~(CurrState == STATE_READ_HOLD); + assign SelAdr = (CurrState == STATE_READY & AnyMiss) | // changes if store delay hazard removed + (CurrState == STATE_FETCH) | + (CurrState == STATE_WRITE_LINE) | + resetDelay; + assign SetDirty = 0; + assign ClearDirty = 0; + assign SelWriteback = 0; + assign SelFlush = 0; + assign FlushAdrCntEn = 0; + assign FlushWayCntEn = 0; + assign FlushCntRst = 0; + assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss) | + (CurrState == STATE_FETCH & ~CacheBusAck); + assign CacheBusRW[0] = 0; + assign CacheEn = (~Stall | AnyMiss) | (CurrState != STATE_READY) | reset | InvalidateCache; + end // else: (READ_ONLY_CACHE) + // write enables internal to cache assign SetValid = CurrState == STATE_WRITE_LINE; - assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) | - (CurrState == STATE_WRITE_LINE & (StoreAMO)); - assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(StoreAMO)) | - (CurrState == STATE_FLUSH & LineDirty); // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set. assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) | (CurrState == STATE_WRITE_LINE); - // Flush and eviction controls - assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) | - (CurrState == STATE_READY & AnyMiss & LineDirty); - - assign SelFlush = (CurrState == STATE_READY & FlushCache) | - (CurrState == STATE_FLUSH) | - (CurrState == STATE_FLUSH_WRITEBACK); - assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITEBACK & FlushWayFlag & CacheBusAck) | - (CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty); - assign FlushWayCntEn = (CurrState == STATE_FLUSH & ~LineDirty) | - (CurrState == STATE_FLUSH_WRITEBACK & CacheBusAck); - assign FlushCntRst = (CurrState == STATE_FLUSH & FlushFlag & ~LineDirty) | - (CurrState == STATE_FLUSH_WRITEBACK & FlushFlag & CacheBusAck); - // Bus interface controls - assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) | - (CurrState == STATE_FETCH & ~CacheBusAck) | - (CurrState == STATE_WRITEBACK & CacheBusAck); - assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) | - (CurrState == STATE_WRITEBACK & ~CacheBusAck) | - (CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck); - - assign SelAdr = (CurrState == STATE_READY & (StoreAMO | AnyMiss)) | // changes if store delay hazard removed - (CurrState == STATE_FETCH) | - (CurrState == STATE_WRITEBACK) | - (CurrState == STATE_WRITE_LINE) | - resetDelay; - assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD; - assign CacheEn = (~Stall | FlushCache | AnyMiss) | (CurrState != STATE_READY) | reset | InvalidateCache; endmodule // cachefsm From d60e3aaf5314acdfdaba6c61c6c00f15c4647c9c Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Wed, 12 Apr 2023 00:53:22 -0700 Subject: [PATCH 09/40] only assign ClearDirtyWay for read-write caches --- src/cache/cacheway.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 568e626e5..106905939 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -97,9 +97,9 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, ///////////////////////////////////////////////////////////////////////////////////////////// assign SetValidWay = SetValid & SelData; - assign ClearDirtyWay = ClearDirty & SelData; if (!READ_ONLY_CACHE) begin assign SetDirtyWay = SetDirty & SelData; + assign ClearDirtyWay = ClearDirty & SelData; assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage; assign SetValidEN = SetValidWay & ~FlushStage; end From 800f0245f3514e2e0a8c747ff94951ae6d535e52 Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Wed, 12 Apr 2023 13:32:36 -0700 Subject: [PATCH 10/40] Cachefsm gate LRUWriteEn with ~FlushStage --- src/cache/cache.sv | 2 +- src/cache/cachefsm.sv | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 2d90e98e8..ea7504f23 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -129,7 +129,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE // Select victim way for associative caches if(NUMWAYS > 1) begin:vict cacheLRU #(NUMWAYS, SETLEN, OFFSETLEN, NUMLINES) cacheLRU( - .clk, .reset, .CacheEn, .FlushStage, .HitWay, .ValidWay, .VictimWay, .CacheSet, .LRUWriteEn, + .clk, .reset, .CacheEn, .HitWay, .ValidWay, .VictimWay, .CacheSet, .LRUWriteEn, .SetValid, .PAdr(PAdr[SETTOP-1:OFFSETLEN]), .InvalidateCache, .FlushCache); end else assign VictimWay = 1'b1; // one hot. diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index a42176325..c5e261f27 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -224,8 +224,9 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( // write enables internal to cache assign SetValid = CurrState == STATE_WRITE_LINE; + // coverage off -item e 1 -fecexprrow 8 assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) | - (CurrState == STATE_WRITE_LINE); + (CurrState == STATE_WRITE_LINE) & ~FlushStage; assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD; endmodule // cachefsm From a3d9e11b0fd9109bec2fc57567490b620bc16253 Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Wed, 12 Apr 2023 15:57:45 -0700 Subject: [PATCH 11/40] cachefsm exclude icache logic without code reuse --- sim/coverage-exclusions-rv64gc.do | 34 ++++- src/cache/cachefsm.sv | 198 ++++++++++++------------------ 2 files changed, 105 insertions(+), 127 deletions(-) diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index 3e880b502..eb10505eb 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -27,17 +27,41 @@ # This file should be a last resort. It's preferable to put # // coverage off # statements inline with the code whenever possible. +# a hack to describe coverage exclusions without hardcoding linenumbers: +do GetLineNum.do # LZA (i<64) statement confuses coverage tool # This is ugly to exlcude the whole file - is there a better option? // coverage off isn't working coverage exclude -srcfile lzc.sv -# Exclude D$ states from coverage in the I$ instance of cachefsm. -# This is cleaner than trying to set an I$-specific pragma in cachefsm.sv -# Also exclude the write line to ready transition for the I$ since we can't get a flush -# during this operation. -coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -fstate CurrState STATE_FLUSH STATE_FLUSH_WRITEBACK STATE_FLUSH_WRITEBACK +### Exclude D$ states and logic for the I$ instance +# This is cleaner than trying to set an I$-specific pragma in cachefsm.sv (which would exclude it for the D$ instance too) +# Also exclude the write line to ready transition for the I$ since we can't get a flush during this operation. +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -fstate CurrState STATE_FLUSH STATE_FLUSH_WRITEBACK STATE_FLUSH_WRITEBACK STATE_WRITEBACK coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -ftrans CurrState STATE_WRITE_LINE->STATE_READY +# exclude unused transitions from case statement. Unfortunately the whole branch needs to be excluded I think. Expression coverage should still work. +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache state-case"] -item b 1 +# exclude branch/condition coverage: LineDirty if statement +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache FETCHStatement"] -item bc 1 +# exclude the unreachable logic +set start [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-start: icache case"] +set end [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-end: icache case"] +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange $start-$end +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache WRITEBACKStatement"] +# exclude Atomic Operation logic +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache storeAMO"] -item e 1 -fecexprrow 6 +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache storeAMO1"] -item e 1 -fecexprrow 2-4 +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache AnyUpdateHit"] -item e 1 -fecexprrow 2 +# cache write logic +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheW"] -item e 1 -fecexprrow 4 +# output signal logic +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache StallStates"] -item e 1 -fecexprrow 8 12 14 +set start [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-start: icache flushdirtycontrols"] +set end [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag-end: icache flushdirtycontrols"] +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange $start-$end +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheBusW"] +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache SelAdrCauses"] -item e 1 -fecexprrow 4 10 +coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheBusRCauses"] -item e 1 -fecexprrow 1-2 12 ###################### # Toggle exclusions diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index c5e261f27..fc31aec4b 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -86,25 +86,18 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( statetype CurrState, NextState; - // no atomic operations on i$ - if (!READ_ONLY_CACHE) begin - assign AMO = CacheAtomic[1] & (&CacheRW); - assign StoreAMO = AMO | CacheRW[0]; - assign AnyMiss = (StoreAMO | CacheRW[1]) & ~CacheHit & ~InvalidateCache; - assign AnyUpdateHit = StoreAMO & CacheHit; - assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit); - assign CacheAccess = (AMO | CacheRW[1] | CacheRW[0]) & CurrState == STATE_READY; // for performance counter - end - else begin - assign AnyMiss = CacheRW[1] & ~CacheHit & ~InvalidateCache; - assign AnyUpdateHit = 0; // todo clear all RO cache of usage of this logic - assign AnyHit = CacheRW[1] & CacheHit; - assign CacheAccess = CacheRW[1] & CurrState == STATE_READY; // for performance counter - end + assign AMO = CacheAtomic[1] & (&CacheRW); + assign StoreAMO = AMO | CacheRW[0]; - assign CacheMiss = CacheAccess & ~CacheHit; // for performance counter + assign AnyMiss = (StoreAMO | CacheRW[1]) & ~CacheHit & ~InvalidateCache; // exclusion-tag: icache storeAMO + assign AnyUpdateHit = (StoreAMO) & CacheHit; // exclusion-tag: icache storeAMO1 + assign AnyHit = AnyUpdateHit | (CacheRW[1] & CacheHit); // exclusion-tag: icache AnyUpdateHit assign FlushFlag = FlushAdrFlag & FlushWayFlag; + // outputs for the performance counters. + assign CacheAccess = (AMO | CacheRW[1] | CacheRW[0]) & CurrState == STATE_READY; // exclusion-tag: icache CacheW + assign CacheMiss = CacheAccess & ~CacheHit; + // special case on reset. When the fsm first exists reset the // PCNextF will no longer be pointing to the correct address. // But PCF will be the reset vector. @@ -113,120 +106,81 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( always_ff @(posedge clk) if (reset | FlushStage) CurrState <= #1 STATE_READY; else CurrState <= #1 NextState; - - // seperating NextState logic by ro vs rw cache results in code duplication but this is needed to hit coverage. - if (!READ_ONLY_CACHE) - always_comb begin - NextState = STATE_READY; - case (CurrState) - STATE_READY: if(InvalidateCache) NextState = STATE_READY; - else if(FlushCache) NextState = STATE_FLUSH; - else if(AnyMiss & ~LineDirty) NextState = STATE_FETCH; - else if(AnyMiss & LineDirty) NextState = STATE_WRITEBACK; - else NextState = STATE_READY; - STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE; - else NextState = STATE_FETCH; - STATE_WRITE_LINE: NextState = STATE_READ_HOLD; - STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD; - else NextState = STATE_READY; - STATE_WRITEBACK: if(CacheBusAck) NextState = STATE_FETCH; - else NextState = STATE_WRITEBACK; - // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same - // time as getting back the bus ack. - STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK; - else if (FlushFlag) NextState = STATE_READ_HOLD; - else NextState = STATE_FLUSH; - STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH; - else if(CacheBusAck) NextState = STATE_READ_HOLD; - else NextState = STATE_FLUSH_WRITEBACK; - default: NextState = STATE_READY; - endcase - end // always_comb - else // READ_ONLY_CACHE - always_comb begin - NextState = STATE_READY; - case (CurrState) - STATE_READY: if(InvalidateCache) NextState = STATE_READY; - else if(AnyMiss) NextState = STATE_FETCH; - else NextState = STATE_READY; - STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE; - else NextState = STATE_FETCH; - STATE_WRITE_LINE: NextState = STATE_READ_HOLD; - STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD; - else NextState = STATE_READY; - default: NextState = STATE_READY; - endcase // case (CurrState) - end // always_comb + + always_comb begin + NextState = STATE_READY; + case (CurrState) // exclusion-tag: icache state-case + STATE_READY: if(InvalidateCache) NextState = STATE_READY; + else if(FlushCache & ~READ_ONLY_CACHE) NextState = STATE_FLUSH; + else if(AnyMiss & (READ_ONLY_CACHE | ~LineDirty)) NextState = STATE_FETCH; // exclusion-tag: icache FETCHStatement + else if(AnyMiss & LineDirty) NextState = STATE_WRITEBACK; // exclusion-tag: icache WRITEBACKStatement + else NextState = STATE_READY; + STATE_FETCH: if(CacheBusAck) NextState = STATE_WRITE_LINE; + else NextState = STATE_FETCH; + STATE_WRITE_LINE: NextState = STATE_READ_HOLD; + STATE_READ_HOLD: if(Stall) NextState = STATE_READ_HOLD; + else NextState = STATE_READY; + // exclusion-tag-start: icache case + STATE_WRITEBACK: if(CacheBusAck) NextState = STATE_FETCH; + else NextState = STATE_WRITEBACK; + // eviction needs a delay as the bus fsm does not correctly handle sending the write command at the same time as getting back the bus ack. + STATE_FLUSH: if(LineDirty) NextState = STATE_FLUSH_WRITEBACK; + else if (FlushFlag) NextState = STATE_READ_HOLD; + else NextState = STATE_FLUSH; + STATE_FLUSH_WRITEBACK: if(CacheBusAck & ~FlushFlag) NextState = STATE_FLUSH; + else if(CacheBusAck) NextState = STATE_READ_HOLD; + else NextState = STATE_FLUSH_WRITEBACK; + // exclusion-tag-end: icache case + default: NextState = STATE_READY; + endcase + end // com back to CPU - if (!READ_ONLY_CACHE) begin - assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) | - (CurrState == STATE_FETCH) | - (CurrState == STATE_WRITEBACK) | - (CurrState == STATE_WRITE_LINE) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write. - (CurrState == STATE_FLUSH) | - (CurrState == STATE_FLUSH_WRITEBACK); - assign CacheCommitted = CurrState != STATE_READY; - assign SelAdr = (CurrState == STATE_READY & (StoreAMO | AnyMiss)) | // changes if store delay hazard removed - (CurrState == STATE_FETCH) | - (CurrState == STATE_WRITEBACK) | - (CurrState == STATE_WRITE_LINE) | - resetDelay; - assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) | - (CurrState == STATE_WRITE_LINE & (StoreAMO)); - assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(StoreAMO)) | - (CurrState == STATE_FLUSH & LineDirty); // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set. - - // Flush and eviction controls - assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) | - (CurrState == STATE_READY & AnyMiss & LineDirty); - - assign SelFlush = (CurrState == STATE_READY & FlushCache) | - (CurrState == STATE_FLUSH) | + assign CacheCommitted = (CurrState != STATE_READY) & ~(READ_ONLY_CACHE & CurrState == STATE_READ_HOLD); + assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) | // exclusion-tag: icache StallStates + (CurrState == STATE_FETCH) | + (CurrState == STATE_WRITEBACK) | + (CurrState == STATE_WRITE_LINE) | // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write. + (CurrState == STATE_FLUSH) | (CurrState == STATE_FLUSH_WRITEBACK); - assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITEBACK & FlushWayFlag & CacheBusAck) | - (CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty); - assign FlushWayCntEn = (CurrState == STATE_FLUSH & ~LineDirty) | - (CurrState == STATE_FLUSH_WRITEBACK & CacheBusAck); - assign FlushCntRst = (CurrState == STATE_FLUSH & FlushFlag & ~LineDirty) | - (CurrState == STATE_FLUSH_WRITEBACK & FlushFlag & CacheBusAck); - // Bus interface controls - assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) | - (CurrState == STATE_FETCH & ~CacheBusAck) | - (CurrState == STATE_WRITEBACK & CacheBusAck); - assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) | - (CurrState == STATE_WRITEBACK & ~CacheBusAck) | - (CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck); - // write enable internal to cache - assign CacheEn = (~Stall | FlushCache | AnyMiss) | (CurrState != STATE_READY) | reset | InvalidateCache; - end - else begin - assign CacheStall = (CurrState == STATE_READY & (FlushCache | AnyMiss)) | - (CurrState == STATE_FETCH) | - (CurrState == STATE_WRITE_LINE); // this cycle writes the sram, must keep stalling so the next cycle can read the next hit/miss unless its a write. - assign CacheCommitted = (CurrState != STATE_READY) & ~(CurrState == STATE_READ_HOLD); - assign SelAdr = (CurrState == STATE_READY & AnyMiss) | // changes if store delay hazard removed - (CurrState == STATE_FETCH) | - (CurrState == STATE_WRITE_LINE) | - resetDelay; - assign SetDirty = 0; - assign ClearDirty = 0; - assign SelWriteback = 0; - assign SelFlush = 0; - assign FlushAdrCntEn = 0; - assign FlushWayCntEn = 0; - assign FlushCntRst = 0; - assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss) | - (CurrState == STATE_FETCH & ~CacheBusAck); - assign CacheBusRW[0] = 0; - assign CacheEn = (~Stall | AnyMiss) | (CurrState != STATE_READY) | reset | InvalidateCache; - end // else: (READ_ONLY_CACHE) - // write enables internal to cache assign SetValid = CurrState == STATE_WRITE_LINE; // coverage off -item e 1 -fecexprrow 8 assign LRUWriteEn = (CurrState == STATE_READY & AnyHit) | (CurrState == STATE_WRITE_LINE) & ~FlushStage; + // exclusion-tag-start: icache flushdirtycontrols + assign SetDirty = (CurrState == STATE_READY & AnyUpdateHit) | // exclusion-tag: icache SetDirty + (CurrState == STATE_WRITE_LINE & (StoreAMO)); + assign ClearDirty = (CurrState == STATE_WRITE_LINE & ~(StoreAMO)) | // exclusion-tag: icache ClearDirty + (CurrState == STATE_FLUSH & LineDirty); // This is wrong in a multicore snoop cache protocal. Dirty must be cleared concurrently and atomically with writeback. For single core cannot clear after writeback on bus ack and change flushadr. Clears the wrong set. + // Flush and eviction controls + assign SelWriteback = (CurrState == STATE_WRITEBACK & ~CacheBusAck) | + (CurrState == STATE_READY & AnyMiss & LineDirty); + + assign SelFlush = (CurrState == STATE_READY & FlushCache) | + (CurrState == STATE_FLUSH) | + (CurrState == STATE_FLUSH_WRITEBACK); + assign FlushAdrCntEn = (CurrState == STATE_FLUSH_WRITEBACK & FlushWayFlag & CacheBusAck) | + (CurrState == STATE_FLUSH & FlushWayFlag & ~LineDirty); + assign FlushWayCntEn = (CurrState == STATE_FLUSH & ~LineDirty) | + (CurrState == STATE_FLUSH_WRITEBACK & CacheBusAck); + assign FlushCntRst = (CurrState == STATE_FLUSH & FlushFlag & ~LineDirty) | + (CurrState == STATE_FLUSH_WRITEBACK & FlushFlag & CacheBusAck); + // exclusion-tag-end: icache flushdirtycontrols + // Bus interface controls + assign CacheBusRW[1] = (CurrState == STATE_READY & AnyMiss & ~LineDirty) | // exclusion-tag: icache CacheBusRCauses + (CurrState == STATE_FETCH & ~CacheBusAck) | + (CurrState == STATE_WRITEBACK & CacheBusAck); + assign CacheBusRW[0] = (CurrState == STATE_READY & AnyMiss & LineDirty) | // exclusion-tag: icache CacheBusW + (CurrState == STATE_WRITEBACK & ~CacheBusAck) | + (CurrState == STATE_FLUSH_WRITEBACK & ~CacheBusAck); + + assign SelAdr = (CurrState == STATE_READY & (StoreAMO | AnyMiss)) | // exclusion-tag: icache SelAdrCauses // changes if store delay hazard removed + (CurrState == STATE_FETCH) | + (CurrState == STATE_WRITEBACK) | + (CurrState == STATE_WRITE_LINE) | + resetDelay; assign SelFetchBuffer = CurrState == STATE_WRITE_LINE | CurrState == STATE_READ_HOLD; + assign CacheEn = (~Stall | FlushCache | AnyMiss) | (CurrState != STATE_READY) | reset | InvalidateCache; endmodule // cachefsm From 92cd0cb6ab2467bfea758db2891005fb48e05c7d Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Wed, 12 Apr 2023 15:58:38 -0700 Subject: [PATCH 12/40] track GetLinenum.do (tcl procedure to find line numbers to exclude) --- sim/GetLineNum.do | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) create mode 100644 sim/GetLineNum.do diff --git a/sim/GetLineNum.do b/sim/GetLineNum.do new file mode 100644 index 000000000..4d38d9121 --- /dev/null +++ b/sim/GetLineNum.do @@ -0,0 +1,18 @@ +# Alec Vercruysse +# 2023-04-12 +# Note that the target string is regex, and needs to be double-escaped. +# e.g. to match a (, you need \\(. +proc GetLineNum {fname target} { + set f [open $fname] + set linectr 1 + while {[gets $f line] != -1} { + if {[regexp $target $line]} { + close $f + return $linectr + } + incr linectr + } + close $f + return -code error \ + "target string not found" +} From f8a8c433076f941df0b39ffae80ab980e88f3aba Mon Sep 17 00:00:00 2001 From: Alexa Wright Date: Thu, 13 Apr 2023 09:23:32 -0700 Subject: [PATCH 13/40] Fixed exception handling to handle ecalls properly --- tests/coverage/WALLY-init-lib.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tests/coverage/WALLY-init-lib.h b/tests/coverage/WALLY-init-lib.h index 1dd43accf..6b6dd6dd9 100644 --- a/tests/coverage/WALLY-init-lib.h +++ b/tests/coverage/WALLY-init-lib.h @@ -66,8 +66,7 @@ interrupt: # must be a timer interrupt j trap_return # clean up and return exception: - li t0, 2 - csrr t1, mcause + csrr t0, mcause li t1, 8 # is it an ecall trap? andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11 bne t0, t1, trap_return # ignore other exceptions From 3d5c128470cb2644e66094151859d5a0cc051ff1 Mon Sep 17 00:00:00 2001 From: Dygore Date: Thu, 13 Apr 2023 16:39:27 -0500 Subject: [PATCH 14/40] Added a test for denormalized FP numbers --- tests/coverage/fpu.S | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index 02b3f4a49..9c8f3d344 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -31,6 +31,11 @@ main: #bseti t0, zero, 14 # turn on FPU csrs mstatus, t0 + #Pull denormalized FP number from memory and pass it to fclass.S for coverage + la t0, TestData + flw ft0, 0(t0) + fclass.s t1, ft0 + # Test legal instructions not covered elsewhere flq ft0, 0(a0) flh ft0, 8(a0) @@ -98,3 +103,7 @@ main: j done +.section .data +.align 3 +TestData: +.int 0x00100000 #Denormalized FP number \ No newline at end of file From 98420e45acf188654311d3f4fe9ad97217742ac8 Mon Sep 17 00:00:00 2001 From: Noah Limpert Date: Thu, 13 Apr 2023 15:13:55 -0700 Subject: [PATCH 15/40] update tests.vh, add tlbKP to load all lines of tlb --- tests/coverage/tlbKP.S | 143 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 143 insertions(+) create mode 100644 tests/coverage/tlbKP.S diff --git a/tests/coverage/tlbKP.S b/tests/coverage/tlbKP.S new file mode 100644 index 000000000..5aaf5c195 --- /dev/null +++ b/tests/coverage/tlbKP.S @@ -0,0 +1,143 @@ +/////////////////////////////////////////// +// lsu_test.S +// +// Written: mmendozamanriquez@hmc.edu 4 April 2023 +// nlimpert@hmc.edu +// +// Purpose: Test coverage for LSU +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate + +#include "WALLY-init-lib.h" + +# run-elf.bash find this in project description +main: + # Page table root address at 0x80010000 + li t5, 0x9000000000080010 + csrw satp, t5 + + # sfence.vma x0, x0 + + # switch to supervisor mode + li a0, 1 + ecall + + li t0, 0x80015000 + + li t2, 0 # i = 0 + li t3, 33 # Max amount of Loops = 32 + +loop: bge t2, t3, finished # exit loop if i >= loops + lw t1, 0(t0) + li t4, 0x1000 + add t0, t0, t4 + addi t2, t2, 1 + j loop + +finished: + j done + +.data + +.align 16 +# Page table situated at 0x80010000 +pagetable: + .8byte 0x200044C1 // old page table was 200040 which just pointed to itself! wrong + +.align 12 + .8byte 0x0000000000000000 + .8byte 0x00000000200048C1 + .8byte 0x00000000200048C1 + + +.align 12 + .8byte 0x0000000020004CC1 + //.8byte 0x00000200800CF// ADD IN THE MEGAPAGE should 3 nibbles of zeros be removed? + +.align 12 + #80000000 + .8byte 0x200000CF + .8byte 0x200004CF + .8byte 0x200008CF + .8byte 0x20000CCF + + .8byte 0x200010CF + .8byte 0x200014CF + .8byte 0x200018CF + .8byte 0x20001CCF + + .8byte 0x200020CF + .8byte 0x200024CF + .8byte 0x200028CF + .8byte 0x20002CCF + + .8byte 0x200030CF + .8byte 0x200034CF + .8byte 0x200038CF + .8byte 0x20003CCF + + .8byte 0x200040CF + .8byte 0x200044CF + .8byte 0x200048CF + .8byte 0x20004CCF + + .8byte 0x200050CF + .8byte 0x200054CF + .8byte 0x200058CF + .8byte 0x20005CCF + + .8byte 0x200060CF + .8byte 0x200064CF + .8byte 0x200068CF + .8byte 0x20006CCF + + .8byte 0x200070CF + .8byte 0x200074CF + .8byte 0x200078CF + .8byte 0x20007CCF + + .8byte 0x200080CF + .8byte 0x200084CF + .8byte 0x200088CF + .8byte 0x20008CCF + + .8byte 0x200090CF + .8byte 0x200094CF + .8byte 0x200098CF + .8byte 0x20009CCF + + .8byte 0x200100CF + .8byte 0x200104CF + .8byte 0x200108CF + .8byte 0x20010CCF + + .8byte 0x200110CF + .8byte 0x200114CF + .8byte 0x200118CF + .8byte 0x20011CCF + + .8byte 0x200120CF + .8byte 0x200124CF + .8byte 0x200128CF + .8byte 0x20012CCF + + .8byte 0x200130CF + .8byte 0x200134CF From 8db317133cdb5311ac8ec222d379f821e05e05e4 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 13 Apr 2023 16:53:33 -0700 Subject: [PATCH 16/40] Starting fdivsqrt cleanup --- src/fpu/fdivsqrt/fdivsqrtfsm.sv | 4 +++- src/fpu/fdivsqrt/fdivsqrtpreproc.sv | 12 +++++++----- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 4cfede605..5e84ab03f 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -71,6 +71,7 @@ module fdivsqrtfsm( // NS = NF + 1 // N = NS or NS+2 for div/sqrt. +// *** CT 4/13/23 move cycles calculation back to preprocesor /* verilator lint_off WIDTH */ logic [`DURLEN+1:0] Nf, fbits; // number of fractional bits if (`FPSIZES == 1) @@ -110,7 +111,8 @@ module fdivsqrtfsm( always_ff @(posedge clk) begin if (reset | FlushE) begin state <= #1 IDLE; - end else if ((state == IDLE) & IFDivStartE) begin + end else if (IFDivStartE) begin // IFDivStartE implies stat is IDLE +// end else if ((state == IDLE) & IFDivStartE) begin // IFDivStartE implies stat is IDLE step <= cycles; if (SpecialCaseE) state <= #1 DONE; else state <= #1 BUSY; diff --git a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv index a00d82663..cf8a055ef 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpreproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpreproc.sv @@ -101,17 +101,19 @@ module fdivsqrtpreproc ( lzc #(`DIVb) lzcX (IFX, ell); lzc #(`DIVb) lzcY (IFD, mE); - // Normalization shift - assign XPreproc = IFX << (ell + {{`DIVBLEN{1'b0}}, 1'b1}); // *** try to remove this +1 - assign DPreproc = IFD << (mE + {{`DIVBLEN{1'b0}}, 1'b1}); + // Normalization shift: shift off leading one + assign XPreproc = (IFX << ell) << 1; + assign DPreproc = (IFD << mE) << 1; - // append leading 1 (for normal inputs) + // append leading 1 (for nonzero inputs) // shift square root to be in range [1/4, 1) // Normalized numbers are shifted right by 1 if the exponent is odd // Denormalized numbers have Xe = 0 and an unbiased exponent of 1-BIAS. They are shifted right if the number of leading zeros is odd. mux2 #(`DIVb+1) sqrtxmux({~XZeroE, XPreproc}, {1'b0, ~XZeroE, XPreproc[`DIVb-1:1]}, (Xe[0] ^ ell[0]), PreSqrtX); assign DivX = {3'b000, ~NumerZeroE, XPreproc}; + // *** CT 4/13/23 Create D output here with leading 1 appended as well, use in the other modules + // ***CT: factor out fdivsqrtcycles if (`IDIV_ON_FPU) begin:intrightshift // Int Supported logic [`DIVBLEN:0] ZeroDiff, p; logic ALTBE; @@ -119,7 +121,7 @@ module fdivsqrtpreproc ( // calculate number of fractional bits p assign ZeroDiff = mE - ell; // Difference in number of leading zeros assign ALTBE = ZeroDiff[`DIVBLEN]; // A less than B (A has more leading zeros) - mux2 #(`DIVBLEN+1) pmux(ZeroDiff, {(`DIVBLEN+1){1'b0}}, ALTBE, p); // *** is there a more graceful way to write these constants + mux2 #(`DIVBLEN+1) pmux(ZeroDiff, '0, ALTBE, p); // Integer special cases (terminate immediately) assign ISpecialCaseE = BZeroE | ALTBE; From ecce9b0ce177402ef7000a222718aba0f7db36b3 Mon Sep 17 00:00:00 2001 From: Limnanthes Serafini Date: Thu, 13 Apr 2023 16:53:36 -0700 Subject: [PATCH 17/40] Fix of InvalDelayed warning --- testbench/testbench.sv | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 417956ed4..386dc8d8b 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -49,8 +49,8 @@ module testbench; string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName; logic [31:0] InstrW; -string tests[]; -logic [3:0] dummy; + string tests[]; + logic [3:0] dummy; logic [`AHBW-1:0] HRDATAEXT; logic HREADYEXT, HRESPEXT; @@ -559,11 +559,8 @@ end int file; string LogFile; logic resetD, resetEdge; - logic Enable; - // assign Enable = ~dut.core.StallD & ~dut.core.FlushD & dut.core.ifu.bus.icache.CacheRWF[1] & ~reset; + logic Enable, InvalDelayed; - // this version of Enable allows for accurate eviction logging. - // Likely needs further improvement. assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn & dut.core.ifu.immu.immu.pmachecker.Cacheable & ~dut.core.ifu.bus.icache.icache.cachefsm.FlushStage & @@ -596,13 +593,13 @@ end if (`DCACHE_SUPPORTED && `D_CACHE_ADDR_LOGGER) begin : DCacheLogger int file; - string LogFile; - logic resetD, resetEdge; + string LogFile; + logic resetD, resetEdge; logic Enabled; string AccessTypeString, HitMissString; - flop #(1) ResetDReg(clk, reset, resetD); - assign resetEdge = ~reset & resetD; + flop #(1) ResetDReg(clk, reset, resetD); + assign resetEdge = ~reset & resetD; assign HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" : (!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" : dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E"; @@ -611,12 +608,7 @@ end dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" : dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" : "NULL"; - // assign Enabled = (dut.core.lsu.bus.dcache.dcache.cachefsm.CurrState == 0) & - // ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage & - // (AccessTypeString != "NULL"); - - // This version of enable allows for accurate eviction logging. - // Likely needs further improvement. + assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn & ~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage & dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable & From c427b4c89636b2fae9e3dd142ce8348616360632 Mon Sep 17 00:00:00 2001 From: Limnanthes Serafini Date: Thu, 13 Apr 2023 16:54:15 -0700 Subject: [PATCH 18/40] Misc typo and indent fixing. --- bin/CacheSim.py | 2 +- sim/rv64gc_CacheSim.py | 2 +- src/cache/cachefsm.sv | 4 ++-- src/cache/cacheway.sv | 6 +++--- src/fpu/fcmp.sv | 22 +++++++++++----------- src/fpu/fsgninj.sv | 2 +- src/ieu/bmu/popcnt.sv | 2 +- src/ieu/controller.sv | 2 +- src/ieu/datapath.sv | 3 ++- src/ieu/regfile.sv | 2 +- src/ieu/shifter.sv | 2 +- src/ifu/decompress.sv | 2 +- src/ifu/ifu.sv | 6 +++--- src/mdu/mdu.sv | 4 ++-- src/mmu/mmu.sv | 16 ++++++++-------- src/privileged/csrsr.sv | 2 +- 16 files changed, 40 insertions(+), 39 deletions(-) diff --git a/bin/CacheSim.py b/bin/CacheSim.py index 7fd36b054..24857837b 100755 --- a/bin/CacheSim.py +++ b/bin/CacheSim.py @@ -5,7 +5,7 @@ ## ## Written: lserafini@hmc.edu ## Created: 27 March 2023 -## Modified: 5 April 2023 +## Modified: 12 April 2023 ## ## Purpose: Simulate a L1 D$ or I$ for comparison with Wally ## diff --git a/sim/rv64gc_CacheSim.py b/sim/rv64gc_CacheSim.py index 299281d5f..56a76c9ac 100755 --- a/sim/rv64gc_CacheSim.py +++ b/sim/rv64gc_CacheSim.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 ########################################### -## CacheSimTest.py +## rv64gc_CacheSim.py ## ## Written: lserafini@hmc.edu ## Created: 11 April 2023 diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index d1d54097e..2a5cb8235 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -47,7 +47,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( output logic [1:0] CacheBusRW, // [1] Read (cache line fetch) or [0] write bus (cache line writeback) // performance counter outputs output logic CacheMiss, // Cache miss - output logic CacheAccess, // Cache access + output logic CacheAccess, // Cache access // cache internals input logic CacheHit, // Exactly 1 way hits @@ -55,7 +55,7 @@ module cachefsm #(parameter READ_ONLY_CACHE = 0) ( input logic FlushAdrFlag, // On last set of a cache flush input logic FlushWayFlag, // On the last way for any set of a cache flush output logic SelAdr, // [0] SRAM reads from NextAdr, [1] SRAM reads from PAdr - output logic SetValid, // Set the dirty bit in the selected way and set + output logic SetValid, // Set the valid bit in the selected way and set output logic ClearDirty, // Clear the dirty bit in the selected way and set output logic SetDirty, // Set the dirty bit in the selected way and set output logic SelWriteback, // Overrides cached tag check to select a specific way and set for writeback diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 174b82c59..e727662d6 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -35,7 +35,7 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, input logic reset, input logic FlushStage, // Pipeline flush of second stage (prevent writes and bus operations) input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant - input logic [$clog2(NUMLINES)-1:0] CacheSet, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr + input logic [$clog2(NUMLINES)-1:0] CacheSet, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr input logic [`PA_BITS-1:0] PAdr, // Physical address input logic [LINELEN-1:0] LineWriteData, // Final data written to cache (D$ only) input logic SetValid, // Set the valid bit in the selected way and set @@ -45,14 +45,14 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, input logic SelFlush, // [0] Use SelAdr, [1] SRAM reads/writes from FlushAdr input logic VictimWay, // LRU selected this way as victim to evict input logic FlushWay, // This way is selected for flush and possible writeback if dirty - input logic InvalidateCache,//Clear all valid bits + input logic InvalidateCache,// Clear all valid bits input logic [LINELEN/8-1:0] LineByteMask, // Final byte enables to cache (D$ only) output logic [LINELEN-1:0] ReadDataLineWay,// This way's read data if valid output logic HitWay, // This way hits output logic ValidWay, // This way is valid output logic DirtyWay, // This way is dirty - output logic [TAGLEN-1:0] TagWay); // THis way's tag if valid + output logic [TAGLEN-1:0] TagWay); // This way's tag if valid localparam WORDSPERLINE = LINELEN/`XLEN; localparam BYTESPERLINE = LINELEN/8; diff --git a/src/fpu/fcmp.sv b/src/fpu/fcmp.sv index 3be33d997..63c234328 100755 --- a/src/fpu/fcmp.sv +++ b/src/fpu/fcmp.sv @@ -71,11 +71,11 @@ module fcmp ( // EQ - quiet - sets invalid if signaling NaN input always_comb begin case (OpCtrl[2:0]) - 3'b110: CmpNV = EitherSNaN;//min - 3'b101: CmpNV = EitherSNaN;//max - 3'b010: CmpNV = EitherSNaN;//equal - 3'b001: CmpNV = EitherNaN;//less than - 3'b011: CmpNV = EitherNaN;//less than or equal + 3'b110: CmpNV = EitherSNaN; //min + 3'b101: CmpNV = EitherSNaN; //max + 3'b010: CmpNV = EitherSNaN; //equal + 3'b001: CmpNV = EitherNaN; //less than + 3'b011: CmpNV = EitherNaN; //less than or equal default: CmpNV = 1'bx; endcase end @@ -137,19 +137,19 @@ module fcmp ( if(YNaN) CmpFpRes = NaNRes; // X = NaN Y = NaN else CmpFpRes = Y; // X = NaN Y != NaN else - if(YNaN) CmpFpRes = X; // X != NaN Y = NaN + if(YNaN) CmpFpRes = X; // X != NaN Y = NaN else // X,Y != NaN - if(LT) CmpFpRes = Y; // X < Y - else CmpFpRes = X; // X > Y + if(LT) CmpFpRes = Y; // X < Y + else CmpFpRes = X; // X > Y else // MIN if(XNaN) if(YNaN) CmpFpRes = NaNRes; // X = NaN Y = NaN else CmpFpRes = Y; // X = NaN Y != NaN else - if(YNaN) CmpFpRes = X; // X != NaN Y = NaN + if(YNaN) CmpFpRes = X; // X != NaN Y = NaN else // X,Y != NaN - if(LT) CmpFpRes = X; // X < Y - else CmpFpRes = Y; // X > Y + if(LT) CmpFpRes = X; // X < Y + else CmpFpRes = Y; // X > Y // LT/LE/EQ // - -0 = 0 diff --git a/src/fpu/fsgninj.sv b/src/fpu/fsgninj.sv index 9ce938709..f85206b41 100755 --- a/src/fpu/fsgninj.sv +++ b/src/fpu/fsgninj.sv @@ -48,7 +48,7 @@ module fsgninj ( // format final result based on precision // - uses NaN-blocking format - // - if there are any unsused bits the most significant bits are filled with 1s + // - if there are any unused bits the most significant bits are filled with 1s if (`FPSIZES == 1) assign SgnRes = {ResSgn, X[`FLEN-2:0]}; diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index 77c4b6158..8732f29f2 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -27,7 +27,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module popcnt #(parameter WIDTH = 32) ( - input logic [WIDTH-1:0] num, // number to count total ones + input logic [WIDTH-1:0] num, // number to count total ones output logic [$clog2(WIDTH):0] PopCnt // the total number of ones ); diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index d18e20ecc..25395825b 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -300,7 +300,7 @@ module controller( assign FlushDCacheD = 0; end - // Decocde stage pipeline control register + // Decode stage pipeline control register flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD); // Execute stage pipeline control register and logic diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index d6fe92a2a..df9216761 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -138,7 +138,8 @@ module datapath ( assign MulDivResultW = MDUResultW; end end else begin:fpmux - assign IFResultM = IEUResultM; assign IFCvtResultW = IFResultW; + assign IFResultM = IEUResultM; + assign IFCvtResultW = IFResultW; assign MulDivResultW = MDUResultW; end mux5 #(`XLEN) resultmuxW(IFCvtResultW, ReadDataW, CSRReadValW, MulDivResultW, SCResultW, ResultSrcW, ResultW); diff --git a/src/ieu/regfile.sv b/src/ieu/regfile.sv index a4ee1cc3e..967a2101e 100644 --- a/src/ieu/regfile.sv +++ b/src/ieu/regfile.sv @@ -32,7 +32,7 @@ module regfile ( input logic clk, reset, input logic we3, // Write enable - input logic [ 4:0] a1, a2, a3, // Source registers to read (a1, a2), destination register to write (a3) + input logic [4:0] a1, a2, a3, // Source registers to read (a1, a2), destination register to write (a3) input logic [`XLEN-1:0] wd3, // Write data for port 3 output logic [`XLEN-1:0] rd1, rd2); // Read data for ports 1, 2 diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index 132ec590f..5227ee3bd 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -32,7 +32,7 @@ module shifter ( input logic [`XLEN-1:0] A, // shift Source input logic [`LOG_XLEN-1:0] Amt, // Shift amount - input logic Right, Rotate, W64, SubArith, // Shift right, rotate, W64-type operation, arithmetic shift + input logic Right, Rotate, W64, SubArith, // Shift right, rotate, W64-type operation, arithmetic shift output logic [`XLEN-1:0] Y); // Shifted result logic [2*`XLEN-2:0] Z, ZShift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits diff --git a/src/ifu/decompress.sv b/src/ifu/decompress.sv index f0882ddf7..bc9ae0abe 100644 --- a/src/ifu/decompress.sv +++ b/src/ifu/decompress.sv @@ -44,7 +44,7 @@ module decompress ( logic [5:0] immSH; logic [1:0] op; - // Extrac op and register source/destination fields + // Extract op and register source/destination fields assign instr16 = InstrRawD[15:0]; // instruction is already aligned assign op = instr16[1:0]; assign rds1 = instr16[11:7]; diff --git a/src/ifu/ifu.sv b/src/ifu/ifu.sv index 75b2bc9e8..82e8a33b9 100644 --- a/src/ifu/ifu.sv +++ b/src/ifu/ifu.sv @@ -4,7 +4,7 @@ // Written: David_Harris@hmc.edu 9 January 2021 // Modified: // -// Purpose: Instrunction Fetch Unit +// Purpose: Instruction Fetch Unit // PC, branch prediction, instruction cache // // A component of the CORE-V-WALLY configurable RISC-V project. @@ -362,7 +362,7 @@ module ifu ( assign IllegalIEUFPUInstrD = IllegalIEUInstrD & IllegalFPUInstrD; // Misaligned PC logic - // Instruction address misalignement only from br/jal(r) instructions. + // Instruction address misalignment only from br/jal(r) instructions. // instruction address misalignment is generated by the target of control flow instructions, not // the fetch itself. // xret and Traps both cannot produce instruction misaligned. @@ -372,7 +372,7 @@ module ifu ( // Spec 3.1.14 // Traps: Can’t happen. The bottom two bits of MTVEC are ignored so the trap always is to a multiple of 4. See 3.1.7 of the privileged spec. assign BranchMisalignedFaultE = (IEUAdrE[1] & ~`C_SUPPORTED) & PCSrcE; - flopenr #(1) InstrMisalginedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM); + flopenr #(1) InstrMisalignedReg(clk, reset, ~StallM, BranchMisalignedFaultE, InstrMisalignedFaultM); // Instruction and PC/PCLink pipeline registers // Cannot use flopenrc for Instr(E/M) as it resets to NOP not 0. diff --git a/src/mdu/mdu.sv b/src/mdu/mdu.sv index 29ae36966..64fdc2891 100644 --- a/src/mdu/mdu.sv +++ b/src/mdu/mdu.sv @@ -69,8 +69,8 @@ module mdu( 3'b001: PrelimResultM = ProdM[`XLEN*2-1:`XLEN]; // mulh 3'b010: PrelimResultM = ProdM[`XLEN*2-1:`XLEN]; // mulhsu 3'b011: PrelimResultM = ProdM[`XLEN*2-1:`XLEN]; // mulhu - 3'b100: PrelimResultM = QuotM; // div - 3'b101: PrelimResultM = QuotM; // divu + 3'b100: PrelimResultM = QuotM; // div + 3'b101: PrelimResultM = QuotM; // divu 3'b110: PrelimResultM = RemM; // rem 3'b111: PrelimResultM = RemM; // remu endcase diff --git a/src/mmu/mmu.sv b/src/mmu/mmu.sv index ffd01c440..ccbbfaf78 100644 --- a/src/mmu/mmu.sv +++ b/src/mmu/mmu.sv @@ -49,14 +49,14 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) ( output logic Idempotent, // PMA indicates memory address is idempotent output logic SelTIM, // Select a tightly integrated memory // Faults - output logic InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM, // access fault sources - output logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM, // page fault sources - output logic UpdateDA, // page fault due to setting dirty or access bit - output logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM, // misaligned fault sources + output logic InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM, // access fault sources + output logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM, // page fault sources + output logic UpdateDA, // page fault due to setting dirty or access bit + output logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM, // misaligned fault sources // PMA checker signals - input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // access type - input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration - input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP addresses + input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // access type + input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0], // PMP configuration + input var logic [`PA_BITS-3:0] PMPADDR_ARRAY_REGW[`PMP_ENTRIES-1:0] // PMP addresses ); logic [`PA_BITS-1:0] TLBPAdr; // physical address for TLB @@ -86,7 +86,7 @@ module mmu #(parameter TLB_ENTRIES = 8, IMMU = 0) ( .DisableTranslation, .PTE, .PageTypeWriteVal, .TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss, .TLBHit, .Translate, .TLBPageFault, .UpdateDA); - end else begin:tlb// just pass address through as physical + end else begin:tlb // just pass address through as physical assign Translate = 0; assign TLBMiss = 0; assign TLBHit = 1; // *** is this necessary diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 92efebbf7..94c72a134 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -93,7 +93,7 @@ module csrsr ( // harwired STATUS bits assign STATUS_TSR = `S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported - assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override reigster with 0 if only machine mode supported + assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override register with 0 if only machine mode supported assign STATUS_TVM = `S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported assign STATUS_MXR = `S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported /* assign STATUS_UBE = 0; // little-endian From 419377a8f8d7af5766d5b6b878363c133d69903c Mon Sep 17 00:00:00 2001 From: Noah Limpert Date: Thu, 13 Apr 2023 16:59:10 -0700 Subject: [PATCH 19/40] git did not seem to add tests.vh, trying again --- testbench/tests.vh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/testbench/tests.vh b/testbench/tests.vh index 55cf464fa..6a0f80276 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -52,7 +52,8 @@ string tvpaths[] = '{ "fpu", "lsu", "vm64check", - "pmp" + "pmp", + "tlbKP" }; string coremark[] = '{ From 51f65614768d3215545bebdce868f2b7c2541940 Mon Sep 17 00:00:00 2001 From: Limnanthes Serafini Date: Thu, 13 Apr 2023 17:00:41 -0700 Subject: [PATCH 20/40] A couple indents->spaces --- testbench/testbench.sv | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index 386dc8d8b..b3c0efeab 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -593,13 +593,13 @@ end if (`DCACHE_SUPPORTED && `D_CACHE_ADDR_LOGGER) begin : DCacheLogger int file; - string LogFile; - logic resetD, resetEdge; + string LogFile; + logic resetD, resetEdge; logic Enabled; string AccessTypeString, HitMissString; - flop #(1) ResetDReg(clk, reset, resetD); - assign resetEdge = ~reset & resetD; + flop #(1) ResetDReg(clk, reset, resetD); + assign resetEdge = ~reset & resetD; assign HitMissString = dut.core.lsu.bus.dcache.dcache.CacheHit ? "H" : (!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" : dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E"; From 4ab27b4f12f5efcb43a34f17bdde8dcc166dabff Mon Sep 17 00:00:00 2001 From: Noah Limpert Date: Thu, 13 Apr 2023 17:28:37 -0700 Subject: [PATCH 21/40] Revert "Test File for Pull Request, Attempt to fill all four ways" This reverts commit f7702436896f88b9cd921ac95e241a32ffb6499f. --- tests/coverage/lsu_test1.S | 34 ---------------------------------- 1 file changed, 34 deletions(-) delete mode 100644 tests/coverage/lsu_test1.S diff --git a/tests/coverage/lsu_test1.S b/tests/coverage/lsu_test1.S deleted file mode 100644 index 92d01b196..000000000 --- a/tests/coverage/lsu_test1.S +++ /dev/null @@ -1,34 +0,0 @@ -//lsu.S -// A set of tests meant to stress the LSU to increase coverage -// Manuel Alejandro Mendoza Manriquez mmendozamanriquez@g.hmc.edu -// Noah Limpert nlimpert@g.hmc.edu -// March 28 2023 - - -// Test 1 -// Cache ways 1,2,3 do not have SelFlush = 0 -// To make SelFlush = 0 we must evict lines from ways 1,2,3 -// Will load 4 words with same tags, filling 4 ways of cache -// edit and store these words so that dirty bit is set ( is this necessary?) -// Will then load 4 more words, evicting the previous 4 words -// will make SelFlush = 0 for all 4 ways. - -// Load code to initialize stack, handle interrupts, terminate -#include "WALLY-init-lib.h" - -main: - li t0, 4096 //offset such that set will be same - li t1, 0 #t1 = i = 0 - li t2, 8 # n = 8 - add t3, sp, 0 // what our offset for loads and stores will be - -for1: bge t1, t2, done - add t3, t3, t0 - lw t4, 0(t3) - addi t4, t4, 1 - sw t4, 0(t3) - addi t1, t1, 1 - j for1 - - - From 2e568877b0854b603fa35dc352e287ea38a0d5ec Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 13 Apr 2023 17:40:14 -0700 Subject: [PATCH 22/40] fdivsqrtfsm coverage attempt to waive a state --- sim/coverage-exclusions-rv64gc.do | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index d58e4c514..65ea0162e 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -32,6 +32,9 @@ # This is ugly to exlcude the whole file - is there a better option? // coverage off isn't working coverage exclude -srcfile lzc.sv +# FDIVSQRT has +coverage exclude -scope /core/fpu/fpu/fdivsqrt/fdivsqrtfsm -ftrans state DONE->BUSY + ###################### # Toggle exclusions @@ -47,3 +50,4 @@ coverage exclude -srcfile lzc.sv # StallFCause is hardwired to 0 #coverage exclude -togglenode /dut/core/hzu/StallFCause + From c76de00d606fb0ff45cef2a52109a790719ac020 Mon Sep 17 00:00:00 2001 From: Noah Limpert Date: Thu, 13 Apr 2023 17:40:39 -0700 Subject: [PATCH 23/40] Revert "instantiate 5 4KiB arrays, aim to thrash all 4 ways" This reverts commit 0fea40282ad829a7823ab286ab02a070ab574fa6. --- tests/coverage/lsuGB.S | 99 ------------------------------------------ 1 file changed, 99 deletions(-) delete mode 100644 tests/coverage/lsuGB.S diff --git a/tests/coverage/lsuGB.S b/tests/coverage/lsuGB.S deleted file mode 100644 index 8a902ba7f..000000000 --- a/tests/coverage/lsuGB.S +++ /dev/null @@ -1,99 +0,0 @@ -//lsuGB.S -// A set of tests meant to stress the LSU to increase coverage -// Manuel Alejandro Mendoza Manriquez mmendozamanriquez@g.hmc.edu -// Noah Limpert nlimpert@g.hmc.edu -// March 28 2023 - - -// Test 2 -//Try to thrash ! used godbolt! -// Cache ways 1,2,3 do not have SelFlush = 0 -// To make SelFlush = 0 we must evict lines from ways 1,2,3 -// Will load 4 words with same tags, filling 4 ways of cache -// edit and store these words so that dirty bit is set ( is this necessary?) -// Will then load 4 more words, evicting the previous 4 words -// will make SelFlush = 0 for all 4 ways. - -// Load code to initialize stack, handle interrupts, terminate -#include "WALLY-init-lib.h" - -main: - addi sp,sp,-32 - sd s0,24(sp) - addi s0,sp,32 - li t1,-20480 - add sp,sp,t1 - sw zero,-20(s0) - j .L2 -.L3: - li a5,-4096 - addi a4,s0,-16 - add a4,a4,a5 - lw a5,-20(s0) - slli a5,a5,2 - add a5,a4,a5 - lw a4,-8(a5) - li a5,-8192 - addi a3,s0,-16 - add a3,a3,a5 - lw a5,-20(s0) - slli a5,a5,2 - add a5,a3,a5 - sw a4,-8(a5) - li a5,-8192 - addi a4,s0,-16 - add a4,a4,a5 - lw a5,-20(s0) - slli a5,a5,2 - add a5,a4,a5 - lw a4,-8(a5) - li a5,-12288 - addi a3,s0,-16 - add a3,a3,a5 - lw a5,-20(s0) - slli a5,a5,2 - add a5,a3,a5 - sw a4,-8(a5) - li a5,-12288 - addi a4,s0,-16 - add a4,a4,a5 - lw a5,-20(s0) - slli a5,a5,2 - add a5,a4,a5 - lw a4,-8(a5) - li a5,-16384 - addi a3,s0,-16 - add a3,a3,a5 - lw a5,-20(s0) - slli a5,a5,2 - add a5,a3,a5 - sw a4,-8(a5) - li a5,-16384 - addi a4,s0,-16 - add a4,a4,a5 - lw a5,-20(s0) - slli a5,a5,2 - add a5,a4,a5 - lw a4,-8(a5) - li a5,-20480 - addi a3,s0,-16 - add a3,a3,a5 - lw a5,-20(s0) - slli a5,a5,2 - add a5,a3,a5 - sw a4,-8(a5) - lw a5,-20(s0) - addiw a5,a5,1 - sw a5,-20(s0) -.L2: - lw a5,-20(s0) - sext.w a4,a5 - li a5,1023 - ble a4,a5,.L3 - nop - nop - li t1,20480 - add sp,sp,t1 - ld s0,24(sp) - addi sp,sp,32 - j done \ No newline at end of file From 187c5b07c79354ba579d9744a419158c05cbb854 Mon Sep 17 00:00:00 2001 From: Noah Limpert Date: Thu, 13 Apr 2023 17:44:09 -0700 Subject: [PATCH 24/40] make pull request more clean --- tests/coverage/lsu.S | 35 ----------------------------------- 1 file changed, 35 deletions(-) delete mode 100644 tests/coverage/lsu.S diff --git a/tests/coverage/lsu.S b/tests/coverage/lsu.S deleted file mode 100644 index a5d8b1e51..000000000 --- a/tests/coverage/lsu.S +++ /dev/null @@ -1,35 +0,0 @@ -/////////////////////////////////////////// -// lsu.S -// -// Written: Kevin Box and Miles Cook kbox@hmc.edu mdcook@hmc.edu 26 March 2023 -// -// Purpose: Test coverage for lsu -// -// A component of the CORE-V-WALLY configurable RISC-V project. -// -// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// load code to initalize stack, handle interrupts, terminate -#include "WALLY-init-lib.h" - -main: - - sfence.vma x0, x0 // sfence.vma to assert TLBFlush - - j done - - From 30ed9c2b69264cc0cafe6d2b766aa803511fae00 Mon Sep 17 00:00:00 2001 From: Noah Limpert Date: Thu, 13 Apr 2023 17:50:18 -0700 Subject: [PATCH 25/40] add back K. Box and M. Cook Lsu test --- tests/coverage/lsu.S | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) create mode 100644 tests/coverage/lsu.S diff --git a/tests/coverage/lsu.S b/tests/coverage/lsu.S new file mode 100644 index 000000000..c50b79eb7 --- /dev/null +++ b/tests/coverage/lsu.S @@ -0,0 +1,33 @@ +/////////////////////////////////////////// +// lsu.S +// +// Written: Kevin Box and Miles Cook kbox@hmc.edu mdcook@hmc.edu 26 March 2023 +// +// Purpose: Test coverage for lsu +// +// A component of the CORE-V-WALLY configurable RISC-V project. +// +// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// load code to initalize stack, handle interrupts, terminate +#include "WALLY-init-lib.h" + +main: + + sfence.vma x0, x0 // sfence.vma to assert TLBFlush + + j done \ No newline at end of file From 0862688168cf070ccf1e84f09230f8240f36ef30 Mon Sep 17 00:00:00 2001 From: Limnanthes Serafini Date: Thu, 13 Apr 2023 19:06:09 -0700 Subject: [PATCH 26/40] testbench code visual improvements --- testbench/testbench.sv | 464 ++++++++++++++++++++--------------------- 1 file changed, 232 insertions(+), 232 deletions(-) diff --git a/testbench/testbench.sv b/testbench/testbench.sv index b3c0efeab..94f8d501b 100644 --- a/testbench/testbench.sv +++ b/testbench/testbench.sv @@ -52,29 +52,29 @@ module testbench; string tests[]; logic [3:0] dummy; - logic [`AHBW-1:0] HRDATAEXT; - logic HREADYEXT, HRESPEXT; + logic [`AHBW-1:0] HRDATAEXT; + logic HREADYEXT, HRESPEXT; logic [`PA_BITS-1:0] HADDR; - logic [`AHBW-1:0] HWDATA; - logic [`XLEN/8-1:0] HWSTRB; - logic HWRITE; - logic [2:0] HSIZE; - logic [2:0] HBURST; - logic [3:0] HPROT; - logic [1:0] HTRANS; - logic HMASTLOCK; - logic HCLK, HRESETn; - logic [`XLEN-1:0] PCW; + logic [`AHBW-1:0] HWDATA; + logic [`XLEN/8-1:0] HWSTRB; + logic HWRITE; + logic [2:0] HSIZE; + logic [2:0] HBURST; + logic [3:0] HPROT; + logic [1:0] HTRANS; + logic HMASTLOCK; + logic HCLK, HRESETn; + logic [`XLEN-1:0] PCW; - string ProgramAddrMapFile, ProgramLabelMapFile; - integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 }; + string ProgramAddrMapFile, ProgramLabelMapFile; + integer ProgramAddrLabelArray [string] = '{ "begin_signature" : 0, "tohost" : 0 }; - logic DCacheFlushDone, DCacheFlushStart; + logic DCacheFlushDone, DCacheFlushStart; logic riscofTest; logic StartSample, EndSample; flopenr #(`XLEN) PCWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.PCM, PCW); - flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW); + flopenr #(32) InstrWReg(clk, reset, ~dut.core.ieu.dp.StallW, dut.core.ifu.InstrM, InstrW); // check assertions for a legal configuration riscvassertions riscvassertions(); @@ -149,7 +149,7 @@ module testbench; end end - string signame, memfilename, pathname, objdumpfilename, adrstr, outputfile; + string signame, memfilename, pathname, objdumpfilename, adrstr, outputfile; integer outputFilePointer; logic [31:0] GPIOIN, GPIOOUT, GPIOEN; @@ -160,16 +160,16 @@ module testbench; logic SDCCmdOut; logic SDCCmdOE; logic [3:0] SDCDatIn; - tri1 [3:0] SDCDat; + tri1 [3:0] SDCDat; tri1 SDCCmd; logic HREADY; logic HSELEXT; - logic InitializingMemories; + logic InitializingMemories; integer ResetCount, ResetThreshold; - logic InReset; - logic Begin; + logic InReset; + logic BeginSample; // instantiate device to be tested assign GPIOIN = 0; @@ -225,13 +225,14 @@ module testbench; totalerrors = 0; testadr = 0; testadrNoBase = 0; - // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests and tests[0] == "2" refers to WallyRiscvArchTests + // riscof tests have a different signature, tests[0] == "1" refers to RiscvArchTests + // and tests[0] == "2" refers to WallyRiscvArchTests riscofTest = tests[0] == "1" | tests[0] == "2"; // fill memory with defined values to reduce Xs in simulation // Quick note the memory will need to be initialized. The C library does not - // guarantee the initialized reads. For example a strcmp can read 6 byte - // strings, but uses a load double to read them in. If the last 2 bytes are - // not initialized the compare results in an 'x' which propagates through + // guarantee the initialized reads. For example a strcmp can read 6 byte + // strings, but uses a load double to read them in. If the last 2 bytes are + // not initialized the compare results in an 'x' which propagates through // the design. if (TEST == "coremark") for (i=MemStartAddr; i Date: Thu, 13 Apr 2023 21:01:57 -0700 Subject: [PATCH 29/40] Some cleanup --- src/cache/cache.sv | 18 +++++++++--------- src/cache/cacheLRU.sv | 4 ++-- src/cache/cachefsm.sv | 4 ++-- src/cache/subcachelineread.sv | 5 ++--- 4 files changed, 15 insertions(+), 16 deletions(-) diff --git a/src/cache/cache.sv b/src/cache/cache.sv index 4721eb167..ebee8f4f1 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// cache +// cache.sv // // Written: Ross Thompson ross1728@gmail.com // Created: 7 July 2021 @@ -167,22 +167,22 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE // Adjust byte mask from word to cache line onehotdecoder #(LOGCWPL) adrdec(.bin(PAdr[LOGCWPL+LOGLLENBYTES-1:LOGLLENBYTES]), .decoded(MemPAdrDecoded)); for(index = 0; index < 2**LOGCWPL; index++) begin - assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0; + assign DemuxedByteMask[(index+1)*(WORDLEN/8)-1:index*(WORDLEN/8)] = MemPAdrDecoded[index] ? ByteMask : '0; end assign FetchBufferByteSel = SetValid & ~SetDirty ? '1 : ~DemuxedByteMask; // If load miss set all muxes to 1. // Merge write data into fetched cache line for store miss for(index = 0; index < LINELEN/8; index++) begin - mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]), - .d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index])); + mux2 #(8) WriteDataMux(.d0(CacheWriteData[(8*index)%WORDLEN+7:(8*index)%WORDLEN]), + .d1(FetchBuffer[8*index+7:8*index]), .s(FetchBufferByteSel[index]), .y(LineWriteData[8*index+7:8*index])); end assign LineByteMask = SetValid ? '1 : SetDirty ? DemuxedByteMask : '0; end else begin:WriteSelLogic - // No need for this mux if the cache does not handle writes. - assign LineWriteData = FetchBuffer; - assign LineByteMask = '1; + // No need for this mux if the cache does not handle writes. + assign LineWriteData = FetchBuffer; + assign LineByteMask = '1; end ///////////////////////////////////////////////////////////////////////////////////////////// // Flush logic @@ -203,8 +203,8 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE assign FlushWayFlag = FlushWay[NUMWAYS-1]; end // block: flushlogic else begin:flushlogic - assign FlushWayFlag = 0; - assign FlushAdrFlag = 0; + assign FlushWayFlag = 0; + assign FlushAdrFlag = 0; end ///////////////////////////////////////////////////////////////////////////////////////////// diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index 1e7101365..87d9f072a 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// dcache (data cache) +// cacheLRU.sv // // Written: Ross Thompson ross1728@gmail.com // Created: 20 July 2021 @@ -37,7 +37,7 @@ module cacheLRU input logic CacheEn, // Enable the cache memory arrays. Disable hold read data constant input logic [NUMWAYS-1:0] HitWay, // Which way is valid and matches PAdr's tag input logic [NUMWAYS-1:0] ValidWay, // Which ways for a particular set are valid, ignores tag - input logic [SETLEN-1:0] CacheSet, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr + input logic [SETLEN-1:0] CacheSet, // Cache address, the output of the address select mux, NextAdr, PAdr, or FlushAdr input logic [SETLEN-1:0] PAdr, // Physical address input logic LRUWriteEn, // Update the LRU state input logic SetValid, // Set the dirty bit in the selected way and set diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 2a5cb8235..525d7524f 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -1,11 +1,11 @@ /////////////////////////////////////////// -// dcache (data cache) fsm +// cachefsm.sv // // Written: Ross Thompson ross1728@gmail.com // Created: 25 August 2021 // Modified: 20 January 2023 // -// Purpose: Controller for the dcache fsm +// Purpose: Controller for the cache fsm // // Documentation: RISC-V System on Chip Design Chapter 7 (Figure 7.14 and Table 7.1) // diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv index 58d022a71..ea305fb6c 100644 --- a/src/cache/subcachelineread.sv +++ b/src/cache/subcachelineread.sv @@ -1,11 +1,11 @@ /////////////////////////////////////////// -// subcachelineread +// subcachelineread.sv // // Written: Ross Thompson ross1728@gmail.com // Created: 4 February 2022 // Modified: 20 January 2023 // -// Purpose: Muxes the cache line downto the word size. Also include possilbe save/restore registers/muxes. +// Purpose: Muxes the cache line down to the word size. Also include possible save/restore registers/muxes. // // Documentation: RISC-V System on Chip Design Chapter 7 @@ -31,7 +31,6 @@ module subcachelineread #(parameter LINELEN, WORDLEN, parameter MUXINTERVAL )( // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$ - input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, // Physical address input logic [LINELEN-1:0] ReadDataLine,// Read data of the whole cacheline output logic [WORDLEN-1:0] ReadDataWord // read data of selected word. From 94b686fcf6eccafd5754a3824774d4a028d37c9e Mon Sep 17 00:00:00 2001 From: Limnanthes Serafini Date: Thu, 13 Apr 2023 21:02:15 -0700 Subject: [PATCH 30/40] More changes --- src/ebu/ahbcacheinterface.sv | 28 +++++++++--------- src/ebu/ahbinterface.sv | 16 +++++------ src/ebu/buscachefsm.sv | 30 ++++++++++---------- src/ebu/controllerinput.sv | 36 +++++++++++------------ src/ebu/ebufsmarb.sv | 6 ++-- src/fpu/fdivsqrt/fdivsqrtexpcalc.sv | 44 ++++++++++++++--------------- 6 files changed, 80 insertions(+), 80 deletions(-) diff --git a/src/ebu/ahbcacheinterface.sv b/src/ebu/ahbcacheinterface.sv index e2e7d3696..38b1e6879 100644 --- a/src/ebu/ahbcacheinterface.sv +++ b/src/ebu/ahbcacheinterface.sv @@ -38,27 +38,27 @@ module ahbcacheinterface #( )( input logic HCLK, HRESETn, // bus interface controls - input logic HREADY, // AHB peripheral ready + input logic HREADY, // AHB peripheral ready output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ output logic HWRITE, // AHB 0: Read operation 1: Write operation output logic [2:0] HSIZE, // AHB transaction width output logic [2:0] HBURST, // AHB burst length // bus interface buses - input logic [`AHBW-1:0] HRDATA, // AHB read data + input logic [`AHBW-1:0] HRDATA, // AHB read data output logic [`PA_BITS-1:0] HADDR, // AHB address output logic [`AHBW-1:0] HWDATA, // AHB write data output logic [`AHBW/8-1:0] HWSTRB, // AHB byte mask // cache interface - input logic [`PA_BITS-1:0] CacheBusAdr, // Address of cache line - input logic [`LLEN-1:0] CacheReadDataWordM, // one word of cache line during a writeback - input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$ - input logic Cacheable, // Memory operation is cachable - input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch - output logic CacheBusAck, // Handshack to $ indicating bus transaction completed - output logic [LINELEN-1:0] FetchBuffer, // Register to hold beats of cache line as the arrive from bus - output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase - output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr + input logic [`PA_BITS-1:0] CacheBusAdr, // Address of cache line + input logic [`LLEN-1:0] CacheReadDataWordM, // One word of cache line during a writeback + input logic CacheableOrFlushCacheM, // Memory operation is cacheable or flushing D$ + input logic Cacheable, // Memory operation is cachable + input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch + output logic CacheBusAck, // Handshake to $ indicating bus transaction completed + output logic [LINELEN-1:0] FetchBuffer, // Register to hold beats of cache line as the arrive from bus + output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase + output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr // uncached interface input logic [`PA_BITS-1:0] PAdr, // Physical address of uncached memory operation @@ -77,7 +77,7 @@ module ahbcacheinterface #( logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA - logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s + logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data genvar index; @@ -107,7 +107,7 @@ module ahbcacheinterface #( end else assign CacheReadDataWordAHB = CacheReadDataWordM[`AHBW-1:0]; mux2 #(`AHBW) HWDATAMux(.d0(CacheReadDataWordAHB), .d1(WriteDataM[`AHBW-1:0]), - .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); + .s(~(CacheableOrFlushCacheM)), .y(PreHWDATA)); flopen #(`AHBW) wdreg(HCLK, HREADY, PreHWDATA, HWDATA); // delay HWDATA by 1 cycle per spec // *** bummer need a second byte mask for bus as it is AHBW rather than LLEN. @@ -119,5 +119,5 @@ module ahbcacheinterface #( buscachefsm #(BeatCountThreshold, AHBWLOGBWPL, READ_ONLY_CACHE) AHBBuscachefsm( .HCLK, .HRESETn, .Flush, .BusRW, .Stall, .BusCommitted, .BusStall, .CaptureEn, .SelBusBeat, .CacheBusRW, .CacheBusAck, .BeatCount, .BeatCountDelayed, - .HREADY, .HTRANS, .HWRITE, .HBURST); + .HREADY, .HTRANS, .HWRITE, .HBURST); endmodule diff --git a/src/ebu/ahbinterface.sv b/src/ebu/ahbinterface.sv index 579791032..1a9308dd4 100644 --- a/src/ebu/ahbinterface.sv +++ b/src/ebu/ahbinterface.sv @@ -32,21 +32,21 @@ module ahbinterface #( parameter LSU = 0 // 1: LSU bus width is `XLEN, 0: IFU bus width is 32 bits )( - input logic HCLK, HRESETn, + input logic HCLK, HRESETn, // bus interface - input logic HREADY, // AHB peripheral ready + input logic HREADY, // AHB peripheral ready output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ output logic HWRITE, // AHB 0: Read operation 1: Write operation - input logic [`XLEN-1:0] HRDATA, // AHB read data + input logic [`XLEN-1:0] HRDATA, // AHB read data output logic [`XLEN-1:0] HWDATA, // AHB write data output logic [`XLEN/8-1:0] HWSTRB, // AHB byte mask // lsu/ifu interface - input logic Stall, // Core pipeline is stalled - input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting - input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write - input logic [`XLEN/8-1:0] ByteMask, // Bytes enables within a word - input logic [`XLEN-1:0] WriteData, // IEU write data for a store + input logic Stall, // Core pipeline is stalled + input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting + input logic [1:0] BusRW, // Memory operation read/write control: 10: read, 01: write + input logic [`XLEN/8-1:0] ByteMask, // Bytes enables within a word + input logic [`XLEN-1:0] WriteData, // IEU write data for a store output logic BusStall, // Bus is busy with an in flight memory operation output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt output logic [(LSU ? `XLEN : 32)-1:0] FetchBuffer // Register to hold HRDATA after arriving from the bus diff --git a/src/ebu/buscachefsm.sv b/src/ebu/buscachefsm.sv index e0efcf3a3..7456cac8b 100644 --- a/src/ebu/buscachefsm.sv +++ b/src/ebu/buscachefsm.sv @@ -40,29 +40,29 @@ module buscachefsm #( input logic HRESETn, // IEU interface - input logic Stall, // Core pipeline is stalled - input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting - input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write - output logic BusStall, // Bus is busy with an in flight memory operation - output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt + input logic Stall, // Core pipeline is stalled + input logic Flush, // Pipeline stage flush. Prevents bus transaction from starting + input logic [1:0] BusRW, // Uncached memory operation read/write control: 10: read, 01: write + output logic BusStall, // Bus is busy with an in flight memory operation + output logic BusCommitted, // Bus is busy with an in flight memory operation and it is not safe to take an interrupt // ahb cache interface locals. - output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA + output logic CaptureEn, // Enable updating the Fetch buffer with valid data from HRDATA // cache interface - input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch - output logic CacheBusAck, // Handshack to $ indicating bus transaction completed + input logic [1:0] CacheBusRW, // Cache bus operation, 01: writeback, 10: fetch + output logic CacheBusAck, // Handshack to $ indicating bus transaction completed // lsu interface output logic [AHBWLOGBWPL-1:0] BeatCount, // Beat position within the cache line in the Address Phase output logic [AHBWLOGBWPL-1:0] BeatCountDelayed, // Beat within the cache line in the second (Data) cache stage - output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr + output logic SelBusBeat, // Tells the cache to select the word from ReadData or WriteData from BeatCount rather than PAdr // BUS interface - input logic HREADY, // AHB peripheral ready - output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ - output logic HWRITE, // AHB 0: Read operation 1: Write operation - output logic [2:0] HBURST // AHB burst length + input logic HREADY, // AHB peripheral ready + output logic [1:0] HTRANS, // AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ + output logic HWRITE, // AHB 0: Read operation 1: Write operation + output logic [2:0] HBURST // AHB burst length ); typedef enum logic [2:0] {ADR_PHASE, DATA_PHASE, MEM3, CACHE_FETCH, CACHE_WRITEBACK} busstatetype; @@ -78,8 +78,8 @@ module buscachefsm #( logic CacheAccess; always_ff @(posedge HCLK) - if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE; - else CurrState <= #1 NextState; + if (~HRESETn | Flush) CurrState <= #1 ADR_PHASE; + else CurrState <= #1 NextState; always_comb begin case(CurrState) diff --git a/src/ebu/controllerinput.sv b/src/ebu/controllerinput.sv index a8c8e8308..6e3c27d3b 100644 --- a/src/ebu/controllerinput.sv +++ b/src/ebu/controllerinput.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// controller input stage +// controllerinput.sv // // Written: Ross Thompson ross1728@gmail.com // Created: August 31, 2022 @@ -36,26 +36,26 @@ module controllerinput #( parameter SAVE_ENABLED = 1 // 1: Save manager inputs if Save = 1, 0: Don't save inputs )( - input logic HCLK, - input logic HRESETn, - input logic Save, // Two or more managers requesting (HTRANS != 00) at the same time. Save the non-granted manager inputs - input logic Restore, // Restore a saved manager inputs when it is finally granted - input logic Disable, // Supress HREADY to the non-granted manager + input logic HCLK, + input logic HRESETn, + input logic Save, // Two or more managers requesting (HTRANS != 00) at the same time. Save the non-granted manager inputs + input logic Restore, // Restore a saved manager inputs when it is finally granted + input logic Disable, // Suppress HREADY to the non-granted manager output logic Request, // This manager is making a request // controller input - input logic [1:0] HTRANSIn, // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ - input logic HWRITEIn, // Manager input. AHB 0: Read operation 1: Write operation - input logic [2:0] HSIZEIn, // Manager input. AHB transaction width - input logic [2:0] HBURSTIn, // Manager input. AHB burst length - input logic [`PA_BITS-1:0] HADDRIn, // Manager input. AHB address - output logic HREADYOut, // Indicate to manager the peripherial is not busy and another manager does not have priority + input logic [1:0] HTRANSIn, // Manager input. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ + input logic HWRITEIn, // Manager input. AHB 0: Read operation 1: Write operation + input logic [2:0] HSIZEIn, // Manager input. AHB transaction width + input logic [2:0] HBURSTIn, // Manager input. AHB burst length + input logic [`PA_BITS-1:0] HADDRIn, // Manager input. AHB address + output logic HREADYOut, // Indicate to manager the peripheral is not busy and another manager does not have priority // controller output - output logic [1:0] HTRANSOut, // Aribrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ - output logic HWRITEOut, // Aribrated manager transaction. AHB 0: Read operation 1: Write operation - output logic [2:0] HSIZEOut, // Aribrated manager transaction. AHB transaction width - output logic [2:0] HBURSTOut, // Aribrated manager transaction. AHB burst length - output logic [`PA_BITS-1:0] HADDROut, // Aribrated manager transaction. AHB address - input logic HREADYIn // Peripherial ready + output logic [1:0] HTRANSOut, // Arbitrated manager transaction. AHB transaction type, 00: IDLE, 10 NON_SEQ, 11 SEQ + output logic HWRITEOut, // Arbitrated manager transaction. AHB 0: Read operation 1: Write operation + output logic [2:0] HSIZEOut, // Arbitrated manager transaction. AHB transaction width + output logic [2:0] HBURSTOut, // Arbitrated manager transaction. AHB burst length + output logic [`PA_BITS-1:0] HADDROut, // Arbitrated manager transaction. AHB address + input logic HREADYIn // Peripheral ready ); logic HWRITESave; diff --git a/src/ebu/ebufsmarb.sv b/src/ebu/ebufsmarb.sv index ec1a3d674..a61a3961f 100644 --- a/src/ebu/ebufsmarb.sv +++ b/src/ebu/ebufsmarb.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// ebufsmarb +// ebufsmarb.sv // // Written: Ross Thompson ross1728@gmail.com // Created: 23 January 2023 @@ -55,7 +55,7 @@ module ebufsmarb ( logic IFUReqD; // 1 cycle delayed IFU request. Part of arbitration logic FinalBeat, FinalBeatD; // Indicates the last beat of a burst logic BeatCntEn; - logic [3:0] BeatCount; // Position within a burst transfer + logic [3:0] BeatCount; // Position within a burst transfer logic BeatCntReset; logic [3:0] Threshold; // Number of beats derived from HBURST @@ -86,7 +86,7 @@ module ebufsmarb ( // Controller 1 (LSU) // When both the IFU and LSU request at the same time, the FSM will go into the arbitrate state. // Once the LSU request is done the fsm returns to IDLE. To prevent the LSU from regaining - // priority and re issuing the same memroy operation, the delayed IFUReqD squashes the LSU request. + // priority and re-issuing the same memory operation, the delayed IFUReqD squashes the LSU request. // This is necessary because the pipeline is stalled for the entire duration of both transactions, // and the LSU memory request will stil be active. flopr #(1) ifureqreg(HCLK, ~HRESETn, IFUReq, IFUReqD); diff --git a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv index 482fed842..aa8ae051d 100644 --- a/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtexpcalc.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// fdivsqrtpreproc.sv +// fdivsqrtexpcalc.sv // // Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu // Modified:13 January 2022 @@ -30,11 +30,11 @@ module fdivsqrtexpcalc( input logic [`FMTBITS-1:0] Fmt, - input logic [`NE-1:0] Xe, Ye, - input logic Sqrt, - input logic XZero, - input logic [`DIVBLEN:0] ell, m, - output logic [`NE+1:0] Qe + input logic [`NE-1:0] Xe, Ye, + input logic Sqrt, + input logic XZero, + input logic [`DIVBLEN:0] ell, m, + output logic [`NE+1:0] Qe ); logic [`NE-2:0] Bias; logic [`NE+1:0] SXExp; @@ -42,28 +42,28 @@ module fdivsqrtexpcalc( logic [`NE+1:0] DExp; if (`FPSIZES == 1) begin - assign Bias = (`NE-1)'(`BIAS); + assign Bias = (`NE-1)'(`BIAS); end else if (`FPSIZES == 2) begin - assign Bias = Fmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1); + assign Bias = Fmt ? (`NE-1)'(`BIAS) : (`NE-1)'(`BIAS1); end else if (`FPSIZES == 3) begin - always_comb - case (Fmt) - `FMT: Bias = (`NE-1)'(`BIAS); - `FMT1: Bias = (`NE-1)'(`BIAS1); - `FMT2: Bias = (`NE-1)'(`BIAS2); - default: Bias = 'x; - endcase + always_comb + case (Fmt) + `FMT: Bias = (`NE-1)'(`BIAS); + `FMT1: Bias = (`NE-1)'(`BIAS1); + `FMT2: Bias = (`NE-1)'(`BIAS2); + default: Bias = 'x; + endcase end else if (`FPSIZES == 4) begin - always_comb - case (Fmt) - 2'h3: Bias = (`NE-1)'(`Q_BIAS); - 2'h1: Bias = (`NE-1)'(`D_BIAS); - 2'h0: Bias = (`NE-1)'(`S_BIAS); - 2'h2: Bias = (`NE-1)'(`H_BIAS); - endcase + always_comb + case (Fmt) + 2'h3: Bias = (`NE-1)'(`Q_BIAS); + 2'h1: Bias = (`NE-1)'(`D_BIAS); + 2'h0: Bias = (`NE-1)'(`S_BIAS); + 2'h2: Bias = (`NE-1)'(`H_BIAS); + endcase end assign SXExp = {2'b0, Xe} - {{(`NE+1-`DIVBLEN){1'b0}}, ell} - (`NE+2)'(`BIAS); assign SExp = {SXExp[`NE+1], SXExp[`NE+1:1]} + {2'b0, Bias}; From 28dd41291a85b41cf1666890922a9c2db5ed4cf6 Mon Sep 17 00:00:00 2001 From: Limnanthes Serafini Date: Thu, 13 Apr 2023 21:02:30 -0700 Subject: [PATCH 31/40] More cleanup --- src/fpu/fdivsqrt/fdivsqrtfgen2.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtfgen4.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtfsm.sv | 34 ++++++++++++++-------------- src/fpu/fdivsqrt/fdivsqrtiter.sv | 8 +++---- src/fpu/fdivsqrt/fdivsqrtpostproc.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtqsel2.sv | 2 +- src/fpu/fdivsqrt/fdivsqrtstage4.sv | 6 ++--- src/fpu/fdivsqrt/fdivsqrtuotfc2.sv | 6 ++--- 8 files changed, 31 insertions(+), 31 deletions(-) diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv index 9c13a91da..250fb4fbd 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen2.sv @@ -29,7 +29,7 @@ `include "wally-config.vh" module fdivsqrtfgen2 ( - input logic up, uz, + input logic up, uz, input logic [`DIVb+3:0] C, U, UM, output logic [`DIVb+3:0] F ); diff --git a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv index 975d58ebd..a07e504f4 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfgen4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfgen4.sv @@ -29,7 +29,7 @@ `include "wally-config.vh" module fdivsqrtfgen4 ( - input logic [3:0] udigit, + input logic [3:0] udigit, input logic [`DIVb+3:0] C, U, UM, output logic [`DIVb+3:0] F ); diff --git a/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/src/fpu/fdivsqrt/fdivsqrtfsm.sv index 4cfede605..559e4b775 100644 --- a/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -29,24 +29,24 @@ `include "wally-config.vh" module fdivsqrtfsm( - input logic clk, - input logic reset, + input logic clk, + input logic reset, input logic [`FMTBITS-1:0] FmtE, - input logic XInfE, YInfE, - input logic XZeroE, YZeroE, - input logic XNaNE, YNaNE, - input logic FDivStartE, IDivStartE, - input logic XsE, - input logic SqrtE, - input logic StallM, - input logic FlushE, - input logic WZeroE, - input logic IntDivE, - input logic [`DIVBLEN:0] nE, - input logic ISpecialCaseE, - output logic IFDivStartE, - output logic FDivBusyE, FDivDoneE, - output logic SpecialCaseM + input logic XInfE, YInfE, + input logic XZeroE, YZeroE, + input logic XNaNE, YNaNE, + input logic FDivStartE, IDivStartE, + input logic XsE, + input logic SqrtE, + input logic StallM, + input logic FlushE, + input logic WZeroE, + input logic IntDivE, + input logic [`DIVBLEN:0] nE, + input logic ISpecialCaseE, + output logic IFDivStartE, + output logic FDivBusyE, FDivDoneE, + output logic SpecialCaseM ); typedef enum logic [1:0] {IDLE, BUSY, DONE} statetype; diff --git a/src/fpu/fdivsqrt/fdivsqrtiter.sv b/src/fpu/fdivsqrt/fdivsqrtiter.sv index 7de120eda..ec15423e4 100644 --- a/src/fpu/fdivsqrt/fdivsqrtiter.sv +++ b/src/fpu/fdivsqrt/fdivsqrtiter.sv @@ -29,10 +29,10 @@ `include "wally-config.vh" module fdivsqrtiter( - input logic clk, - input logic IFDivStartE, - input logic FDivBusyE, - input logic SqrtE, + input logic clk, + input logic IFDivStartE, + input logic FDivBusyE, + input logic SqrtE, input logic [`DIVb+3:0] X, input logic [`DIVb-1:0] DPreproc, output logic [`DIVb-1:0] D, diff --git a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv index 7b92f8c83..b8575f7fe 100644 --- a/src/fpu/fdivsqrt/fdivsqrtpostproc.sv +++ b/src/fpu/fdivsqrt/fdivsqrtpostproc.sv @@ -112,7 +112,7 @@ module fdivsqrtpostproc( // Select quotient or remainder and do normalization shift mux2 #(`DIVBLEN+1) normshiftmux(((`DIVBLEN+1)'(`DIVb) - (nM * (`DIVBLEN+1)'(`LOGR))), (mM + (`DIVBLEN+1)'(`DIVa)), RemOpM, NormShiftM); - mux2 #(`DIVb+4) presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM); + mux2 #(`DIVb+4) presresultmux(NormQuotM, NormRemM, RemOpM, PreResultM); assign PreIntResultM = $signed(PreResultM >>> NormShiftM); // special case logic diff --git a/src/fpu/fdivsqrt/fdivsqrtqsel2.sv b/src/fpu/fdivsqrt/fdivsqrtqsel2.sv index fd0a2a469..18c577b97 100644 --- a/src/fpu/fdivsqrt/fdivsqrtqsel2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtqsel2.sv @@ -30,7 +30,7 @@ module fdivsqrtqsel2 ( input logic [3:0] ps, pc, - output logic up, uz, un + output logic up, uz, un ); logic [3:0] p, g; diff --git a/src/fpu/fdivsqrt/fdivsqrtstage4.sv b/src/fpu/fdivsqrt/fdivsqrtstage4.sv index ee92d263b..f2ff3734b 100644 --- a/src/fpu/fdivsqrt/fdivsqrtstage4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtstage4.sv @@ -31,7 +31,7 @@ module fdivsqrtstage4 ( input logic [`DIVb-1:0] D, input logic [`DIVb+3:0] DBar, D2, DBar2, - input logic [`DIVb:0] U,UM, + input logic [`DIVb:0] U,UM, input logic [`DIVb+3:0] WS, WC, input logic [`DIVb+1:0] C, input logic SqrtE, j1, @@ -58,8 +58,8 @@ module fdivsqrtstage4 ( // 0000 = 0 // 0010 = -1 // 0001 = -2 - assign Smsbs = U[`DIVb:`DIVb-4]; - assign Dmsbs = D[`DIVb-1:`DIVb-3]; + assign Smsbs = U[`DIVb:`DIVb-4]; + assign Dmsbs = D[`DIVb-1:`DIVb-3]; assign WCmsbs = WC[`DIVb+3:`DIVb-4]; assign WSmsbs = WS[`DIVb+3:`DIVb-4]; diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv index 65b8940ac..33956a0fd 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuotfc2.sv @@ -32,10 +32,10 @@ // Unified OTFC, Radix 2 // /////////////////////////////// module fdivsqrtuotfc2( - input logic up, un, + input logic up, un, input logic [`DIVb+1:0] C, - input logic [`DIVb:0] U, UM, - output logic [`DIVb:0] UNext, UMNext + input logic [`DIVb:0] U, UM, + output logic [`DIVb:0] UNext, UMNext ); // The on-the-fly converter transfers the divsqrt // bits to the quotient as they come. From 95223bf11c3b40b8b700958df145376c61e47065 Mon Sep 17 00:00:00 2001 From: Limnanthes Serafini Date: Thu, 13 Apr 2023 21:34:50 -0700 Subject: [PATCH 32/40] More cleanup --- src/fpu/fdivsqrt/fdivsqrtuotfc4.sv | 2 +- src/generic/lzc.sv | 2 +- src/generic/onehotdecoder.sv | 2 +- src/hazard/hazard.sv | 14 +++++++------- src/ieu/bmu/byte.sv | 2 +- src/ieu/bmu/cnt.sv | 4 ++-- src/ieu/bmu/ext.sv | 2 +- src/ieu/bmu/popcnt.sv | 2 +- src/ieu/ieu.sv | 2 +- src/ieu/shifter.sv | 6 +++--- src/ifu/bpred/bpred.sv | 26 +++++++++++++------------- src/ifu/bpred/btb.sv | 22 +++++++++++----------- 12 files changed, 43 insertions(+), 43 deletions(-) diff --git a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv index a1416384b..57298b4c8 100644 --- a/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv +++ b/src/fpu/fdivsqrt/fdivsqrtuotfc4.sv @@ -29,7 +29,7 @@ `include "wally-config.vh" module fdivsqrtuotfc4( - input logic [3:0] udigit, + input logic [3:0] udigit, input logic [`DIVb:0] U, UM, input logic [`DIVb:0] C, output logic [`DIVb:0] UNext, UMNext diff --git a/src/generic/lzc.sv b/src/generic/lzc.sv index 9b7c841b2..7314b29e9 100644 --- a/src/generic/lzc.sv +++ b/src/generic/lzc.sv @@ -24,7 +24,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module lzc #(parameter WIDTH = 1) ( - input logic [WIDTH-1:0] num, // number to count the leading zeroes of + input logic [WIDTH-1:0] num, // number to count the leading zeroes of output logic [$clog2(WIDTH+1)-1:0] ZeroCnt // the number of leading zeroes ); diff --git a/src/generic/onehotdecoder.sv b/src/generic/onehotdecoder.sv index 6334e91f8..5e8f01c26 100644 --- a/src/generic/onehotdecoder.sv +++ b/src/generic/onehotdecoder.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// oneHotDecoder.sv +// onehotdecoder.sv // // Written: ross1728@gmail.com July 09, 2021 // Modified: diff --git a/src/hazard/hazard.sv b/src/hazard/hazard.sv index 224ff8b37..51f2ccf40 100644 --- a/src/hazard/hazard.sv +++ b/src/hazard/hazard.sv @@ -30,13 +30,13 @@ module hazard ( // Detect hazards - input logic BPWrongE, CSRWriteFenceM, RetM, TrapM, - input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD, - input logic LSUStallM, IFUStallF, - input logic FCvtIntStallD, FPUStallD, - input logic DivBusyE, FDivBusyE, - input logic EcallFaultM, BreakpointFaultM, - input logic wfiM, IntPendingM, + input logic BPWrongE, CSRWriteFenceM, RetM, TrapM, + input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD, + input logic LSUStallM, IFUStallF, + input logic FCvtIntStallD, FPUStallD, + input logic DivBusyE, FDivBusyE, + input logic EcallFaultM, BreakpointFaultM, + input logic wfiM, IntPendingM, // Stall & flush outputs output logic StallF, StallD, StallE, StallM, StallW, output logic FlushD, FlushE, FlushM, FlushW diff --git a/src/ieu/bmu/byte.sv b/src/ieu/bmu/byte.sv index db7a3b45c..32031059a 100644 --- a/src/ieu/bmu/byte.sv +++ b/src/ieu/bmu/byte.sv @@ -31,7 +31,7 @@ module byteUnit #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, // Operands - input logic ByteSelect, // LSB of Immediate + input logic ByteSelect, // LSB of Immediate output logic [WIDTH-1:0] ByteResult); // rev8, orcb result logic [WIDTH-1:0] OrcBResult, Rev8Result; diff --git a/src/ieu/bmu/cnt.sv b/src/ieu/bmu/cnt.sv index 75ace3ac7..a1f82eb7e 100644 --- a/src/ieu/bmu/cnt.sv +++ b/src/ieu/bmu/cnt.sv @@ -32,8 +32,8 @@ module cnt #(parameter WIDTH = 32) ( input logic [WIDTH-1:0] A, RevA, // Operands - input logic [1:0] B, // Last 2 bits of immediate - input logic W64, // Indicates word operation + input logic [1:0] B, // Last 2 bits of immediate + input logic W64, // Indicates word operation output logic [WIDTH-1:0] CntResult // count result ); diff --git a/src/ieu/bmu/ext.sv b/src/ieu/bmu/ext.sv index 12e690436..438addaa8 100644 --- a/src/ieu/bmu/ext.sv +++ b/src/ieu/bmu/ext.sv @@ -32,7 +32,7 @@ module ext #(parameter WIDTH = 32) ( input logic [WIDTH-1:0] A, // Operands - input logic [1:0] ExtSelect, // B[2], B[0] of immediate + input logic [1:0] ExtSelect, // B[2], B[0] of immediate output logic [WIDTH-1:0] ExtResult); // Extend Result logic [WIDTH-1:0] sexthResult, zexthResult, sextbResult; diff --git a/src/ieu/bmu/popcnt.sv b/src/ieu/bmu/popcnt.sv index 8732f29f2..7701c0d65 100644 --- a/src/ieu/bmu/popcnt.sv +++ b/src/ieu/bmu/popcnt.sv @@ -27,7 +27,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module popcnt #(parameter WIDTH = 32) ( - input logic [WIDTH-1:0] num, // number to count total ones + input logic [WIDTH-1:0] num, // number to count total ones output logic [$clog2(WIDTH):0] PopCnt // the total number of ones ); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index d5b3e8f40..02fa1dd7c 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -29,7 +29,7 @@ `include "wally-config.vh" module ieu ( - input logic clk, reset, + input logic clk, reset, // Decode stage signals input logic [31:0] InstrD, // Instruction input logic IllegalIEUFPUInstrD, // Illegal instruction diff --git a/src/ieu/shifter.sv b/src/ieu/shifter.sv index 5227ee3bd..11ae1cf0a 100644 --- a/src/ieu/shifter.sv +++ b/src/ieu/shifter.sv @@ -35,9 +35,9 @@ module shifter ( input logic Right, Rotate, W64, SubArith, // Shift right, rotate, W64-type operation, arithmetic shift output logic [`XLEN-1:0] Y); // Shifted result - logic [2*`XLEN-2:0] Z, ZShift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits - logic [`LOG_XLEN-1:0] TruncAmt, Offset; // Shift amount adjusted for RV64, right-shift amount - logic Sign; // Sign bit for sign extension + logic [2*`XLEN-2:0] Z, ZShift; // Input to funnel shifter, shifted amount before truncated to 32 or 64 bits + logic [`LOG_XLEN-1:0] TruncAmt, Offset; // Shift amount adjusted for RV64, right-shift amount + logic Sign; // Sign bit for sign extension assign Sign = A[`XLEN-1] & SubArith; // sign bit for sign extension if (`XLEN==32) begin // rv32 diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index e74d19870..881150b3f 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -48,25 +48,25 @@ module bpred ( input logic [`XLEN-1:0] PCE, // Execution stage instruction address input logic [`XLEN-1:0] PCM, // Memory stage instruction address - input logic [31:0] PostSpillInstrRawF, // Instruction + input logic [31:0] PostSpillInstrRawF, // Instruction // Branch and jump outcome - input logic InstrValidD, InstrValidE, + input logic InstrValidD, InstrValidE, input logic BranchD, BranchE, input logic JumpD, JumpE, - input logic PCSrcE, // Executation stage branch is taken - input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address - input logic [`XLEN-1:0] IEUAdrM, // The branch/jump target address - input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) + input logic PCSrcE, // Executation stage branch is taken + input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address + input logic [`XLEN-1:0] IEUAdrM, // The branch/jump target address + input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address) output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as call, return, jr (not return), j, br // Report branch prediction status - output logic BPWrongE, // Prediction is wrong - output logic BPWrongM, // Prediction is wrong + output logic BPWrongE, // Prediction is wrong + output logic BPWrongM, // Prediction is wrong output logic BPDirPredWrongM, // Prediction direction is wrong - output logic BTAWrongM, // Prediction target wrong + output logic BTAWrongM, // Prediction target wrong output logic RASPredPCWrongM, // RAS prediction is wrong - output logic IClassWrongM // Class prediction is wrong + output logic IClassWrongM // Class prediction is wrong ); logic [1:0] BPDirPredF; @@ -187,7 +187,7 @@ module bpred ( // Correct branch/jump target. mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE); - // If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE. + // If the fence/csrw was predicted as a taken branch then we select PCF, rather than PCE. // Effectively this is PCM+4 or the non-existant PCLinkM if(`INSTR_CLASS_PRED) mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPWrongM, NextValidPCE); else assign NextValidPCE = PCE; @@ -201,11 +201,11 @@ module bpred ( // 3. target ras (ras target wrong / class[2]) // 4. direction (br dir wrong / class[0]) - // Unforuantely we can't use PCD to infer the correctness of the BTB or RAS because the class prediction + // Unfortunately we can't use PCD to infer the correctness of the BTB or RAS because the class prediction // could be wrong or the fall through address selected for branch predict not taken. // By pipeline the BTB's PC and RAS address through the pipeline we can measure the accuracy of // both without the above inaccuracies. - // **** use BPBTAWrongM from BTB. + // **** use BPBTAWrongM from BTB. assign BTAWrongE = (BPBTAE != IEUAdrE) & (BranchE | JumpE & ~ReturnE) & PCSrcE; assign RASPredPCWrongE = (RASPCE != IEUAdrE) & ReturnE & PCSrcE; diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index 90246e0ea..2689b4128 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -1,7 +1,7 @@ /////////////////////////////////////////// // btb.sv // -// Written: Ross Thomposn ross1728@gmail.com +// Written: Ross Thompson ross1728@gmail.com // Created: February 15, 2021 // Modified: 24 January 2023 // @@ -34,19 +34,19 @@ module btb #(parameter Depth = 10 ) ( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, FlushD, FlushE, FlushM, FlushW, - input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,// PC at various stages - output logic [`XLEN-1:0] BPBTAF, // BTB's guess at PC + input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, // PC at various stages + output logic [`XLEN-1:0] BPBTAF, // BTB's guess at PC output logic [`XLEN-1:0] BPBTAD, output logic [`XLEN-1:0] BPBTAE, - output logic [3:0] BTBIClassF, // BTB's guess at instruction class + output logic [3:0] BTBIClassF, // BTB's guess at instruction class // update - input logic IClassWrongM, // BTB's instruction class guess was wrong + input logic IClassWrongM, // BTB's instruction class guess was wrong input logic IClassWrongE, - input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb - input logic [`XLEN-1:0] IEUAdrM, // Branch/jump target address to insert into btb - input logic [3:0] InstrClassD, // Instruction class to insert into btb - input logic [3:0] InstrClassE, // Instruction class to insert into btb - input logic [3:0] InstrClassM, // Instruction class to insert into btb + input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb + input logic [`XLEN-1:0] IEUAdrM, // Branch/jump target address to insert into btb + input logic [3:0] InstrClassD, // Instruction class to insert into btb + input logic [3:0] InstrClassE, // Instruction class to insert into btb + input logic [3:0] InstrClassM, // Instruction class to insert into btb input logic [3:0] InstrClassW ); @@ -73,7 +73,7 @@ module btb #(parameter Depth = 10 ) ( // must output a valid PC and valid bit during reset. Because only PCF, not PCNextF is reset, PCNextF is invalid // during reset. The BTB must produce a non X PC1NextF to allow the simulation to run. - // While thie mux could be included in IFU it is not necessary for the IROM/I$/bus. + // While the mux could be included in IFU it is not necessary for the IROM/I$/bus. // For now it is optimal to leave it here. assign ResetPC = `RESET_VECTOR; assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]}; From 23dbca399184718596375da56b6006f254c2cef7 Mon Sep 17 00:00:00 2001 From: Dygore Date: Fri, 14 Apr 2023 00:33:53 -0500 Subject: [PATCH 33/40] Added tests for full coverage of the FPU result sign module --- tests/coverage/fpu.S | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index 9c8f3d344..d377d47d6 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -32,10 +32,19 @@ main: csrs mstatus, t0 #Pull denormalized FP number from memory and pass it to fclass.S for coverage - la t0, TestData + la t0, TestData1 flw ft0, 0(t0) fclass.s t1, ft0 + #Result Sign Test Coverage + la t0, TestData2 + flw ft0, 0(t0) + flw ft1, 4(t0) + fadd.s ft2, ft0, ft1 #Adds coverage for inf as arg for FADD + + flw ft2, 4(t0) + fmsub.s ft3, ft0, ft1, ft2 #Adds coverage for fmaAs or Z Sign Bit + # Test legal instructions not covered elsewhere flq ft0, 0(a0) flh ft0, 8(a0) @@ -105,5 +114,8 @@ main: .section .data .align 3 -TestData: -.int 0x00100000 #Denormalized FP number \ No newline at end of file +TestData1: +.int 0x00100000 #Denormalized FP number +TestData2: +.word 0x60000001 #Random FP Number (Pos) +.word 0x7f800000 #INF \ No newline at end of file From 92a0827d80a74f28d9c98885558726aff2ef8676 Mon Sep 17 00:00:00 2001 From: Dygore Date: Fri, 14 Apr 2023 14:40:55 -0500 Subject: [PATCH 34/40] Added multiple tests to increase FPU coverage --- tests/coverage/fpu.S | 31 +++++++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/tests/coverage/fpu.S b/tests/coverage/fpu.S index d377d47d6..b2a52be06 100644 --- a/tests/coverage/fpu.S +++ b/tests/coverage/fpu.S @@ -45,6 +45,30 @@ main: flw ft2, 4(t0) fmsub.s ft3, ft0, ft1, ft2 #Adds coverage for fmaAs or Z Sign Bit + #Adds Coverage for Flag fmaAs, fmaPs, YSNaN, ZSNaN + fmadd.s ft3, ft0, ft1, ft2 + + flw ft0, 8(t0) + fmadd.s ft3, ft0, ft1, ft2 + + flw ft1, 12(t0) + fmadd.s ft3, ft0, ft1, ft2 + + flw ft2, 12(t0) + flw ft1, 4(t0) + fmadd.s ft3, ft0, ft1, ft2 + + #Add Coverage for round lsbRes + flw ft0, 16(t0) + flw ft1, 4(t0) + fmadd.s ft3, ft0, ft1, ft2 + + #Fix BadNaNBox test on unpackinput Z + la t0, TestData2 + flw ft3, 0(t0) + flw ft4, 0(t0) + fadd.s ft5, ft3, ft4 + # Test legal instructions not covered elsewhere flq ft0, 0(a0) flh ft0, 8(a0) @@ -117,5 +141,8 @@ main: TestData1: .int 0x00100000 #Denormalized FP number TestData2: -.word 0x60000001 #Random FP Number (Pos) -.word 0x7f800000 #INF \ No newline at end of file +.int 0x3f800000 #FP 1.0 +.word 0x7f800000 #INF +.int 0xbf800000 #FP -1.0 +.int 0x7fa00000 #SNaN +.int 0x3fffffff #OverFlow Test \ No newline at end of file From 34aedc4f798c05116f164c5213762849aab06630 Mon Sep 17 00:00:00 2001 From: Limnanthes Serafini Date: Fri, 14 Apr 2023 14:14:34 -0700 Subject: [PATCH 35/40] indent fix --- src/generic/lzc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/generic/lzc.sv b/src/generic/lzc.sv index 7314b29e9..daf2bf077 100644 --- a/src/generic/lzc.sv +++ b/src/generic/lzc.sv @@ -24,7 +24,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module lzc #(parameter WIDTH = 1) ( - input logic [WIDTH-1:0] num, // number to count the leading zeroes of + input logic [WIDTH-1:0] num, // number to count the leading zeroes of output logic [$clog2(WIDTH+1)-1:0] ZeroCnt // the number of leading zeroes ); From 5952a4b0a30313a786b826c211535ac5772a9d12 Mon Sep 17 00:00:00 2001 From: Limnanthes Serafini Date: Fri, 14 Apr 2023 14:15:52 -0700 Subject: [PATCH 36/40] Final small fix --- src/generic/lzc.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/generic/lzc.sv b/src/generic/lzc.sv index daf2bf077..aa5381a22 100644 --- a/src/generic/lzc.sv +++ b/src/generic/lzc.sv @@ -24,7 +24,7 @@ //////////////////////////////////////////////////////////////////////////////////////////////// module lzc #(parameter WIDTH = 1) ( - input logic [WIDTH-1:0] num, // number to count the leading zeroes of + input logic [WIDTH-1:0] num, // number to count the leading zeroes of output logic [$clog2(WIDTH+1)-1:0] ZeroCnt // the number of leading zeroes ); From 862d1e01163611ec5337bc471cda4b5a450de47b Mon Sep 17 00:00:00 2001 From: Alec Vercruysse Date: Fri, 14 Apr 2023 16:54:55 -0700 Subject: [PATCH 37/40] replace instances of code duplication for i$ exclusions w/commands --- sim/coverage-exclusions-rv64gc.do | 11 +++++++++++ src/cache/cache.sv | 28 +++++++++------------------- src/cache/cacheway.sv | 20 ++++---------------- src/generic/mux.sv | 2 +- 4 files changed, 25 insertions(+), 36 deletions(-) diff --git a/sim/coverage-exclusions-rv64gc.do b/sim/coverage-exclusions-rv64gc.do index eb10505eb..374c4b917 100644 --- a/sim/coverage-exclusions-rv64gc.do +++ b/sim/coverage-exclusions-rv64gc.do @@ -62,6 +62,17 @@ coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange $sta coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheBusW"] coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache SelAdrCauses"] -item e 1 -fecexprrow 4 10 coverage exclude -scope /dut/core/ifu/bus/icache/icache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: icache CacheBusRCauses"] -item e 1 -fecexprrow 1-2 12 +# cache.sv AdrSelMux and CacheBusAdrMux, excluding unhit Flush branch +coverage exclude -scope /dut/core/ifu/bus/icache/icache/AdrSelMux -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1 +coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheBusAdrMux -linerange [GetLineNum ../src/generic/mux.sv "exclusion-tag: mux3"] -item b 1 3 +# CacheWay Dirty logic. -scope does not accept wildcards. +set numcacheways 4 +for {set i 0} {$i < $numcacheways} {incr i} { + coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetDirtyWay"] -item e 1 + coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SelectedWiteWordEn"] -item e 1 -fecexprrow 4 6 + # below: flushD can't go high during an icache write b/c of pipeline stall + coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetValidEN"] -item e 1 -fecexprrow 4 +} ###################### # Toggle exclusions diff --git a/src/cache/cache.sv b/src/cache/cache.sv index ea7504f23..57ff20ab3 100644 --- a/src/cache/cache.sv +++ b/src/cache/cache.sv @@ -73,6 +73,7 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE logic SelAdr; + logic [1:0] AdrSelMuxSel; logic [SETLEN-1:0] CacheSet; logic [LINELEN-1:0] LineWriteData; logic ClearDirty, SetDirty, SetValid; @@ -108,18 +109,10 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE // and FlushAdr when handling D$ flushes // The icache must update to the newest PCNextF on flush as it is probably a trap. Trap // sets PCNextF to XTVEC and the icache must start reading the instruction. - if (!READ_ONLY_CACHE) begin - logic [1:0] AdrSelMuxSel; - assign AdrSelMuxSel = {SelFlush, SelAdr | SelHPTW}; - mux3 #(SETLEN) AdrSelMux(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr, + assign AdrSelMuxSel = {SelFlush, ((SelAdr | SelHPTW) & ~((READ_ONLY_CACHE == 1) & FlushStage))}; + mux3 #(SETLEN) AdrSelMux(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], FlushAdr, AdrSelMuxSel, CacheSet); - end - else begin - logic AdrSelMuxSel; - assign AdrSelMuxSel = ((SelAdr | SelHPTW) & ~FlushStage); - mux2 #(SETLEN) AdrSelMux(NextSet[SETTOP-1:OFFSETLEN], PAdr[SETTOP-1:OFFSETLEN], - AdrSelMuxSel, CacheSet); - end + // Array of cache ways, along with victim, hit, dirty, and read merging logic cacheway #(NUMLINES, LINELEN, TAGLEN, OFFSETLEN, SETLEN, READ_ONLY_CACHE) CacheWays[NUMWAYS-1:0]( .clk, .reset, .CacheEn, .CacheSet, .PAdr, .LineWriteData, .LineByteMask, @@ -159,14 +152,11 @@ module cache #(parameter LINELEN, NUMLINES, NUMWAYS, LOGBWPL, WORDLEN, MUXINTE .PAdr(WordOffsetAddr), .ReadDataLine, .ReadDataWord); // Bus address for fetch, writeback, or flush writeback - if (!READ_ONLY_CACHE) - mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), - .d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), - .d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}), - .s({SelFlush, SelWriteback}), .y(CacheBusAdr)); - else - assign CacheBusAdr = {PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}; - + mux3 #(`PA_BITS) CacheBusAdrMux(.d0({PAdr[`PA_BITS-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), + .d1({Tag, PAdr[SETTOP-1:OFFSETLEN], {OFFSETLEN{1'b0}}}), + .d2({Tag, FlushAdr, {OFFSETLEN{1'b0}}}), + .s({SelFlush, SelWriteback}), .y(CacheBusAdr)); + ///////////////////////////////////////////////////////////////////////////////////////////// // Write Path ///////////////////////////////////////////////////////////////////////////////////////////// diff --git a/src/cache/cacheway.sv b/src/cache/cacheway.sv index 106905939..77e844b20 100644 --- a/src/cache/cacheway.sv +++ b/src/cache/cacheway.sv @@ -97,22 +97,10 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26, ///////////////////////////////////////////////////////////////////////////////////////////// assign SetValidWay = SetValid & SelData; - if (!READ_ONLY_CACHE) begin - assign SetDirtyWay = SetDirty & SelData; - assign ClearDirtyWay = ClearDirty & SelData; - assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage; - assign SetValidEN = SetValidWay & ~FlushStage; - end - else begin - // Don't cover FlushStage assertion during SetValidWay. - // it's not explicitely gated anywhere, but for read-only caches, - // there's no way that a FlushD can happen during the write stage - // of a fetch. - // coverage off -item e 1 -fecexprrow 4 - assign SelectedWriteWordEn = SetValidWay & ~FlushStage; - // coverage off -item e 1 -fecexprrow 4 - assign SetValidEN = SetValidWay & ~FlushStage; - end + assign SetDirtyWay = SetDirty & SelData; // exclusion-tag: icache SetDirtyWay + assign ClearDirtyWay = ClearDirty & SelData; + assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage; // exclusion-tag: icache SelectedWiteWordEn + assign SetValidEN = SetValidWay & ~FlushStage; // exclusion-tag: icache SetValidEN // If writing the whole line set all write enables to 1, else only set the correct word. assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR diff --git a/src/generic/mux.sv b/src/generic/mux.sv index 636c19c9f..223d41afc 100644 --- a/src/generic/mux.sv +++ b/src/generic/mux.sv @@ -40,7 +40,7 @@ module mux3 #(parameter WIDTH = 8) ( input logic [1:0] s, output logic [WIDTH-1:0] y); - assign y = s[1] ? d2 : (s[0] ? d1 : d0); + assign y = s[1] ? d2 : (s[0] ? d1 : d0); // exclusion-tag: mux3 endmodule module mux4 #(parameter WIDTH = 8) ( From 34dd481f93b222d5835e4e9b8732272727432d02 Mon Sep 17 00:00:00 2001 From: Diego Herrera Vicioso Date: Sat, 15 Apr 2023 23:13:39 -0700 Subject: [PATCH 38/40] Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc --- src/privileged/csrsr.sv | 3 +++ src/privileged/trap.sv | 3 +++ tests/coverage/priv.S | 59 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 65 insertions(+) diff --git a/src/privileged/csrsr.sv b/src/privileged/csrsr.sv index 94c72a134..60968a68b 100644 --- a/src/privileged/csrsr.sv +++ b/src/privileged/csrsr.sv @@ -198,9 +198,12 @@ module csrsr ( STATUS_UBE <= #1 CSRWriteValM[6] & `U_SUPPORTED & `BIGENDIAN_SUPPORTED; STATUS_MBE <= #1 nextMBE; STATUS_SBE <= #1 nextSBE; + // coverage off + // MSTATUSH only exists in 32-bit configurations, will not be hit on rv64gc end else if (WriteMSTATUSHM) begin STATUS_MBE <= #1 CSRWriteValM[5] & `BIGENDIAN_SUPPORTED; STATUS_SBE <= #1 CSRWriteValM[4] & `S_SUPPORTED & `BIGENDIAN_SUPPORTED; + // coverage on end else if (WriteSSTATUSM) begin // write a subset of the STATUS bits STATUS_MXR_INT <= #1 CSRWriteValM[19]; STATUS_SUM_INT <= #1 CSRWriteValM[18]; diff --git a/src/privileged/trap.sv b/src/privileged/trap.sv index bc1f329df..96b404ef9 100644 --- a/src/privileged/trap.sv +++ b/src/privileged/trap.sv @@ -81,11 +81,14 @@ module trap ( /////////////////////////////////////////// assign BothInstrAccessFaultM = InstrAccessFaultM | HPTWInstrAccessFaultM; + // coverage off -item e 1 -fecexprrow 2 + // excludes InstrMisalignedFaultM from coverage of this line, since misaligned instructions cannot occur in rv64gc. assign ExceptionM = InstrMisalignedFaultM | BothInstrAccessFaultM | IllegalInstrFaultM | LoadMisalignedFaultM | StoreAmoMisalignedFaultM | InstrPageFaultM | LoadPageFaultM | StoreAmoPageFaultM | BreakpointFaultM | EcallFaultM | LoadAccessFaultM | StoreAmoAccessFaultM; + // coverage on assign TrapM = ExceptionM | InterruptM; assign RetM = mretM | sretM; diff --git a/tests/coverage/priv.S b/tests/coverage/priv.S index 6ab5951b4..94b7cd0ef 100644 --- a/tests/coverage/priv.S +++ b/tests/coverage/priv.S @@ -142,6 +142,65 @@ main: # Test writes to floating point CSRs csrw frm, t0 csrw fflags, t0 + + # CSRC MCOUNTEREN Register + # Go to machine mode + li a0, 3 + ecall + # Activate HPM3 + li t0, -1 + csrw mcounteren, t0 + csrw scounteren, t0 + + # Go to supervisor + li a0, 1 + ecall + #try to write to HPMs + csrw 333, t0 + #go to user mode + li a0, 0 + ecall + csrr t0, hpmcounter22 + + # setting registers bits to 0 + li a0, 3 # back to machine mode + ecall + li t0, 0 + csrw mcounteren, t0 + csrw scounteren, t0 + + # Write to satp when status.TVM is 1 from machine mode + bseti t0, zero, 20 + csrs mstatus, t0 + + csrw satp, t0 + + + + # Test checking privilege for reading counters (using counter 22 as an example) + + # Go to machine mode + li a0, 3 + ecall + + # Set SCOUNTEREN to all 0s, MCOUNTEREN to all 1s + li t0, 0 + csrw scounteren, t0 + li t1, -1 + csrw mcounteren, t1 + + # Go to supervisor mode + li a0, 1 + ecall + + # try to read from HPM22 + csrr t0, hpmcounter22 + + # go to user mode + li a0, 0 + ecall + + csrr t0, hpmcounter22 j done From d327ed494ac1b081b4d036d21d9529e06f026eaf Mon Sep 17 00:00:00 2001 From: David Harris Date: Mon, 17 Apr 2023 10:18:06 -0700 Subject: [PATCH 39/40] Started DV Test Plan --- docs/testplans/testplan.md | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 docs/testplans/testplan.md diff --git a/docs/testplans/testplan.md b/docs/testplans/testplan.md new file mode 100644 index 000000000..a25b3a189 --- /dev/null +++ b/docs/testplans/testplan.md @@ -0,0 +1,29 @@ +# CORE-V Wally Test Plan + +CORE-V Wally is tested in the following ways: + +* Run [RISC-V Architecture Compatibility Tests](https://github.com/riscv-non-isa/riscv-arch-test) in lock-step against the ImperasDV reference model. +* Run custom tests to cover virtual memory, PMP, privileged unit, and peripherals in lock step against ImperasDV. +* ***pending: Run random tests generated by risc-dv +* Run CoreMark and Embench benchmarks. +* Run performance validation against reference models for the branch predictor and caches. +* Run the TestFloat suite against all precisions of all operations for the FPU unit. +* *** 83.5% coverage of statements, branches, expressions, and FSM states and transitions +* Boot Buildroot Linux in lock-step against ImperasDV. +* Boot Buildroot Linux on an FPGA and run programs. + +# Running Tests + +# + +# Detailed Test Plans + +The test plans for specific units are lined below: + +* Privileged Unit +* Memory Management Unit +* Peripherals +* Branch Predictor Performance Validation +* Cache Performance Validation + +Wally is described in an upcoming textbook, *RISC-V System-on-Chip Design*, by Harris, Stine, Thompson, and Harris. \ No newline at end of file From 4468086e067792c3243122d0d18776e52da883fc Mon Sep 17 00:00:00 2001 From: Mason Adams Date: Mon, 17 Apr 2023 14:13:26 -0500 Subject: [PATCH 40/40] Removed redundent expression to increase coverage --- src/fpu/postproc/round.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/fpu/postproc/round.sv b/src/fpu/postproc/round.sv index ee5a44751..c1914bb53 100644 --- a/src/fpu/postproc/round.sv +++ b/src/fpu/postproc/round.sv @@ -111,7 +111,7 @@ module round( // determine what format the final result is in: int or fp - assign IntRes = CvtOp & ToInt; + assign IntRes = ToInt; assign FpRes = ~IntRes; // sticky bit calculation @@ -328,4 +328,4 @@ module round( assign Re = FullRe[`NE-1:0]; -endmodule \ No newline at end of file +endmodule