From 1f791031424d7e701bd3ca37c255634d996ab91b Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 7 Dec 2023 11:13:56 -0800 Subject: [PATCH] division configurations --- config/rv32gc_2_1/config.vh | 189 +++++++++++++++++++++++++++++++++++ config/rv32gc_2_1i/config.vh | 189 +++++++++++++++++++++++++++++++++++ config/rv32gc_2_4/config.vh | 189 +++++++++++++++++++++++++++++++++++ config/rv32gc_2_4i/config.vh | 189 +++++++++++++++++++++++++++++++++++ config/rv32gc_4_1/config.vh | 189 +++++++++++++++++++++++++++++++++++ config/rv32gc_4_1i/config.vh | 189 +++++++++++++++++++++++++++++++++++ config/rv64gc_2_1/config.vh | 179 +++++++++++++++++++++++++++++++++ config/rv64gc_2_1i/config.vh | 179 +++++++++++++++++++++++++++++++++ config/rv64gc_2_4/config.vh | 179 +++++++++++++++++++++++++++++++++ config/rv64gc_2_4i/config.vh | 179 +++++++++++++++++++++++++++++++++ config/rv64gc_4_1/config.vh | 179 +++++++++++++++++++++++++++++++++ config/rv64gc_4_1i/config.vh | 179 +++++++++++++++++++++++++++++++++ sim/regression-wally | 115 +++++++++++++++++++++ testbench/testbench.sv | 33 ++++-- testbench/tests.vh | 98 +++++++++++++++++- 15 files changed, 2442 insertions(+), 12 deletions(-) create mode 100644 config/rv32gc_2_1/config.vh create mode 100644 config/rv32gc_2_1i/config.vh create mode 100644 config/rv32gc_2_4/config.vh create mode 100644 config/rv32gc_2_4i/config.vh create mode 100644 config/rv32gc_4_1/config.vh create mode 100644 config/rv32gc_4_1i/config.vh create mode 100644 config/rv64gc_2_1/config.vh create mode 100644 config/rv64gc_2_1i/config.vh create mode 100644 config/rv64gc_2_4/config.vh create mode 100644 config/rv64gc_2_4i/config.vh create mode 100644 config/rv64gc_4_1/config.vh create mode 100644 config/rv64gc_4_1i/config.vh diff --git a/config/rv32gc_2_1/config.vh b/config/rv32gc_2_1/config.vh new file mode 100644 index 000000000..652de2bb2 --- /dev/null +++ b/config/rv32gc_2_1/config.vh @@ -0,0 +1,189 @@ +////////////////////////////////////////// +// config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// include shared configuration +// `include "wally-shared.vh" +`include "BranchPredictorType.vh" + +// RV32 or RV64: XLEN = 32 or 64 +localparam XLEN = 32'd32; + +// IEEE 754 compliance +localparam IEEE754 = 0; + +localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5); +localparam ZICSR_SUPPORTED = 1; +localparam ZIFENCEI_SUPPORTED = 1; +localparam COUNTERS = 12'd32; +localparam ZICNTR_SUPPORTED = 1; +localparam ZIHPM_SUPPORTED = 1; +localparam ZFH_SUPPORTED = 0; +localparam SSTC_SUPPORTED = 1; +localparam ZICBOM_SUPPORTED = 1; +localparam ZICBOZ_SUPPORTED = 1; +localparam ZICBOP_SUPPORTED = 1; +localparam ZICCLSM_SUPPORTED = 0; +localparam SVPBMT_SUPPORTED = 0; +localparam SVNAPOT_SUPPORTED = 0; +localparam SVINVAL_SUPPORTED = 1; + +// LSU microarchitectural Features +localparam BUS_SUPPORTED = 1; +localparam DCACHE_SUPPORTED = 1; +localparam ICACHE_SUPPORTED = 1; +localparam VIRTMEM_SUPPORTED = 1; +localparam VECTORED_INTERRUPTS_SUPPORTED = 1; +localparam BIGENDIAN_SUPPORTED = 1; + +// TLB configuration. Entries should be a power of 2 +localparam ITLB_ENTRIES = 32'd32; +localparam DTLB_ENTRIES = 32'd32; + +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines +localparam DCACHE_NUMWAYS = 32'd4; +localparam DCACHE_WAYSIZEINBYTES = 32'd4096; +localparam DCACHE_LINELENINBITS = 32'd512; +localparam ICACHE_NUMWAYS = 32'd4; +localparam ICACHE_WAYSIZEINBYTES = 32'd4096; +localparam ICACHE_LINELENINBITS = 32'd512; + +// Integer Divider Configuration +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +localparam IDIV_BITSPERCYCLE = 32'd4; +localparam IDIV_ON_FPU = 1; + +// Legal number of PMP entries are 0, 16, or 64 +localparam PMP_ENTRIES = 32'd16; + +// Address space +localparam logic [63:0] RESET_VECTOR = 64'h80000000; + +// WFI Timeout Wait +localparam WFI_TIMEOUT_BIT = 32'd16; + +// Peripheral Addresses +// Peripheral memory space extends from BASE to BASE+RANGE +// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits +localparam DTIM_SUPPORTED = 1'b0; +localparam logic [63:0] DTIM_BASE = 64'h80000000; +localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; +localparam IROM_SUPPORTED = 1'b0; +localparam logic [63:0] IROM_BASE = 64'h80000000; +localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; +localparam BOOTROM_SUPPORTED = 1'b1; +localparam logic [63:0] BOOTROM_BASE = 64'h00001000; +localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; +localparam BOOTROM_PRELOAD = 1'b0; +localparam UNCORE_RAM_SUPPORTED = 1'b1; +localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; +localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; +localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam EXT_MEM_SUPPORTED = 1'b0; +localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; +localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; +localparam CLINT_SUPPORTED = 1'b1; +localparam logic [63:0] CLINT_BASE = 64'h02000000; +localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF; +localparam GPIO_SUPPORTED = 1'b1; +localparam logic [63:0] GPIO_BASE = 64'h10060000; +localparam logic [63:0] GPIO_RANGE = 64'h000000FF; +localparam UART_SUPPORTED = 1'b1; +localparam logic [63:0] UART_BASE = 64'h10000000; +localparam logic [63:0] UART_RANGE = 64'h00000007; +localparam PLIC_SUPPORTED = 1'b1; +localparam logic [63:0] PLIC_BASE = 64'h0C000000; +localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; +localparam SDC_SUPPORTED = 1'b0; +localparam logic [63:0] SDC_BASE = 64'h00013000; +localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam SPI_SUPPORTED = 1'b1; +localparam logic [63:0] SPI_BASE = 64'h10040000; +localparam logic [63:0] SPI_RANGE = 64'h00000FFF; + +// Bus Interface width +localparam AHBW = 32'd32; + +// Test modes + +// Tie GPIO outputs back to inputs +localparam GPIO_LOOPBACK_TEST = 1; +localparam SPI_LOOPBACK_TEST = 1; + +// Hardware configuration +localparam UART_PRESCALE = 32'd1; + +// Interrupt configuration +localparam PLIC_NUM_SRC = 32'd10; +// comment out the following if >=32 sources +localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); +localparam PLIC_GPIO_ID = 32'd3; +localparam PLIC_UART_ID = 32'd10; +localparam PLIC_SPI_ID = 32'd6; +localparam PLIC_SDC_ID = 32'd9; + +localparam BPRED_SUPPORTED = 1; +// this is an annoying hack for the branch predictor parameterization override. +`ifdef BPRED_OVERRIDE +localparam BPRED_TYPE = `BPRED_TYPE; +localparam BPRED_SIZE = `BPRED_SIZE; +`else +localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT +localparam BPRED_SIZE = 32'd10; +`endif +localparam BPRED_NUM_LHR = 32'd6; +`ifdef BTB_OVERRIDE +localparam BTB_SIZE = `BTB_SIZE; +localparam RAS_SIZE = `RAS_SIZE; +`else +localparam BTB_SIZE = 32'd10; +localparam RAS_SIZE = 32'd16; +`endif + +localparam SVADU_SUPPORTED = 1; +localparam ZMMUL_SUPPORTED = 0; + +// FPU division architecture +localparam RADIX = 32'd2; +localparam DIVCOPIES = 32'd1; + +// bit manipulation +localparam ZBA_SUPPORTED = 1; +localparam ZBB_SUPPORTED = 1; +localparam ZBC_SUPPORTED = 1; +localparam ZBS_SUPPORTED = 1; + +// New compressed instructions +localparam ZCB_SUPPORTED = 1; +localparam ZCA_SUPPORTED = 0; +localparam ZCF_SUPPORTED = 0; +localparam ZCD_SUPPORTED = 0; + +// Memory synthesis configuration +localparam USE_SRAM = 0; + +`include "config-shared.vh" diff --git a/config/rv32gc_2_1i/config.vh b/config/rv32gc_2_1i/config.vh new file mode 100644 index 000000000..47ebfb88f --- /dev/null +++ b/config/rv32gc_2_1i/config.vh @@ -0,0 +1,189 @@ +////////////////////////////////////////// +// config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// include shared configuration +// `include "wally-shared.vh" +`include "BranchPredictorType.vh" + +// RV32 or RV64: XLEN = 32 or 64 +localparam XLEN = 32'd32; + +// IEEE 754 compliance +localparam IEEE754 = 0; + +localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5); +localparam ZICSR_SUPPORTED = 1; +localparam ZIFENCEI_SUPPORTED = 1; +localparam COUNTERS = 12'd32; +localparam ZICNTR_SUPPORTED = 1; +localparam ZIHPM_SUPPORTED = 1; +localparam ZFH_SUPPORTED = 0; +localparam SSTC_SUPPORTED = 1; +localparam ZICBOM_SUPPORTED = 1; +localparam ZICBOZ_SUPPORTED = 1; +localparam ZICBOP_SUPPORTED = 1; +localparam ZICCLSM_SUPPORTED = 0; +localparam SVPBMT_SUPPORTED = 0; +localparam SVNAPOT_SUPPORTED = 0; +localparam SVINVAL_SUPPORTED = 1; + +// LSU microarchitectural Features +localparam BUS_SUPPORTED = 1; +localparam DCACHE_SUPPORTED = 1; +localparam ICACHE_SUPPORTED = 1; +localparam VIRTMEM_SUPPORTED = 1; +localparam VECTORED_INTERRUPTS_SUPPORTED = 1; +localparam BIGENDIAN_SUPPORTED = 1; + +// TLB configuration. Entries should be a power of 2 +localparam ITLB_ENTRIES = 32'd32; +localparam DTLB_ENTRIES = 32'd32; + +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines +localparam DCACHE_NUMWAYS = 32'd4; +localparam DCACHE_WAYSIZEINBYTES = 32'd4096; +localparam DCACHE_LINELENINBITS = 32'd512; +localparam ICACHE_NUMWAYS = 32'd4; +localparam ICACHE_WAYSIZEINBYTES = 32'd4096; +localparam ICACHE_LINELENINBITS = 32'd512; + +// Integer Divider Configuration +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +localparam IDIV_BITSPERCYCLE = 32'd4; +localparam IDIV_ON_FPU = 0; + +// Legal number of PMP entries are 0, 16, or 64 +localparam PMP_ENTRIES = 32'd16; + +// Address space +localparam logic [63:0] RESET_VECTOR = 64'h80000000; + +// WFI Timeout Wait +localparam WFI_TIMEOUT_BIT = 32'd16; + +// Peripheral Addresses +// Peripheral memory space extends from BASE to BASE+RANGE +// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits +localparam DTIM_SUPPORTED = 1'b0; +localparam logic [63:0] DTIM_BASE = 64'h80000000; +localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; +localparam IROM_SUPPORTED = 1'b0; +localparam logic [63:0] IROM_BASE = 64'h80000000; +localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; +localparam BOOTROM_SUPPORTED = 1'b1; +localparam logic [63:0] BOOTROM_BASE = 64'h00001000; +localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; +localparam BOOTROM_PRELOAD = 1'b0; +localparam UNCORE_RAM_SUPPORTED = 1'b1; +localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; +localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; +localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam EXT_MEM_SUPPORTED = 1'b0; +localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; +localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; +localparam CLINT_SUPPORTED = 1'b1; +localparam logic [63:0] CLINT_BASE = 64'h02000000; +localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF; +localparam GPIO_SUPPORTED = 1'b1; +localparam logic [63:0] GPIO_BASE = 64'h10060000; +localparam logic [63:0] GPIO_RANGE = 64'h000000FF; +localparam UART_SUPPORTED = 1'b1; +localparam logic [63:0] UART_BASE = 64'h10000000; +localparam logic [63:0] UART_RANGE = 64'h00000007; +localparam PLIC_SUPPORTED = 1'b1; +localparam logic [63:0] PLIC_BASE = 64'h0C000000; +localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; +localparam SDC_SUPPORTED = 1'b0; +localparam logic [63:0] SDC_BASE = 64'h00013000; +localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam SPI_SUPPORTED = 1'b1; +localparam logic [63:0] SPI_BASE = 64'h10040000; +localparam logic [63:0] SPI_RANGE = 64'h00000FFF; + +// Bus Interface width +localparam AHBW = 32'd32; + +// Test modes + +// Tie GPIO outputs back to inputs +localparam GPIO_LOOPBACK_TEST = 1; +localparam SPI_LOOPBACK_TEST = 1; + +// Hardware configuration +localparam UART_PRESCALE = 32'd1; + +// Interrupt configuration +localparam PLIC_NUM_SRC = 32'd10; +// comment out the following if >=32 sources +localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); +localparam PLIC_GPIO_ID = 32'd3; +localparam PLIC_UART_ID = 32'd10; +localparam PLIC_SPI_ID = 32'd6; +localparam PLIC_SDC_ID = 32'd9; + +localparam BPRED_SUPPORTED = 1; +// this is an annoying hack for the branch predictor parameterization override. +`ifdef BPRED_OVERRIDE +localparam BPRED_TYPE = `BPRED_TYPE; +localparam BPRED_SIZE = `BPRED_SIZE; +`else +localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT +localparam BPRED_SIZE = 32'd10; +`endif +localparam BPRED_NUM_LHR = 32'd6; +`ifdef BTB_OVERRIDE +localparam BTB_SIZE = `BTB_SIZE; +localparam RAS_SIZE = `RAS_SIZE; +`else +localparam BTB_SIZE = 32'd10; +localparam RAS_SIZE = 32'd16; +`endif + +localparam SVADU_SUPPORTED = 1; +localparam ZMMUL_SUPPORTED = 0; + +// FPU division architecture +localparam RADIX = 32'd2; +localparam DIVCOPIES = 32'd1; + +// bit manipulation +localparam ZBA_SUPPORTED = 1; +localparam ZBB_SUPPORTED = 1; +localparam ZBC_SUPPORTED = 1; +localparam ZBS_SUPPORTED = 1; + +// New compressed instructions +localparam ZCB_SUPPORTED = 1; +localparam ZCA_SUPPORTED = 0; +localparam ZCF_SUPPORTED = 0; +localparam ZCD_SUPPORTED = 0; + +// Memory synthesis configuration +localparam USE_SRAM = 0; + +`include "config-shared.vh" diff --git a/config/rv32gc_2_4/config.vh b/config/rv32gc_2_4/config.vh new file mode 100644 index 000000000..5e5cefc1e --- /dev/null +++ b/config/rv32gc_2_4/config.vh @@ -0,0 +1,189 @@ +////////////////////////////////////////// +// config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// include shared configuration +// `include "wally-shared.vh" +`include "BranchPredictorType.vh" + +// RV32 or RV64: XLEN = 32 or 64 +localparam XLEN = 32'd32; + +// IEEE 754 compliance +localparam IEEE754 = 0; + +localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5); +localparam ZICSR_SUPPORTED = 1; +localparam ZIFENCEI_SUPPORTED = 1; +localparam COUNTERS = 12'd32; +localparam ZICNTR_SUPPORTED = 1; +localparam ZIHPM_SUPPORTED = 1; +localparam ZFH_SUPPORTED = 0; +localparam SSTC_SUPPORTED = 1; +localparam ZICBOM_SUPPORTED = 1; +localparam ZICBOZ_SUPPORTED = 1; +localparam ZICBOP_SUPPORTED = 1; +localparam ZICCLSM_SUPPORTED = 0; +localparam SVPBMT_SUPPORTED = 0; +localparam SVNAPOT_SUPPORTED = 0; +localparam SVINVAL_SUPPORTED = 1; + +// LSU microarchitectural Features +localparam BUS_SUPPORTED = 1; +localparam DCACHE_SUPPORTED = 1; +localparam ICACHE_SUPPORTED = 1; +localparam VIRTMEM_SUPPORTED = 1; +localparam VECTORED_INTERRUPTS_SUPPORTED = 1; +localparam BIGENDIAN_SUPPORTED = 1; + +// TLB configuration. Entries should be a power of 2 +localparam ITLB_ENTRIES = 32'd32; +localparam DTLB_ENTRIES = 32'd32; + +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines +localparam DCACHE_NUMWAYS = 32'd4; +localparam DCACHE_WAYSIZEINBYTES = 32'd4096; +localparam DCACHE_LINELENINBITS = 32'd512; +localparam ICACHE_NUMWAYS = 32'd4; +localparam ICACHE_WAYSIZEINBYTES = 32'd4096; +localparam ICACHE_LINELENINBITS = 32'd512; + +// Integer Divider Configuration +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +localparam IDIV_BITSPERCYCLE = 32'd4; +localparam IDIV_ON_FPU = 1; + +// Legal number of PMP entries are 0, 16, or 64 +localparam PMP_ENTRIES = 32'd16; + +// Address space +localparam logic [63:0] RESET_VECTOR = 64'h80000000; + +// WFI Timeout Wait +localparam WFI_TIMEOUT_BIT = 32'd16; + +// Peripheral Addresses +// Peripheral memory space extends from BASE to BASE+RANGE +// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits +localparam DTIM_SUPPORTED = 1'b0; +localparam logic [63:0] DTIM_BASE = 64'h80000000; +localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; +localparam IROM_SUPPORTED = 1'b0; +localparam logic [63:0] IROM_BASE = 64'h80000000; +localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; +localparam BOOTROM_SUPPORTED = 1'b1; +localparam logic [63:0] BOOTROM_BASE = 64'h00001000; +localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; +localparam BOOTROM_PRELOAD = 1'b0; +localparam UNCORE_RAM_SUPPORTED = 1'b1; +localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; +localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; +localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam EXT_MEM_SUPPORTED = 1'b0; +localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; +localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; +localparam CLINT_SUPPORTED = 1'b1; +localparam logic [63:0] CLINT_BASE = 64'h02000000; +localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF; +localparam GPIO_SUPPORTED = 1'b1; +localparam logic [63:0] GPIO_BASE = 64'h10060000; +localparam logic [63:0] GPIO_RANGE = 64'h000000FF; +localparam UART_SUPPORTED = 1'b1; +localparam logic [63:0] UART_BASE = 64'h10000000; +localparam logic [63:0] UART_RANGE = 64'h00000007; +localparam PLIC_SUPPORTED = 1'b1; +localparam logic [63:0] PLIC_BASE = 64'h0C000000; +localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; +localparam SDC_SUPPORTED = 1'b0; +localparam logic [63:0] SDC_BASE = 64'h00013000; +localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam SPI_SUPPORTED = 1'b1; +localparam logic [63:0] SPI_BASE = 64'h10040000; +localparam logic [63:0] SPI_RANGE = 64'h00000FFF; + +// Bus Interface width +localparam AHBW = 32'd32; + +// Test modes + +// Tie GPIO outputs back to inputs +localparam GPIO_LOOPBACK_TEST = 1; +localparam SPI_LOOPBACK_TEST = 1; + +// Hardware configuration +localparam UART_PRESCALE = 32'd1; + +// Interrupt configuration +localparam PLIC_NUM_SRC = 32'd10; +// comment out the following if >=32 sources +localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); +localparam PLIC_GPIO_ID = 32'd3; +localparam PLIC_UART_ID = 32'd10; +localparam PLIC_SPI_ID = 32'd6; +localparam PLIC_SDC_ID = 32'd9; + +localparam BPRED_SUPPORTED = 1; +// this is an annoying hack for the branch predictor parameterization override. +`ifdef BPRED_OVERRIDE +localparam BPRED_TYPE = `BPRED_TYPE; +localparam BPRED_SIZE = `BPRED_SIZE; +`else +localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT +localparam BPRED_SIZE = 32'd10; +`endif +localparam BPRED_NUM_LHR = 32'd6; +`ifdef BTB_OVERRIDE +localparam BTB_SIZE = `BTB_SIZE; +localparam RAS_SIZE = `RAS_SIZE; +`else +localparam BTB_SIZE = 32'd10; +localparam RAS_SIZE = 32'd16; +`endif + +localparam SVADU_SUPPORTED = 1; +localparam ZMMUL_SUPPORTED = 0; + +// FPU division architecture +localparam RADIX = 32'd2; +localparam DIVCOPIES = 32'd4; + +// bit manipulation +localparam ZBA_SUPPORTED = 1; +localparam ZBB_SUPPORTED = 1; +localparam ZBC_SUPPORTED = 1; +localparam ZBS_SUPPORTED = 1; + +// New compressed instructions +localparam ZCB_SUPPORTED = 1; +localparam ZCA_SUPPORTED = 0; +localparam ZCF_SUPPORTED = 0; +localparam ZCD_SUPPORTED = 0; + +// Memory synthesis configuration +localparam USE_SRAM = 0; + +`include "config-shared.vh" diff --git a/config/rv32gc_2_4i/config.vh b/config/rv32gc_2_4i/config.vh new file mode 100644 index 000000000..d4ee73b3d --- /dev/null +++ b/config/rv32gc_2_4i/config.vh @@ -0,0 +1,189 @@ +////////////////////////////////////////// +// config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// include shared configuration +// `include "wally-shared.vh" +`include "BranchPredictorType.vh" + +// RV32 or RV64: XLEN = 32 or 64 +localparam XLEN = 32'd32; + +// IEEE 754 compliance +localparam IEEE754 = 0; + +localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5); +localparam ZICSR_SUPPORTED = 1; +localparam ZIFENCEI_SUPPORTED = 1; +localparam COUNTERS = 12'd32; +localparam ZICNTR_SUPPORTED = 1; +localparam ZIHPM_SUPPORTED = 1; +localparam ZFH_SUPPORTED = 0; +localparam SSTC_SUPPORTED = 1; +localparam ZICBOM_SUPPORTED = 1; +localparam ZICBOZ_SUPPORTED = 1; +localparam ZICBOP_SUPPORTED = 1; +localparam ZICCLSM_SUPPORTED = 0; +localparam SVPBMT_SUPPORTED = 0; +localparam SVNAPOT_SUPPORTED = 0; +localparam SVINVAL_SUPPORTED = 1; + +// LSU microarchitectural Features +localparam BUS_SUPPORTED = 1; +localparam DCACHE_SUPPORTED = 1; +localparam ICACHE_SUPPORTED = 1; +localparam VIRTMEM_SUPPORTED = 1; +localparam VECTORED_INTERRUPTS_SUPPORTED = 1; +localparam BIGENDIAN_SUPPORTED = 1; + +// TLB configuration. Entries should be a power of 2 +localparam ITLB_ENTRIES = 32'd32; +localparam DTLB_ENTRIES = 32'd32; + +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines +localparam DCACHE_NUMWAYS = 32'd4; +localparam DCACHE_WAYSIZEINBYTES = 32'd4096; +localparam DCACHE_LINELENINBITS = 32'd512; +localparam ICACHE_NUMWAYS = 32'd4; +localparam ICACHE_WAYSIZEINBYTES = 32'd4096; +localparam ICACHE_LINELENINBITS = 32'd512; + +// Integer Divider Configuration +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +localparam IDIV_BITSPERCYCLE = 32'd4; +localparam IDIV_ON_FPU = 0; + +// Legal number of PMP entries are 0, 16, or 64 +localparam PMP_ENTRIES = 32'd16; + +// Address space +localparam logic [63:0] RESET_VECTOR = 64'h80000000; + +// WFI Timeout Wait +localparam WFI_TIMEOUT_BIT = 32'd16; + +// Peripheral Addresses +// Peripheral memory space extends from BASE to BASE+RANGE +// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits +localparam DTIM_SUPPORTED = 1'b0; +localparam logic [63:0] DTIM_BASE = 64'h80000000; +localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; +localparam IROM_SUPPORTED = 1'b0; +localparam logic [63:0] IROM_BASE = 64'h80000000; +localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; +localparam BOOTROM_SUPPORTED = 1'b1; +localparam logic [63:0] BOOTROM_BASE = 64'h00001000; +localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; +localparam BOOTROM_PRELOAD = 1'b0; +localparam UNCORE_RAM_SUPPORTED = 1'b1; +localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; +localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; +localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam EXT_MEM_SUPPORTED = 1'b0; +localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; +localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; +localparam CLINT_SUPPORTED = 1'b1; +localparam logic [63:0] CLINT_BASE = 64'h02000000; +localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF; +localparam GPIO_SUPPORTED = 1'b1; +localparam logic [63:0] GPIO_BASE = 64'h10060000; +localparam logic [63:0] GPIO_RANGE = 64'h000000FF; +localparam UART_SUPPORTED = 1'b1; +localparam logic [63:0] UART_BASE = 64'h10000000; +localparam logic [63:0] UART_RANGE = 64'h00000007; +localparam PLIC_SUPPORTED = 1'b1; +localparam logic [63:0] PLIC_BASE = 64'h0C000000; +localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; +localparam SDC_SUPPORTED = 1'b0; +localparam logic [63:0] SDC_BASE = 64'h00013000; +localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam SPI_SUPPORTED = 1'b1; +localparam logic [63:0] SPI_BASE = 64'h10040000; +localparam logic [63:0] SPI_RANGE = 64'h00000FFF; + +// Bus Interface width +localparam AHBW = 32'd32; + +// Test modes + +// Tie GPIO outputs back to inputs +localparam GPIO_LOOPBACK_TEST = 1; +localparam SPI_LOOPBACK_TEST = 1; + +// Hardware configuration +localparam UART_PRESCALE = 32'd1; + +// Interrupt configuration +localparam PLIC_NUM_SRC = 32'd10; +// comment out the following if >=32 sources +localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); +localparam PLIC_GPIO_ID = 32'd3; +localparam PLIC_UART_ID = 32'd10; +localparam PLIC_SPI_ID = 32'd6; +localparam PLIC_SDC_ID = 32'd9; + +localparam BPRED_SUPPORTED = 1; +// this is an annoying hack for the branch predictor parameterization override. +`ifdef BPRED_OVERRIDE +localparam BPRED_TYPE = `BPRED_TYPE; +localparam BPRED_SIZE = `BPRED_SIZE; +`else +localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT +localparam BPRED_SIZE = 32'd10; +`endif +localparam BPRED_NUM_LHR = 32'd6; +`ifdef BTB_OVERRIDE +localparam BTB_SIZE = `BTB_SIZE; +localparam RAS_SIZE = `RAS_SIZE; +`else +localparam BTB_SIZE = 32'd10; +localparam RAS_SIZE = 32'd16; +`endif + +localparam SVADU_SUPPORTED = 1; +localparam ZMMUL_SUPPORTED = 0; + +// FPU division architecture +localparam RADIX = 32'd2; +localparam DIVCOPIES = 32'd4; + +// bit manipulation +localparam ZBA_SUPPORTED = 1; +localparam ZBB_SUPPORTED = 1; +localparam ZBC_SUPPORTED = 1; +localparam ZBS_SUPPORTED = 1; + +// New compressed instructions +localparam ZCB_SUPPORTED = 1; +localparam ZCA_SUPPORTED = 0; +localparam ZCF_SUPPORTED = 0; +localparam ZCD_SUPPORTED = 0; + +// Memory synthesis configuration +localparam USE_SRAM = 0; + +`include "config-shared.vh" diff --git a/config/rv32gc_4_1/config.vh b/config/rv32gc_4_1/config.vh new file mode 100644 index 000000000..e572f09d2 --- /dev/null +++ b/config/rv32gc_4_1/config.vh @@ -0,0 +1,189 @@ +////////////////////////////////////////// +// config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// include shared configuration +// `include "wally-shared.vh" +`include "BranchPredictorType.vh" + +// RV32 or RV64: XLEN = 32 or 64 +localparam XLEN = 32'd32; + +// IEEE 754 compliance +localparam IEEE754 = 0; + +localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5); +localparam ZICSR_SUPPORTED = 1; +localparam ZIFENCEI_SUPPORTED = 1; +localparam COUNTERS = 12'd32; +localparam ZICNTR_SUPPORTED = 1; +localparam ZIHPM_SUPPORTED = 1; +localparam ZFH_SUPPORTED = 0; +localparam SSTC_SUPPORTED = 1; +localparam ZICBOM_SUPPORTED = 1; +localparam ZICBOZ_SUPPORTED = 1; +localparam ZICBOP_SUPPORTED = 1; +localparam ZICCLSM_SUPPORTED = 0; +localparam SVPBMT_SUPPORTED = 0; +localparam SVNAPOT_SUPPORTED = 0; +localparam SVINVAL_SUPPORTED = 1; + +// LSU microarchitectural Features +localparam BUS_SUPPORTED = 1; +localparam DCACHE_SUPPORTED = 1; +localparam ICACHE_SUPPORTED = 1; +localparam VIRTMEM_SUPPORTED = 1; +localparam VECTORED_INTERRUPTS_SUPPORTED = 1; +localparam BIGENDIAN_SUPPORTED = 1; + +// TLB configuration. Entries should be a power of 2 +localparam ITLB_ENTRIES = 32'd32; +localparam DTLB_ENTRIES = 32'd32; + +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines +localparam DCACHE_NUMWAYS = 32'd4; +localparam DCACHE_WAYSIZEINBYTES = 32'd4096; +localparam DCACHE_LINELENINBITS = 32'd512; +localparam ICACHE_NUMWAYS = 32'd4; +localparam ICACHE_WAYSIZEINBYTES = 32'd4096; +localparam ICACHE_LINELENINBITS = 32'd512; + +// Integer Divider Configuration +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +localparam IDIV_BITSPERCYCLE = 32'd4; +localparam IDIV_ON_FPU = 1; + +// Legal number of PMP entries are 0, 16, or 64 +localparam PMP_ENTRIES = 32'd16; + +// Address space +localparam logic [63:0] RESET_VECTOR = 64'h80000000; + +// WFI Timeout Wait +localparam WFI_TIMEOUT_BIT = 32'd16; + +// Peripheral Addresses +// Peripheral memory space extends from BASE to BASE+RANGE +// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits +localparam DTIM_SUPPORTED = 1'b0; +localparam logic [63:0] DTIM_BASE = 64'h80000000; +localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; +localparam IROM_SUPPORTED = 1'b0; +localparam logic [63:0] IROM_BASE = 64'h80000000; +localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; +localparam BOOTROM_SUPPORTED = 1'b1; +localparam logic [63:0] BOOTROM_BASE = 64'h00001000; +localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; +localparam BOOTROM_PRELOAD = 1'b0; +localparam UNCORE_RAM_SUPPORTED = 1'b1; +localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; +localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; +localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam EXT_MEM_SUPPORTED = 1'b0; +localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; +localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; +localparam CLINT_SUPPORTED = 1'b1; +localparam logic [63:0] CLINT_BASE = 64'h02000000; +localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF; +localparam GPIO_SUPPORTED = 1'b1; +localparam logic [63:0] GPIO_BASE = 64'h10060000; +localparam logic [63:0] GPIO_RANGE = 64'h000000FF; +localparam UART_SUPPORTED = 1'b1; +localparam logic [63:0] UART_BASE = 64'h10000000; +localparam logic [63:0] UART_RANGE = 64'h00000007; +localparam PLIC_SUPPORTED = 1'b1; +localparam logic [63:0] PLIC_BASE = 64'h0C000000; +localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; +localparam SDC_SUPPORTED = 1'b0; +localparam logic [63:0] SDC_BASE = 64'h00013000; +localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam SPI_SUPPORTED = 1'b1; +localparam logic [63:0] SPI_BASE = 64'h10040000; +localparam logic [63:0] SPI_RANGE = 64'h00000FFF; + +// Bus Interface width +localparam AHBW = 32'd32; + +// Test modes + +// Tie GPIO outputs back to inputs +localparam GPIO_LOOPBACK_TEST = 1; +localparam SPI_LOOPBACK_TEST = 1; + +// Hardware configuration +localparam UART_PRESCALE = 32'd1; + +// Interrupt configuration +localparam PLIC_NUM_SRC = 32'd10; +// comment out the following if >=32 sources +localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); +localparam PLIC_GPIO_ID = 32'd3; +localparam PLIC_UART_ID = 32'd10; +localparam PLIC_SPI_ID = 32'd6; +localparam PLIC_SDC_ID = 32'd9; + +localparam BPRED_SUPPORTED = 1; +// this is an annoying hack for the branch predictor parameterization override. +`ifdef BPRED_OVERRIDE +localparam BPRED_TYPE = `BPRED_TYPE; +localparam BPRED_SIZE = `BPRED_SIZE; +`else +localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT +localparam BPRED_SIZE = 32'd10; +`endif +localparam BPRED_NUM_LHR = 32'd6; +`ifdef BTB_OVERRIDE +localparam BTB_SIZE = `BTB_SIZE; +localparam RAS_SIZE = `RAS_SIZE; +`else +localparam BTB_SIZE = 32'd10; +localparam RAS_SIZE = 32'd16; +`endif + +localparam SVADU_SUPPORTED = 1; +localparam ZMMUL_SUPPORTED = 0; + +// FPU division architecture +localparam RADIX = 32'd4; +localparam DIVCOPIES = 32'd1; + +// bit manipulation +localparam ZBA_SUPPORTED = 1; +localparam ZBB_SUPPORTED = 1; +localparam ZBC_SUPPORTED = 1; +localparam ZBS_SUPPORTED = 1; + +// New compressed instructions +localparam ZCB_SUPPORTED = 1; +localparam ZCA_SUPPORTED = 0; +localparam ZCF_SUPPORTED = 0; +localparam ZCD_SUPPORTED = 0; + +// Memory synthesis configuration +localparam USE_SRAM = 0; + +`include "config-shared.vh" diff --git a/config/rv32gc_4_1i/config.vh b/config/rv32gc_4_1i/config.vh new file mode 100644 index 000000000..bea38ba69 --- /dev/null +++ b/config/rv32gc_4_1i/config.vh @@ -0,0 +1,189 @@ +////////////////////////////////////////// +// config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +// include shared configuration +// `include "wally-shared.vh" +`include "BranchPredictorType.vh" + +// RV32 or RV64: XLEN = 32 or 64 +localparam XLEN = 32'd32; + +// IEEE 754 compliance +localparam IEEE754 = 0; + +localparam MISA = (32'h00000104 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 <<3 | 1 << 5); +localparam ZICSR_SUPPORTED = 1; +localparam ZIFENCEI_SUPPORTED = 1; +localparam COUNTERS = 12'd32; +localparam ZICNTR_SUPPORTED = 1; +localparam ZIHPM_SUPPORTED = 1; +localparam ZFH_SUPPORTED = 0; +localparam SSTC_SUPPORTED = 1; +localparam ZICBOM_SUPPORTED = 1; +localparam ZICBOZ_SUPPORTED = 1; +localparam ZICBOP_SUPPORTED = 1; +localparam ZICCLSM_SUPPORTED = 0; +localparam SVPBMT_SUPPORTED = 0; +localparam SVNAPOT_SUPPORTED = 0; +localparam SVINVAL_SUPPORTED = 1; + +// LSU microarchitectural Features +localparam BUS_SUPPORTED = 1; +localparam DCACHE_SUPPORTED = 1; +localparam ICACHE_SUPPORTED = 1; +localparam VIRTMEM_SUPPORTED = 1; +localparam VECTORED_INTERRUPTS_SUPPORTED = 1; +localparam BIGENDIAN_SUPPORTED = 1; + +// TLB configuration. Entries should be a power of 2 +localparam ITLB_ENTRIES = 32'd32; +localparam DTLB_ENTRIES = 32'd32; + +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines +localparam DCACHE_NUMWAYS = 32'd4; +localparam DCACHE_WAYSIZEINBYTES = 32'd4096; +localparam DCACHE_LINELENINBITS = 32'd512; +localparam ICACHE_NUMWAYS = 32'd4; +localparam ICACHE_WAYSIZEINBYTES = 32'd4096; +localparam ICACHE_LINELENINBITS = 32'd512; + +// Integer Divider Configuration +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +localparam IDIV_BITSPERCYCLE = 32'd4; +localparam IDIV_ON_FPU = 0; + +// Legal number of PMP entries are 0, 16, or 64 +localparam PMP_ENTRIES = 32'd16; + +// Address space +localparam logic [63:0] RESET_VECTOR = 64'h80000000; + +// WFI Timeout Wait +localparam WFI_TIMEOUT_BIT = 32'd16; + +// Peripheral Addresses +// Peripheral memory space extends from BASE to BASE+RANGE +// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits +localparam DTIM_SUPPORTED = 1'b0; +localparam logic [63:0] DTIM_BASE = 64'h80000000; +localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; +localparam IROM_SUPPORTED = 1'b0; +localparam logic [63:0] IROM_BASE = 64'h80000000; +localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; +localparam BOOTROM_SUPPORTED = 1'b1; +localparam logic [63:0] BOOTROM_BASE = 64'h00001000; +localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; +localparam BOOTROM_PRELOAD = 1'b0; +localparam UNCORE_RAM_SUPPORTED = 1'b1; +localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; +localparam logic [63:0] UNCORE_RAM_RANGE = 64'h07FFFFFF; +localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam EXT_MEM_SUPPORTED = 1'b0; +localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; +localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; +localparam CLINT_SUPPORTED = 1'b1; +localparam logic [63:0] CLINT_BASE = 64'h02000000; +localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF; +localparam GPIO_SUPPORTED = 1'b1; +localparam logic [63:0] GPIO_BASE = 64'h10060000; +localparam logic [63:0] GPIO_RANGE = 64'h000000FF; +localparam UART_SUPPORTED = 1'b1; +localparam logic [63:0] UART_BASE = 64'h10000000; +localparam logic [63:0] UART_RANGE = 64'h00000007; +localparam PLIC_SUPPORTED = 1'b1; +localparam logic [63:0] PLIC_BASE = 64'h0C000000; +localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; +localparam SDC_SUPPORTED = 1'b0; +localparam logic [63:0] SDC_BASE = 64'h00013000; +localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam SPI_SUPPORTED = 1'b1; +localparam logic [63:0] SPI_BASE = 64'h10040000; +localparam logic [63:0] SPI_RANGE = 64'h00000FFF; + +// Bus Interface width +localparam AHBW = 32'd32; + +// Test modes + +// Tie GPIO outputs back to inputs +localparam GPIO_LOOPBACK_TEST = 1; +localparam SPI_LOOPBACK_TEST = 1; + +// Hardware configuration +localparam UART_PRESCALE = 32'd1; + +// Interrupt configuration +localparam PLIC_NUM_SRC = 32'd10; +// comment out the following if >=32 sources +localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); +localparam PLIC_GPIO_ID = 32'd3; +localparam PLIC_UART_ID = 32'd10; +localparam PLIC_SPI_ID = 32'd6; +localparam PLIC_SDC_ID = 32'd9; + +localparam BPRED_SUPPORTED = 1; +// this is an annoying hack for the branch predictor parameterization override. +`ifdef BPRED_OVERRIDE +localparam BPRED_TYPE = `BPRED_TYPE; +localparam BPRED_SIZE = `BPRED_SIZE; +`else +localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT +localparam BPRED_SIZE = 32'd10; +`endif +localparam BPRED_NUM_LHR = 32'd6; +`ifdef BTB_OVERRIDE +localparam BTB_SIZE = `BTB_SIZE; +localparam RAS_SIZE = `RAS_SIZE; +`else +localparam BTB_SIZE = 32'd10; +localparam RAS_SIZE = 32'd16; +`endif + +localparam SVADU_SUPPORTED = 1; +localparam ZMMUL_SUPPORTED = 0; + +// FPU division architecture +localparam RADIX = 32'd4; +localparam DIVCOPIES = 32'd1; + +// bit manipulation +localparam ZBA_SUPPORTED = 1; +localparam ZBB_SUPPORTED = 1; +localparam ZBC_SUPPORTED = 1; +localparam ZBS_SUPPORTED = 1; + +// New compressed instructions +localparam ZCB_SUPPORTED = 1; +localparam ZCA_SUPPORTED = 0; +localparam ZCF_SUPPORTED = 0; +localparam ZCD_SUPPORTED = 0; + +// Memory synthesis configuration +localparam USE_SRAM = 0; + +`include "config-shared.vh" diff --git a/config/rv64gc_2_1/config.vh b/config/rv64gc_2_1/config.vh new file mode 100644 index 000000000..ff87cf854 --- /dev/null +++ b/config/rv64gc_2_1/config.vh @@ -0,0 +1,179 @@ +////////////////////////////////////////// +// config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "BranchPredictorType.vh" + +// RV32 or RV64: XLEN = 32 or 64 +localparam XLEN = 32'd64; + +// IEEE 754 compliance +localparam IEEE754 = 0; + +// MISA RISC-V configuration per specification +localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0); +localparam ZICSR_SUPPORTED = 1; +localparam ZIFENCEI_SUPPORTED = 1; +localparam COUNTERS = 12'd32; +localparam ZICNTR_SUPPORTED = 1; +localparam ZIHPM_SUPPORTED = 1; +localparam ZFH_SUPPORTED = 0; +localparam SSTC_SUPPORTED = 1; +localparam ZICBOM_SUPPORTED = 1; +localparam ZICBOZ_SUPPORTED = 1; +localparam ZICBOP_SUPPORTED = 1; +localparam ZICCLSM_SUPPORTED = 1; +localparam SVPBMT_SUPPORTED = 1; +localparam SVNAPOT_SUPPORTED = 1; +localparam SVINVAL_SUPPORTED = 1; + +// LSU microarchitectural Features +localparam BUS_SUPPORTED = 1; +localparam DCACHE_SUPPORTED = 1; +localparam ICACHE_SUPPORTED = 1; +localparam VIRTMEM_SUPPORTED = 1; +localparam VECTORED_INTERRUPTS_SUPPORTED = 1; +localparam BIGENDIAN_SUPPORTED = 1; + +// TLB configuration. Entries should be a power of 2 +localparam ITLB_ENTRIES = 32'd32; +localparam DTLB_ENTRIES = 32'd32; + +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines +localparam DCACHE_NUMWAYS = 32'd4; +localparam DCACHE_WAYSIZEINBYTES = 32'd4096; +localparam DCACHE_LINELENINBITS = 32'd512; +localparam ICACHE_NUMWAYS = 32'd4; +localparam ICACHE_WAYSIZEINBYTES = 32'd4096; +localparam ICACHE_LINELENINBITS = 32'd512; + +// Integer Divider Configuration +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +localparam IDIV_BITSPERCYCLE = 32'd4; +localparam IDIV_ON_FPU = 1; + +// Legal number of PMP entries are 0, 16, or 64 +localparam PMP_ENTRIES = 32'd16; + +// Address space +localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000; + +// Bus Interface width +localparam AHBW = 32'd64; + +// WFI Timeout Wait +localparam WFI_TIMEOUT_BIT = 32'd16; + +// Peripheral Physical Addresses +// Peripheral memory space extends from BASE to BASE+RANGE +// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits + +// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? +localparam DTIM_SUPPORTED = 1'b0; +localparam logic [63:0] DTIM_BASE = 64'h80000000; +localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; +localparam IROM_SUPPORTED = 1'b0; +localparam logic [63:0] IROM_BASE = 64'h80000000; +localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; +localparam BOOTROM_SUPPORTED = 1'b1; +localparam logic [63:0] BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder; +localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; +localparam BOOTROM_PRELOAD = 1'b0; +localparam UNCORE_RAM_SUPPORTED = 1'b1; +localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; +localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF; +localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam EXT_MEM_SUPPORTED = 1'b0; +localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; +localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; +localparam CLINT_SUPPORTED = 1'b1; +localparam logic [63:0] CLINT_BASE = 64'h02000000; +localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF; +localparam GPIO_SUPPORTED = 1'b1; +localparam logic [63:0] GPIO_BASE = 64'h10060000; +localparam logic [63:0] GPIO_RANGE = 64'h000000FF; +localparam UART_SUPPORTED = 1'b1; +localparam logic [63:0] UART_BASE = 64'h10000000; +localparam logic [63:0] UART_RANGE = 64'h00000007; +localparam PLIC_SUPPORTED = 1'b1; +localparam logic [63:0] PLIC_BASE = 64'h0C000000; +localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; +localparam SDC_SUPPORTED = 1'b0; +localparam logic [63:0] SDC_BASE = 64'h00013000; +localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam SPI_SUPPORTED = 1'b1; +localparam logic [63:0] SPI_BASE = 64'h10040000; +localparam logic [63:0] SPI_RANGE = 64'h00000FFF; + +// Test modes + +// Tie GPIO outputs back to inputs +localparam GPIO_LOOPBACK_TEST = 1; +localparam SPI_LOOPBACK_TEST = 1; + +// Hardware configuration +localparam UART_PRESCALE = 32'd1; + +// Interrupt configuration +localparam PLIC_NUM_SRC = 32'd10; +// comment out the following if >=32 sources +localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); +localparam PLIC_GPIO_ID = 32'd3; +localparam PLIC_UART_ID = 32'd10; +localparam PLIC_SPI_ID = 32'd6; +localparam PLIC_SDC_ID = 32'd9; + +localparam BPRED_SUPPORTED = 1; +localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT +localparam BPRED_NUM_LHR = 32'd6; +localparam BPRED_SIZE = 32'd6; +localparam BTB_SIZE = 32'd10; +localparam RAS_SIZE = 32'd16; + +localparam SVADU_SUPPORTED = 1; +localparam ZMMUL_SUPPORTED = 0; + +// FPU division architecture +localparam RADIX = 32'h2; +localparam DIVCOPIES = 32'h1; + +// bit manipulation +localparam ZBA_SUPPORTED = 1; +localparam ZBB_SUPPORTED = 1; +localparam ZBC_SUPPORTED = 1; +localparam ZBS_SUPPORTED = 1; + +// New compressed instructions +localparam ZCB_SUPPORTED = 1; +localparam ZCA_SUPPORTED = 0; +localparam ZCF_SUPPORTED = 0; +localparam ZCD_SUPPORTED = 0; + +// Memory synthesis configuration +localparam USE_SRAM = 0; + +`include "config-shared.vh" diff --git a/config/rv64gc_2_1i/config.vh b/config/rv64gc_2_1i/config.vh new file mode 100644 index 000000000..6a3d1b53d --- /dev/null +++ b/config/rv64gc_2_1i/config.vh @@ -0,0 +1,179 @@ +////////////////////////////////////////// +// config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "BranchPredictorType.vh" + +// RV32 or RV64: XLEN = 32 or 64 +localparam XLEN = 32'd64; + +// IEEE 754 compliance +localparam IEEE754 = 0; + +// MISA RISC-V configuration per specification +localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0); +localparam ZICSR_SUPPORTED = 1; +localparam ZIFENCEI_SUPPORTED = 1; +localparam COUNTERS = 12'd32; +localparam ZICNTR_SUPPORTED = 1; +localparam ZIHPM_SUPPORTED = 1; +localparam ZFH_SUPPORTED = 0; +localparam SSTC_SUPPORTED = 1; +localparam ZICBOM_SUPPORTED = 1; +localparam ZICBOZ_SUPPORTED = 1; +localparam ZICBOP_SUPPORTED = 1; +localparam ZICCLSM_SUPPORTED = 1; +localparam SVPBMT_SUPPORTED = 1; +localparam SVNAPOT_SUPPORTED = 1; +localparam SVINVAL_SUPPORTED = 1; + +// LSU microarchitectural Features +localparam BUS_SUPPORTED = 1; +localparam DCACHE_SUPPORTED = 1; +localparam ICACHE_SUPPORTED = 1; +localparam VIRTMEM_SUPPORTED = 1; +localparam VECTORED_INTERRUPTS_SUPPORTED = 1; +localparam BIGENDIAN_SUPPORTED = 1; + +// TLB configuration. Entries should be a power of 2 +localparam ITLB_ENTRIES = 32'd32; +localparam DTLB_ENTRIES = 32'd32; + +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines +localparam DCACHE_NUMWAYS = 32'd4; +localparam DCACHE_WAYSIZEINBYTES = 32'd4096; +localparam DCACHE_LINELENINBITS = 32'd512; +localparam ICACHE_NUMWAYS = 32'd4; +localparam ICACHE_WAYSIZEINBYTES = 32'd4096; +localparam ICACHE_LINELENINBITS = 32'd512; + +// Integer Divider Configuration +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +localparam IDIV_BITSPERCYCLE = 32'd4; +localparam IDIV_ON_FPU = 0; + +// Legal number of PMP entries are 0, 16, or 64 +localparam PMP_ENTRIES = 32'd16; + +// Address space +localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000; + +// Bus Interface width +localparam AHBW = 32'd64; + +// WFI Timeout Wait +localparam WFI_TIMEOUT_BIT = 32'd16; + +// Peripheral Physical Addresses +// Peripheral memory space extends from BASE to BASE+RANGE +// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits + +// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? +localparam DTIM_SUPPORTED = 1'b0; +localparam logic [63:0] DTIM_BASE = 64'h80000000; +localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; +localparam IROM_SUPPORTED = 1'b0; +localparam logic [63:0] IROM_BASE = 64'h80000000; +localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; +localparam BOOTROM_SUPPORTED = 1'b1; +localparam logic [63:0] BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder; +localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; +localparam BOOTROM_PRELOAD = 1'b0; +localparam UNCORE_RAM_SUPPORTED = 1'b1; +localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; +localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF; +localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam EXT_MEM_SUPPORTED = 1'b0; +localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; +localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; +localparam CLINT_SUPPORTED = 1'b1; +localparam logic [63:0] CLINT_BASE = 64'h02000000; +localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF; +localparam GPIO_SUPPORTED = 1'b1; +localparam logic [63:0] GPIO_BASE = 64'h10060000; +localparam logic [63:0] GPIO_RANGE = 64'h000000FF; +localparam UART_SUPPORTED = 1'b1; +localparam logic [63:0] UART_BASE = 64'h10000000; +localparam logic [63:0] UART_RANGE = 64'h00000007; +localparam PLIC_SUPPORTED = 1'b1; +localparam logic [63:0] PLIC_BASE = 64'h0C000000; +localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; +localparam SDC_SUPPORTED = 1'b0; +localparam logic [63:0] SDC_BASE = 64'h00013000; +localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam SPI_SUPPORTED = 1'b1; +localparam logic [63:0] SPI_BASE = 64'h10040000; +localparam logic [63:0] SPI_RANGE = 64'h00000FFF; + +// Test modes + +// Tie GPIO outputs back to inputs +localparam GPIO_LOOPBACK_TEST = 1; +localparam SPI_LOOPBACK_TEST = 1; + +// Hardware configuration +localparam UART_PRESCALE = 32'd1; + +// Interrupt configuration +localparam PLIC_NUM_SRC = 32'd10; +// comment out the following if >=32 sources +localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); +localparam PLIC_GPIO_ID = 32'd3; +localparam PLIC_UART_ID = 32'd10; +localparam PLIC_SPI_ID = 32'd6; +localparam PLIC_SDC_ID = 32'd9; + +localparam BPRED_SUPPORTED = 1; +localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT +localparam BPRED_NUM_LHR = 32'd6; +localparam BPRED_SIZE = 32'd6; +localparam BTB_SIZE = 32'd10; +localparam RAS_SIZE = 32'd16; + +localparam SVADU_SUPPORTED = 1; +localparam ZMMUL_SUPPORTED = 0; + +// FPU division architecture +localparam RADIX = 32'h2; +localparam DIVCOPIES = 32'h1; + +// bit manipulation +localparam ZBA_SUPPORTED = 1; +localparam ZBB_SUPPORTED = 1; +localparam ZBC_SUPPORTED = 1; +localparam ZBS_SUPPORTED = 1; + +// New compressed instructions +localparam ZCB_SUPPORTED = 1; +localparam ZCA_SUPPORTED = 0; +localparam ZCF_SUPPORTED = 0; +localparam ZCD_SUPPORTED = 0; + +// Memory synthesis configuration +localparam USE_SRAM = 0; + +`include "config-shared.vh" diff --git a/config/rv64gc_2_4/config.vh b/config/rv64gc_2_4/config.vh new file mode 100644 index 000000000..827bbd0e8 --- /dev/null +++ b/config/rv64gc_2_4/config.vh @@ -0,0 +1,179 @@ +////////////////////////////////////////// +// config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "BranchPredictorType.vh" + +// RV32 or RV64: XLEN = 32 or 64 +localparam XLEN = 32'd64; + +// IEEE 754 compliance +localparam IEEE754 = 0; + +// MISA RISC-V configuration per specification +localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0); +localparam ZICSR_SUPPORTED = 1; +localparam ZIFENCEI_SUPPORTED = 1; +localparam COUNTERS = 12'd32; +localparam ZICNTR_SUPPORTED = 1; +localparam ZIHPM_SUPPORTED = 1; +localparam ZFH_SUPPORTED = 0; +localparam SSTC_SUPPORTED = 1; +localparam ZICBOM_SUPPORTED = 1; +localparam ZICBOZ_SUPPORTED = 1; +localparam ZICBOP_SUPPORTED = 1; +localparam ZICCLSM_SUPPORTED = 1; +localparam SVPBMT_SUPPORTED = 1; +localparam SVNAPOT_SUPPORTED = 1; +localparam SVINVAL_SUPPORTED = 1; + +// LSU microarchitectural Features +localparam BUS_SUPPORTED = 1; +localparam DCACHE_SUPPORTED = 1; +localparam ICACHE_SUPPORTED = 1; +localparam VIRTMEM_SUPPORTED = 1; +localparam VECTORED_INTERRUPTS_SUPPORTED = 1; +localparam BIGENDIAN_SUPPORTED = 1; + +// TLB configuration. Entries should be a power of 2 +localparam ITLB_ENTRIES = 32'd32; +localparam DTLB_ENTRIES = 32'd32; + +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines +localparam DCACHE_NUMWAYS = 32'd4; +localparam DCACHE_WAYSIZEINBYTES = 32'd4096; +localparam DCACHE_LINELENINBITS = 32'd512; +localparam ICACHE_NUMWAYS = 32'd4; +localparam ICACHE_WAYSIZEINBYTES = 32'd4096; +localparam ICACHE_LINELENINBITS = 32'd512; + +// Integer Divider Configuration +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +localparam IDIV_BITSPERCYCLE = 32'd4; +localparam IDIV_ON_FPU = 1; + +// Legal number of PMP entries are 0, 16, or 64 +localparam PMP_ENTRIES = 32'd16; + +// Address space +localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000; + +// Bus Interface width +localparam AHBW = 32'd64; + +// WFI Timeout Wait +localparam WFI_TIMEOUT_BIT = 32'd16; + +// Peripheral Physical Addresses +// Peripheral memory space extends from BASE to BASE+RANGE +// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits + +// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? +localparam DTIM_SUPPORTED = 1'b0; +localparam logic [63:0] DTIM_BASE = 64'h80000000; +localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; +localparam IROM_SUPPORTED = 1'b0; +localparam logic [63:0] IROM_BASE = 64'h80000000; +localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; +localparam BOOTROM_SUPPORTED = 1'b1; +localparam logic [63:0] BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder; +localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; +localparam BOOTROM_PRELOAD = 1'b0; +localparam UNCORE_RAM_SUPPORTED = 1'b1; +localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; +localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF; +localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam EXT_MEM_SUPPORTED = 1'b0; +localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; +localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; +localparam CLINT_SUPPORTED = 1'b1; +localparam logic [63:0] CLINT_BASE = 64'h02000000; +localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF; +localparam GPIO_SUPPORTED = 1'b1; +localparam logic [63:0] GPIO_BASE = 64'h10060000; +localparam logic [63:0] GPIO_RANGE = 64'h000000FF; +localparam UART_SUPPORTED = 1'b1; +localparam logic [63:0] UART_BASE = 64'h10000000; +localparam logic [63:0] UART_RANGE = 64'h00000007; +localparam PLIC_SUPPORTED = 1'b1; +localparam logic [63:0] PLIC_BASE = 64'h0C000000; +localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; +localparam SDC_SUPPORTED = 1'b0; +localparam logic [63:0] SDC_BASE = 64'h00013000; +localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam SPI_SUPPORTED = 1'b1; +localparam logic [63:0] SPI_BASE = 64'h10040000; +localparam logic [63:0] SPI_RANGE = 64'h00000FFF; + +// Test modes + +// Tie GPIO outputs back to inputs +localparam GPIO_LOOPBACK_TEST = 1; +localparam SPI_LOOPBACK_TEST = 1; + +// Hardware configuration +localparam UART_PRESCALE = 32'd1; + +// Interrupt configuration +localparam PLIC_NUM_SRC = 32'd10; +// comment out the following if >=32 sources +localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); +localparam PLIC_GPIO_ID = 32'd3; +localparam PLIC_UART_ID = 32'd10; +localparam PLIC_SPI_ID = 32'd6; +localparam PLIC_SDC_ID = 32'd9; + +localparam BPRED_SUPPORTED = 1; +localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT +localparam BPRED_NUM_LHR = 32'd6; +localparam BPRED_SIZE = 32'd6; +localparam BTB_SIZE = 32'd10; +localparam RAS_SIZE = 32'd16; + +localparam SVADU_SUPPORTED = 1; +localparam ZMMUL_SUPPORTED = 0; + +// FPU division architecture +localparam RADIX = 32'h2; +localparam DIVCOPIES = 32'h4; + +// bit manipulation +localparam ZBA_SUPPORTED = 1; +localparam ZBB_SUPPORTED = 1; +localparam ZBC_SUPPORTED = 1; +localparam ZBS_SUPPORTED = 1; + +// New compressed instructions +localparam ZCB_SUPPORTED = 1; +localparam ZCA_SUPPORTED = 0; +localparam ZCF_SUPPORTED = 0; +localparam ZCD_SUPPORTED = 0; + +// Memory synthesis configuration +localparam USE_SRAM = 0; + +`include "config-shared.vh" diff --git a/config/rv64gc_2_4i/config.vh b/config/rv64gc_2_4i/config.vh new file mode 100644 index 000000000..a532d6d27 --- /dev/null +++ b/config/rv64gc_2_4i/config.vh @@ -0,0 +1,179 @@ +////////////////////////////////////////// +// config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "BranchPredictorType.vh" + +// RV32 or RV64: XLEN = 32 or 64 +localparam XLEN = 32'd64; + +// IEEE 754 compliance +localparam IEEE754 = 0; + +// MISA RISC-V configuration per specification +localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0); +localparam ZICSR_SUPPORTED = 1; +localparam ZIFENCEI_SUPPORTED = 1; +localparam COUNTERS = 12'd32; +localparam ZICNTR_SUPPORTED = 1; +localparam ZIHPM_SUPPORTED = 1; +localparam ZFH_SUPPORTED = 0; +localparam SSTC_SUPPORTED = 1; +localparam ZICBOM_SUPPORTED = 1; +localparam ZICBOZ_SUPPORTED = 1; +localparam ZICBOP_SUPPORTED = 1; +localparam ZICCLSM_SUPPORTED = 1; +localparam SVPBMT_SUPPORTED = 1; +localparam SVNAPOT_SUPPORTED = 1; +localparam SVINVAL_SUPPORTED = 1; + +// LSU microarchitectural Features +localparam BUS_SUPPORTED = 1; +localparam DCACHE_SUPPORTED = 1; +localparam ICACHE_SUPPORTED = 1; +localparam VIRTMEM_SUPPORTED = 1; +localparam VECTORED_INTERRUPTS_SUPPORTED = 1; +localparam BIGENDIAN_SUPPORTED = 1; + +// TLB configuration. Entries should be a power of 2 +localparam ITLB_ENTRIES = 32'd32; +localparam DTLB_ENTRIES = 32'd32; + +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines +localparam DCACHE_NUMWAYS = 32'd4; +localparam DCACHE_WAYSIZEINBYTES = 32'd4096; +localparam DCACHE_LINELENINBITS = 32'd512; +localparam ICACHE_NUMWAYS = 32'd4; +localparam ICACHE_WAYSIZEINBYTES = 32'd4096; +localparam ICACHE_LINELENINBITS = 32'd512; + +// Integer Divider Configuration +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +localparam IDIV_BITSPERCYCLE = 32'd4; +localparam IDIV_ON_FPU = 0; + +// Legal number of PMP entries are 0, 16, or 64 +localparam PMP_ENTRIES = 32'd16; + +// Address space +localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000; + +// Bus Interface width +localparam AHBW = 32'd64; + +// WFI Timeout Wait +localparam WFI_TIMEOUT_BIT = 32'd16; + +// Peripheral Physical Addresses +// Peripheral memory space extends from BASE to BASE+RANGE +// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits + +// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? +localparam DTIM_SUPPORTED = 1'b0; +localparam logic [63:0] DTIM_BASE = 64'h80000000; +localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; +localparam IROM_SUPPORTED = 1'b0; +localparam logic [63:0] IROM_BASE = 64'h80000000; +localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; +localparam BOOTROM_SUPPORTED = 1'b1; +localparam logic [63:0] BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder; +localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; +localparam BOOTROM_PRELOAD = 1'b0; +localparam UNCORE_RAM_SUPPORTED = 1'b1; +localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; +localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF; +localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam EXT_MEM_SUPPORTED = 1'b0; +localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; +localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; +localparam CLINT_SUPPORTED = 1'b1; +localparam logic [63:0] CLINT_BASE = 64'h02000000; +localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF; +localparam GPIO_SUPPORTED = 1'b1; +localparam logic [63:0] GPIO_BASE = 64'h10060000; +localparam logic [63:0] GPIO_RANGE = 64'h000000FF; +localparam UART_SUPPORTED = 1'b1; +localparam logic [63:0] UART_BASE = 64'h10000000; +localparam logic [63:0] UART_RANGE = 64'h00000007; +localparam PLIC_SUPPORTED = 1'b1; +localparam logic [63:0] PLIC_BASE = 64'h0C000000; +localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; +localparam SDC_SUPPORTED = 1'b0; +localparam logic [63:0] SDC_BASE = 64'h00013000; +localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam SPI_SUPPORTED = 1'b1; +localparam logic [63:0] SPI_BASE = 64'h10040000; +localparam logic [63:0] SPI_RANGE = 64'h00000FFF; + +// Test modes + +// Tie GPIO outputs back to inputs +localparam GPIO_LOOPBACK_TEST = 1; +localparam SPI_LOOPBACK_TEST = 1; + +// Hardware configuration +localparam UART_PRESCALE = 32'd1; + +// Interrupt configuration +localparam PLIC_NUM_SRC = 32'd10; +// comment out the following if >=32 sources +localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); +localparam PLIC_GPIO_ID = 32'd3; +localparam PLIC_UART_ID = 32'd10; +localparam PLIC_SPI_ID = 32'd6; +localparam PLIC_SDC_ID = 32'd9; + +localparam BPRED_SUPPORTED = 1; +localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT +localparam BPRED_NUM_LHR = 32'd6; +localparam BPRED_SIZE = 32'd6; +localparam BTB_SIZE = 32'd10; +localparam RAS_SIZE = 32'd16; + +localparam SVADU_SUPPORTED = 1; +localparam ZMMUL_SUPPORTED = 0; + +// FPU division architecture +localparam RADIX = 32'h2; +localparam DIVCOPIES = 32'h4; + +// bit manipulation +localparam ZBA_SUPPORTED = 1; +localparam ZBB_SUPPORTED = 1; +localparam ZBC_SUPPORTED = 1; +localparam ZBS_SUPPORTED = 1; + +// New compressed instructions +localparam ZCB_SUPPORTED = 1; +localparam ZCA_SUPPORTED = 0; +localparam ZCF_SUPPORTED = 0; +localparam ZCD_SUPPORTED = 0; + +// Memory synthesis configuration +localparam USE_SRAM = 0; + +`include "config-shared.vh" diff --git a/config/rv64gc_4_1/config.vh b/config/rv64gc_4_1/config.vh new file mode 100644 index 000000000..ff87cf854 --- /dev/null +++ b/config/rv64gc_4_1/config.vh @@ -0,0 +1,179 @@ +////////////////////////////////////////// +// config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "BranchPredictorType.vh" + +// RV32 or RV64: XLEN = 32 or 64 +localparam XLEN = 32'd64; + +// IEEE 754 compliance +localparam IEEE754 = 0; + +// MISA RISC-V configuration per specification +localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0); +localparam ZICSR_SUPPORTED = 1; +localparam ZIFENCEI_SUPPORTED = 1; +localparam COUNTERS = 12'd32; +localparam ZICNTR_SUPPORTED = 1; +localparam ZIHPM_SUPPORTED = 1; +localparam ZFH_SUPPORTED = 0; +localparam SSTC_SUPPORTED = 1; +localparam ZICBOM_SUPPORTED = 1; +localparam ZICBOZ_SUPPORTED = 1; +localparam ZICBOP_SUPPORTED = 1; +localparam ZICCLSM_SUPPORTED = 1; +localparam SVPBMT_SUPPORTED = 1; +localparam SVNAPOT_SUPPORTED = 1; +localparam SVINVAL_SUPPORTED = 1; + +// LSU microarchitectural Features +localparam BUS_SUPPORTED = 1; +localparam DCACHE_SUPPORTED = 1; +localparam ICACHE_SUPPORTED = 1; +localparam VIRTMEM_SUPPORTED = 1; +localparam VECTORED_INTERRUPTS_SUPPORTED = 1; +localparam BIGENDIAN_SUPPORTED = 1; + +// TLB configuration. Entries should be a power of 2 +localparam ITLB_ENTRIES = 32'd32; +localparam DTLB_ENTRIES = 32'd32; + +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines +localparam DCACHE_NUMWAYS = 32'd4; +localparam DCACHE_WAYSIZEINBYTES = 32'd4096; +localparam DCACHE_LINELENINBITS = 32'd512; +localparam ICACHE_NUMWAYS = 32'd4; +localparam ICACHE_WAYSIZEINBYTES = 32'd4096; +localparam ICACHE_LINELENINBITS = 32'd512; + +// Integer Divider Configuration +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +localparam IDIV_BITSPERCYCLE = 32'd4; +localparam IDIV_ON_FPU = 1; + +// Legal number of PMP entries are 0, 16, or 64 +localparam PMP_ENTRIES = 32'd16; + +// Address space +localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000; + +// Bus Interface width +localparam AHBW = 32'd64; + +// WFI Timeout Wait +localparam WFI_TIMEOUT_BIT = 32'd16; + +// Peripheral Physical Addresses +// Peripheral memory space extends from BASE to BASE+RANGE +// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits + +// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? +localparam DTIM_SUPPORTED = 1'b0; +localparam logic [63:0] DTIM_BASE = 64'h80000000; +localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; +localparam IROM_SUPPORTED = 1'b0; +localparam logic [63:0] IROM_BASE = 64'h80000000; +localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; +localparam BOOTROM_SUPPORTED = 1'b1; +localparam logic [63:0] BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder; +localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; +localparam BOOTROM_PRELOAD = 1'b0; +localparam UNCORE_RAM_SUPPORTED = 1'b1; +localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; +localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF; +localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam EXT_MEM_SUPPORTED = 1'b0; +localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; +localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; +localparam CLINT_SUPPORTED = 1'b1; +localparam logic [63:0] CLINT_BASE = 64'h02000000; +localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF; +localparam GPIO_SUPPORTED = 1'b1; +localparam logic [63:0] GPIO_BASE = 64'h10060000; +localparam logic [63:0] GPIO_RANGE = 64'h000000FF; +localparam UART_SUPPORTED = 1'b1; +localparam logic [63:0] UART_BASE = 64'h10000000; +localparam logic [63:0] UART_RANGE = 64'h00000007; +localparam PLIC_SUPPORTED = 1'b1; +localparam logic [63:0] PLIC_BASE = 64'h0C000000; +localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; +localparam SDC_SUPPORTED = 1'b0; +localparam logic [63:0] SDC_BASE = 64'h00013000; +localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam SPI_SUPPORTED = 1'b1; +localparam logic [63:0] SPI_BASE = 64'h10040000; +localparam logic [63:0] SPI_RANGE = 64'h00000FFF; + +// Test modes + +// Tie GPIO outputs back to inputs +localparam GPIO_LOOPBACK_TEST = 1; +localparam SPI_LOOPBACK_TEST = 1; + +// Hardware configuration +localparam UART_PRESCALE = 32'd1; + +// Interrupt configuration +localparam PLIC_NUM_SRC = 32'd10; +// comment out the following if >=32 sources +localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); +localparam PLIC_GPIO_ID = 32'd3; +localparam PLIC_UART_ID = 32'd10; +localparam PLIC_SPI_ID = 32'd6; +localparam PLIC_SDC_ID = 32'd9; + +localparam BPRED_SUPPORTED = 1; +localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT +localparam BPRED_NUM_LHR = 32'd6; +localparam BPRED_SIZE = 32'd6; +localparam BTB_SIZE = 32'd10; +localparam RAS_SIZE = 32'd16; + +localparam SVADU_SUPPORTED = 1; +localparam ZMMUL_SUPPORTED = 0; + +// FPU division architecture +localparam RADIX = 32'h2; +localparam DIVCOPIES = 32'h1; + +// bit manipulation +localparam ZBA_SUPPORTED = 1; +localparam ZBB_SUPPORTED = 1; +localparam ZBC_SUPPORTED = 1; +localparam ZBS_SUPPORTED = 1; + +// New compressed instructions +localparam ZCB_SUPPORTED = 1; +localparam ZCA_SUPPORTED = 0; +localparam ZCF_SUPPORTED = 0; +localparam ZCD_SUPPORTED = 0; + +// Memory synthesis configuration +localparam USE_SRAM = 0; + +`include "config-shared.vh" diff --git a/config/rv64gc_4_1i/config.vh b/config/rv64gc_4_1i/config.vh new file mode 100644 index 000000000..5e71ad5a4 --- /dev/null +++ b/config/rv64gc_4_1i/config.vh @@ -0,0 +1,179 @@ +////////////////////////////////////////// +// config.vh +// +// Written: David_Harris@hmc.edu 4 January 2021 +// Modified: +// +// Purpose: Specify which features are configured +// Macros to determine which modes are supported based on MISA +// +// A component of the Wally configurable RISC-V project. +// +// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file +// except in compliance with the License, or, at your option, the Apache License version 2.0. You +// may obtain a copy of the License at +// +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work distributed under the +// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, +// either express or implied. See the License for the specific language governing permissions +// and limitations under the License. +//////////////////////////////////////////////////////////////////////////////////////////////// + +`include "BranchPredictorType.vh" + +// RV32 or RV64: XLEN = 32 or 64 +localparam XLEN = 32'd64; + +// IEEE 754 compliance +localparam IEEE754 = 0; + +// MISA RISC-V configuration per specification +localparam MISA = (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0); +localparam ZICSR_SUPPORTED = 1; +localparam ZIFENCEI_SUPPORTED = 1; +localparam COUNTERS = 12'd32; +localparam ZICNTR_SUPPORTED = 1; +localparam ZIHPM_SUPPORTED = 1; +localparam ZFH_SUPPORTED = 0; +localparam SSTC_SUPPORTED = 1; +localparam ZICBOM_SUPPORTED = 1; +localparam ZICBOZ_SUPPORTED = 1; +localparam ZICBOP_SUPPORTED = 1; +localparam ZICCLSM_SUPPORTED = 1; +localparam SVPBMT_SUPPORTED = 1; +localparam SVNAPOT_SUPPORTED = 1; +localparam SVINVAL_SUPPORTED = 1; + +// LSU microarchitectural Features +localparam BUS_SUPPORTED = 1; +localparam DCACHE_SUPPORTED = 1; +localparam ICACHE_SUPPORTED = 1; +localparam VIRTMEM_SUPPORTED = 1; +localparam VECTORED_INTERRUPTS_SUPPORTED = 1; +localparam BIGENDIAN_SUPPORTED = 1; + +// TLB configuration. Entries should be a power of 2 +localparam ITLB_ENTRIES = 32'd32; +localparam DTLB_ENTRIES = 32'd32; + +// Cache configuration. Sizes should be a power of two +// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines +localparam DCACHE_NUMWAYS = 32'd4; +localparam DCACHE_WAYSIZEINBYTES = 32'd4096; +localparam DCACHE_LINELENINBITS = 32'd512; +localparam ICACHE_NUMWAYS = 32'd4; +localparam ICACHE_WAYSIZEINBYTES = 32'd4096; +localparam ICACHE_LINELENINBITS = 32'd512; + +// Integer Divider Configuration +// IDIV_BITSPERCYCLE must be 1, 2, or 4 +localparam IDIV_BITSPERCYCLE = 32'd4; +localparam IDIV_ON_FPU = 0; + +// Legal number of PMP entries are 0, 16, or 64 +localparam PMP_ENTRIES = 32'd16; + +// Address space +localparam logic [63:0] RESET_VECTOR = 64'h0000000080000000; + +// Bus Interface width +localparam AHBW = 32'd64; + +// WFI Timeout Wait +localparam WFI_TIMEOUT_BIT = 32'd16; + +// Peripheral Physical Addresses +// Peripheral memory space extends from BASE to BASE+RANGE +// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits + +// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? +localparam DTIM_SUPPORTED = 1'b0; +localparam logic [63:0] DTIM_BASE = 64'h80000000; +localparam logic [63:0] DTIM_RANGE = 64'h007FFFFF; +localparam IROM_SUPPORTED = 1'b0; +localparam logic [63:0] IROM_BASE = 64'h80000000; +localparam logic [63:0] IROM_RANGE = 64'h007FFFFF; +localparam BOOTROM_SUPPORTED = 1'b1; +localparam logic [63:0] BOOTROM_BASE = 64'h00001000; // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder; +localparam logic [63:0] BOOTROM_RANGE = 64'h00000FFF; +localparam BOOTROM_PRELOAD = 1'b0; +localparam UNCORE_RAM_SUPPORTED = 1'b1; +localparam logic [63:0] UNCORE_RAM_BASE = 64'h80000000; +localparam logic [63:0] UNCORE_RAM_RANGE = 64'h7FFFFFFF; +localparam UNCORE_RAM_PRELOAD = 1'b0; +localparam EXT_MEM_SUPPORTED = 1'b0; +localparam logic [63:0] EXT_MEM_BASE = 64'h80000000; +localparam logic [63:0] EXT_MEM_RANGE = 64'h07FFFFFF; +localparam CLINT_SUPPORTED = 1'b1; +localparam logic [63:0] CLINT_BASE = 64'h02000000; +localparam logic [63:0] CLINT_RANGE = 64'h0000FFFF; +localparam GPIO_SUPPORTED = 1'b1; +localparam logic [63:0] GPIO_BASE = 64'h10060000; +localparam logic [63:0] GPIO_RANGE = 64'h000000FF; +localparam UART_SUPPORTED = 1'b1; +localparam logic [63:0] UART_BASE = 64'h10000000; +localparam logic [63:0] UART_RANGE = 64'h00000007; +localparam PLIC_SUPPORTED = 1'b1; +localparam logic [63:0] PLIC_BASE = 64'h0C000000; +localparam logic [63:0] PLIC_RANGE = 64'h03FFFFFF; +localparam SDC_SUPPORTED = 1'b0; +localparam logic [63:0] SDC_BASE = 64'h00013000; +localparam logic [63:0] SDC_RANGE = 64'h0000007F; +localparam SPI_SUPPORTED = 1'b1; +localparam logic [63:0] SPI_BASE = 64'h10040000; +localparam logic [63:0] SPI_RANGE = 64'h00000FFF; + +// Test modes + +// Tie GPIO outputs back to inputs +localparam GPIO_LOOPBACK_TEST = 1; +localparam SPI_LOOPBACK_TEST = 1; + +// Hardware configuration +localparam UART_PRESCALE = 32'd1; + +// Interrupt configuration +localparam PLIC_NUM_SRC = 32'd10; +// comment out the following if >=32 sources +localparam PLIC_NUM_SRC_LT_32 = (PLIC_NUM_SRC < 32); +localparam PLIC_GPIO_ID = 32'd3; +localparam PLIC_UART_ID = 32'd10; +localparam PLIC_SPI_ID = 32'd6; +localparam PLIC_SDC_ID = 32'd9; + +localparam BPRED_SUPPORTED = 1; +localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT +localparam BPRED_NUM_LHR = 32'd6; +localparam BPRED_SIZE = 32'd6; +localparam BTB_SIZE = 32'd10; +localparam RAS_SIZE = 32'd16; + +localparam SVADU_SUPPORTED = 1; +localparam ZMMUL_SUPPORTED = 0; + +// FPU division architecture +localparam RADIX = 32'h4; +localparam DIVCOPIES = 32'h1; + +// bit manipulation +localparam ZBA_SUPPORTED = 1; +localparam ZBB_SUPPORTED = 1; +localparam ZBC_SUPPORTED = 1; +localparam ZBS_SUPPORTED = 1; + +// New compressed instructions +localparam ZCB_SUPPORTED = 1; +localparam ZCA_SUPPORTED = 0; +localparam ZCF_SUPPORTED = 0; +localparam ZCD_SUPPORTED = 0; + +// Memory synthesis configuration +localparam USE_SRAM = 0; + +`include "config-shared.vh" diff --git a/sim/regression-wally b/sim/regression-wally index 06f4ce777..ad5b6e9f8 100755 --- a/sim/regression-wally +++ b/sim/regression-wally @@ -66,6 +66,121 @@ def getBuildrootTC(boot): BRgrepstr=str(INSTR_LIMIT)+" instructions" return TestCase(name,variant="rv64gc",cmd=BRcmd,grepstr=BRgrepstr) +tests32gc_2_1 = ["arch32fdiv", "arch32ddiv"] +for test in tests32gc_2_1: + tc = TestCase( + name=test, + variant="rv32gc_2_1", + cmd="vsim > {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c < {} -c <>1+(P.XLEN/32)); adrindex = adrindex+1) dut.uncore.uncore.ram.ram.memory.RAM[adrindex] = '0; if(reset) begin // branch predictor must always be reset - if (P.BPRED_SUPPORTED) begin - // local history only - if (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR) - for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++) - dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0; - for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++) - dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; - for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++) - dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; + if (`BPRED_SUPPORTED_FLAG == 1) begin // hack to avoid listing hierarchical path when not instantiated + if (P.BPRED_SUPPORTED) begin + // local history only + if (P.BPRED_TYPE == `BP_LOCAL_AHEAD | P.BPRED_TYPE == `BP_LOCAL_REPAIR) + for(adrindex = 0; adrindex < 2**P.BPRED_NUM_LHR; adrindex++) + dut.core.ifu.bpred.bpred.Predictor.DirPredictor.BHT.mem[adrindex] = 0; + for(adrindex = 0; adrindex < 2**P.BTB_SIZE; adrindex++) + dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0; + for(adrindex = 0; adrindex < 2**P.BPRED_SIZE; adrindex++) + dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0; + end end end end diff --git a/testbench/tests.vh b/testbench/tests.vh index 46c553cc3..d89c768e8 100644 --- a/testbench/tests.vh +++ b/testbench/tests.vh @@ -1580,9 +1580,104 @@ string arch64zbs[] = '{ // "rv32i_m/F/src/fnmsub_b15-01.S" }; - string arch32f[] = '{ + string arch32fdiv[] = '{ `RISCVARCHTEST, "rv32i_m/F/src/fdiv_b20-01.S", + "rv32i_m/F/src/fdiv_b1-01.S", + "rv32i_m/F/src/fdiv_b2-01.S", + "rv32i_m/F/src/fdiv_b21-01.S", + "rv32i_m/F/src/fdiv_b3-01.S", + "rv32i_m/F/src/fdiv_b4-01.S", + "rv32i_m/F/src/fdiv_b5-01.S", + "rv32i_m/F/src/fdiv_b6-01.S", + "rv32i_m/F/src/fdiv_b7-01.S", + "rv32i_m/F/src/fdiv_b8-01.S", + "rv32i_m/F/src/fdiv_b9-01.S", + "rv32i_m/F/src/fsqrt_b1-01.S", + "rv32i_m/F/src/fsqrt_b20-01.S", + "rv32i_m/F/src/fsqrt_b2-01.S", + "rv32i_m/F/src/fsqrt_b3-01.S", + "rv32i_m/F/src/fsqrt_b4-01.S", + "rv32i_m/F/src/fsqrt_b5-01.S", + "rv32i_m/F/src/fsqrt_b7-01.S", + "rv32i_m/F/src/fsqrt_b8-01.S", + "rv32i_m/F/src/fsqrt_b9-01.S" + }; + + string arch32ddiv[] = '{ + `RISCVARCHTEST, + "rv32i_m/D/src/fdiv.d_b20-01.S", + "rv32i_m/D/src/fdiv.d_b1-01.S", + "rv32i_m/D/src/fdiv.d_b2-01.S", + "rv32i_m/D/src/fdiv.d_b21-01.S", + "rv32i_m/D/src/fdiv.d_b3-01.S", + "rv32i_m/D/src/fdiv.d_b4-01.S", + "rv32i_m/D/src/fdiv.d_b5-01.S", + "rv32i_m/D/src/fdiv.d_b6-01.S", + "rv32i_m/D/src/fdiv.d_b7-01.S", + "rv32i_m/D/src/fdiv.d_b8-01.S", + "rv32i_m/D/src/fdiv.d_b9-01.S", + "rv32i_m/D/src/fsqrt.d_b1-01.S", + "rv32i_m/D/src/fsqrt.d_b20-01.S", + "rv32i_m/D/src/fsqrt.d_b2-01.S", + "rv32i_m/D/src/fsqrt.d_b3-01.S", + "rv32i_m/D/src/fsqrt.d_b4-01.S", + "rv32i_m/D/src/fsqrt.d_b5-01.S", + "rv32i_m/D/src/fsqrt.d_b7-01.S", + "rv32i_m/D/src/fsqrt.d_b8-01.S", + "rv32i_m/D/src/fsqrt.d_b9-01.S" + }; + + string arch64fdiv[] = '{ + `RISCVARCHTEST, + "rv64i_m/F/src/fdiv_b20-01.S", + "rv64i_m/F/src/fdiv_b1-01.S", + "rv64i_m/F/src/fdiv_b2-01.S", + "rv64i_m/F/src/fdiv_b21-01.S", + "rv64i_m/F/src/fdiv_b3-01.S", + "rv64i_m/F/src/fdiv_b4-01.S", + "rv64i_m/F/src/fdiv_b5-01.S", + "rv64i_m/F/src/fdiv_b6-01.S", + "rv64i_m/F/src/fdiv_b7-01.S", + "rv64i_m/F/src/fdiv_b8-01.S", + "rv64i_m/F/src/fdiv_b9-01.S", + "rv64i_m/F/src/fsqrt_b1-01.S", + "rv64i_m/F/src/fsqrt_b20-01.S", + "rv64i_m/F/src/fsqrt_b2-01.S", + "rv64i_m/F/src/fsqrt_b3-01.S", + "rv64i_m/F/src/fsqrt_b4-01.S", + "rv64i_m/F/src/fsqrt_b5-01.S", + "rv64i_m/F/src/fsqrt_b7-01.S", + "rv64i_m/F/src/fsqrt_b8-01.S", + "rv64i_m/F/src/fsqrt_b9-01.S" + }; + + string arch64ddiv[] = '{ + `RISCVARCHTEST, + "rv64i_m/D/src/fdiv.d_b20-01.S", + "rv64i_m/D/src/fdiv.d_b1-01.S", + "rv64i_m/D/src/fdiv.d_b2-01.S", + "rv64i_m/D/src/fdiv.d_b21-01.S", + "rv64i_m/D/src/fdiv.d_b3-01.S", + "rv64i_m/D/src/fdiv.d_b4-01.S", + "rv64i_m/D/src/fdiv.d_b5-01.S", + "rv64i_m/D/src/fdiv.d_b6-01.S", + "rv64i_m/D/src/fdiv.d_b7-01.S", + "rv64i_m/D/src/fdiv.d_b8-01.S", + "rv64i_m/D/src/fdiv.d_b9-01.S", + "rv64i_m/D/src/fsqrt.d_b1-01.S", + "rv64i_m/D/src/fsqrt.d_b20-01.S", + "rv64i_m/D/src/fsqrt.d_b2-01.S", + "rv64i_m/D/src/fsqrt.d_b3-01.S", + "rv64i_m/D/src/fsqrt.d_b4-01.S", + "rv64i_m/D/src/fsqrt.d_b5-01.S", + "rv64i_m/D/src/fsqrt.d_b7-01.S", + "rv64i_m/D/src/fsqrt.d_b8-01.S", + "rv64i_m/D/src/fsqrt.d_b9-01.S" + }; + + string arch32f[] = '{ + `RISCVARCHTEST, "rv32i_m/F/src/fadd_b10-01.S", "rv32i_m/F/src/fadd_b1-01.S", "rv32i_m/F/src/fadd_b11-01.S", @@ -1737,6 +1832,7 @@ string arch64zbs[] = '{ string arch32d[] = '{ `RISCVARCHTEST, + "rv32i_m/D/src/fsqrt.d_b1-01.S", "rv32i_m/D/src/fadd.d_b10-01.S", "rv32i_m/D/src/fadd.d_b1-01.S", "rv32i_m/D/src/fadd.d_b11-01.S",