diff --git a/pipelined/src/fpu/flags.sv b/pipelined/src/fpu/flags.sv
index 67fdb4935..73cc3ae35 100644
--- a/pipelined/src/fpu/flags.sv
+++ b/pipelined/src/fpu/flags.sv
@@ -50,7 +50,7 @@ module flags(
input logic [`NE+1:0] Me, // exponent of the normalized sum
input logic [1:0] CvtNegResMsbs, // the negitive integer result's most significant bits
input logic FmaAs, FmaPs, // the product and modified Z signs
- input logic R, UfL, S, UfPlus1, // bits used to determine rounding
+ input logic R, G, S, UfPlus1, // bits used to determine rounding
output logic DivByZero,
output logic IntInvalid, Invalid, Overflow, // flags used to select the res
output logic [4:0] PostProcFlg // flags
@@ -126,16 +126,16 @@ module flags(
// | | | | and if the result is not exact
// | | | | | and if the input isnt infinity or NaN
// | | | | | |
- assign Underflow = ((FullRe[`NE+1] | (FullRe == 0) | ((FullRe == 1) & (Me == 0) & ~(UfPlus1&UfL)))&(R|S))&~(InfIn|NaNIn|DivByZero|Invalid);
+ assign Underflow = ((FullRe[`NE+1] | (FullRe == 0) | ((FullRe == 1) & (Me == 0) & ~(UfPlus1&G)))&(R|S|G))&~(InfIn|NaNIn|DivByZero|Invalid);
// Set Inexact flag if the res is diffrent from what would be outputed given infinite precision
// - Don't set the underflow flag if an underflowed res isn't outputed
- assign FpInexact = (S|Overflow|R)&~(InfIn|NaNIn|DivByZero|Invalid);
+ assign FpInexact = (S|G|Overflow|R)&~(InfIn|NaNIn|DivByZero|Invalid);
// if the res is too small to be represented and not 0
// | and if the res is not invalid (outside the integer bounds)
// | |
- assign IntInexact = ((CvtCe[`NE]&~XZero)|S|R)&~IntInvalid;
+ assign IntInexact = ((CvtCe[`NE]&~XZero)|S|R|G)&~IntInvalid;
// select the inexact flag to output
assign Inexact = ToInt ? IntInexact : FpInexact;
diff --git a/pipelined/src/fpu/postprocess.sv b/pipelined/src/fpu/postprocess.sv
index f96101443..8039f7c37 100644
--- a/pipelined/src/fpu/postprocess.sv
+++ b/pipelined/src/fpu/postprocess.sv
@@ -83,15 +83,13 @@ module postprocess (
logic [`NE+1:0] Me;
logic [`CORRSHIFTSZ-1:0] Mf; // corectly shifted fraction
logic [`NE+1:0] FullRe; // Re with bits to determine sign and overflow
- logic S; // S bit
logic UfPlus1; // do you add one (for determining underflow flag)
- logic R; // bits needed to determine rounding
logic [$clog2(`NORMSHIFTSZ)-1:0] ShiftAmt; // normalization shift count
logic [`NORMSHIFTSZ-1:0] ShiftIn; // is the sum zero
logic [`NORMSHIFTSZ-1:0] Shifted; // the shifted result
logic Plus1; // add one to the final result?
logic IntInvalid, Overflow, Invalid; // flags
- logic UfL;
+ logic G, R, S; // bits needed to determine rounding
logic [`FMTBITS-1:0] OutFmt;
// fma signals
logic [`NE+1:0] FmaMe; // exponent of the normalized sum
@@ -201,16 +199,16 @@ module postprocess (
roundsign roundsign(.FmaPs, .FmaAs, .FmaInvA, .FmaOp, .DivOp, .CvtOp, .FmaNegSum,
.Sqrt, .FmaSs, .Xs, .Ys, .CvtCs, .Ms);
- round round(.OutFmt, .Frm, .S, .FmaZmS, .Plus1, .PostProcSel, .CvtCe, .Qe,
+ round round(.OutFmt, .Frm, .FmaZmS, .Plus1, .PostProcSel, .CvtCe, .Qe,
.Ms, .FmaMe, .FmaOp, .CvtOp, .CvtResDenormUf, .Mf, .ToInt, .CvtResUf,
.DivS, .DivDone,
- .DivOp, .UfPlus1, .FullRe, .Rf, .Re, .R, .UfL, .Me);
+ .DivOp, .UfPlus1, .FullRe, .Rf, .Re, .S, .R, .G, .Me);
///////////////////////////////////////////////////////////////////////////////
// Sign calculation
///////////////////////////////////////////////////////////////////////////////
- resultsign resultsign(.Frm, .FmaPs, .FmaAs, .FmaMe, .R, .S,
+ resultsign resultsign(.Frm, .FmaPs, .FmaAs, .FmaMe, .R, .S, .G,
.FmaOp, .ZInf, .InfIn, .FmaSZero, .Mult, .Ms, .Ws);
///////////////////////////////////////////////////////////////////////////////
@@ -220,7 +218,7 @@ module postprocess (
flags flags(.XSNaN, .YSNaN, .ZSNaN, .XInf, .YInf, .ZInf, .InfIn, .XZero, .YZero,
.Xs, .Sqrt, .ToInt, .IntToFp, .Int64, .Signed, .OutFmt, .CvtCe,
.NaNIn, .FmaAs, .FmaPs, .R, .IntInvalid, .DivByZero,
- .UfL, .S, .UfPlus1, .CvtOp, .DivOp, .FmaOp, .FullRe, .Plus1,
+ .G, .S, .UfPlus1, .CvtOp, .DivOp, .FmaOp, .FullRe, .Plus1,
.Me, .CvtNegResMsbs, .Invalid, .Overflow, .PostProcFlg);
///////////////////////////////////////////////////////////////////////////////
diff --git a/pipelined/src/fpu/resultsign.sv b/pipelined/src/fpu/resultsign.sv
index c2912ece7..8d6dbb6e9 100644
--- a/pipelined/src/fpu/resultsign.sv
+++ b/pipelined/src/fpu/resultsign.sv
@@ -39,6 +39,7 @@ module resultsign(
input logic Mult,
input logic R,
input logic S,
+ input logic G,
input logic Ms,
output logic Ws
);
@@ -60,7 +61,7 @@ module resultsign(
// - if a multiply opperation is done, then use the products sign(Ps)
// - if the zero sum is not exactly zero i.e. R|S use the sign of the exact result (which is the product's sign)
// - if an effective addition occurs (P+A or -P+-A or P--A) then use the product's sign
- assign Zeros = (FmaPs^FmaAs)&~(R|S)&~Mult ? Frm[1:0] == 2'b10 : FmaPs;
+ assign Zeros = (FmaPs^FmaAs)&~(R|G|S)&~Mult ? Frm[1:0] == 2'b10 : FmaPs;
// is the result negitive
diff --git a/pipelined/src/fpu/round.sv b/pipelined/src/fpu/round.sv
index 0943413bd..d33d894a9 100644
--- a/pipelined/src/fpu/round.sv
+++ b/pipelined/src/fpu/round.sv
@@ -60,16 +60,14 @@ module round(
output logic S, // sticky bit
output logic [`NE+1:0] Me,
output logic Plus1,
- output logic R, UfL // bits needed to calculate rounding
+ output logic R, G // bits needed to calculate rounding
);
- logic L; // bit used for rounding - least significant bit of the normalized sum
logic UfCalcPlus1;
logic NormS; // normalized sum's sticky bit
- logic UfS; // sticky bit for underlow calculation
logic [`NF-1:0] RoundFrac;
logic FpRes, IntRes;
- logic UfR;
- logic FpRound, FpLSBRes, FpUfRound;
+ logic FpG, FpL, FpR;
+ logic L; // lsb of result
logic CalcPlus1, FpPlus1;
logic [`FLEN:0] RoundAdd; // how much to add to the result
@@ -176,106 +174,101 @@ module round(
// only add the Addend sticky if doing an FMA opperation
// - the shifter shifts too far left when there's an underflow (shifting out all possible sticky bits)
- assign UfS = FmaZmS&FmaOp | NormS | CvtResUf&CvtOp | FmaMe[`NE+1]&FmaOp | DivS&DivOp;
+ assign S = FmaZmS&FmaOp | NormS | CvtResUf&CvtOp | FmaMe[`NE+1]&FmaOp | DivS&DivOp;
// determine round and LSB of the rounded value
// - underflow round bit is used to determint the underflow flag
if (`FPSIZES == 1) begin
- assign FpRound = Mf[`CORRSHIFTSZ-`NF-1];
- assign FpLSBRes = Mf[`CORRSHIFTSZ-`NF];
- assign FpUfRound = Mf[`CORRSHIFTSZ-`NF-2];
+ assign FpG = Mf[`CORRSHIFTSZ-`NF-1];
+ assign FpL = Mf[`CORRSHIFTSZ-`NF];
+ assign FpR = Mf[`CORRSHIFTSZ-`NF-2];
end else if (`FPSIZES == 2) begin
- assign FpRound = OutFmt ? Mf[`CORRSHIFTSZ-`NF-1] : Mf[`CORRSHIFTSZ-`NF1-1];
- assign FpLSBRes = OutFmt ? Mf[`CORRSHIFTSZ-`NF] : Mf[`CORRSHIFTSZ-`NF1];
- assign FpUfRound = OutFmt ? Mf[`CORRSHIFTSZ-`NF-2] : Mf[`CORRSHIFTSZ-`NF1-2];
+ assign FpG = OutFmt ? Mf[`CORRSHIFTSZ-`NF-1] : Mf[`CORRSHIFTSZ-`NF1-1];
+ assign FpL = OutFmt ? Mf[`CORRSHIFTSZ-`NF] : Mf[`CORRSHIFTSZ-`NF1];
+ assign FpR = OutFmt ? Mf[`CORRSHIFTSZ-`NF-2] : Mf[`CORRSHIFTSZ-`NF1-2];
end else if (`FPSIZES == 3) begin
always_comb
case (OutFmt)
`FMT: begin
- FpRound = Mf[`CORRSHIFTSZ-`NF-1];
- FpLSBRes = Mf[`CORRSHIFTSZ-`NF];
- FpUfRound = Mf[`CORRSHIFTSZ-`NF-2];
+ FpG = Mf[`CORRSHIFTSZ-`NF-1];
+ FpL = Mf[`CORRSHIFTSZ-`NF];
+ FpR = Mf[`CORRSHIFTSZ-`NF-2];
end
`FMT1: begin
- FpRound = Mf[`CORRSHIFTSZ-`NF1-1];
- FpLSBRes = Mf[`CORRSHIFTSZ-`NF1];
- FpUfRound = Mf[`CORRSHIFTSZ-`NF1-2];
+ FpG = Mf[`CORRSHIFTSZ-`NF1-1];
+ FpL = Mf[`CORRSHIFTSZ-`NF1];
+ FpR = Mf[`CORRSHIFTSZ-`NF1-2];
end
`FMT2: begin
- FpRound = Mf[`CORRSHIFTSZ-`NF2-1];
- FpLSBRes = Mf[`CORRSHIFTSZ-`NF2];
- FpUfRound = Mf[`CORRSHIFTSZ-`NF2-2];
+ FpG = Mf[`CORRSHIFTSZ-`NF2-1];
+ FpL = Mf[`CORRSHIFTSZ-`NF2];
+ FpR = Mf[`CORRSHIFTSZ-`NF2-2];
end
default: begin
- FpRound = 1'bx;
- FpLSBRes = 1'bx;
- FpUfRound = 1'bx;
+ FpG = 1'bx;
+ FpL = 1'bx;
+ FpR = 1'bx;
end
endcase
end else if (`FPSIZES == 4) begin
always_comb
case (OutFmt)
2'h3: begin
- FpRound = Mf[`CORRSHIFTSZ-`Q_NF-1];
- FpLSBRes = Mf[`CORRSHIFTSZ-`Q_NF];
- FpUfRound = Mf[`CORRSHIFTSZ-`Q_NF-2];
+ FpG = Mf[`CORRSHIFTSZ-`Q_NF-1];
+ FpL = Mf[`CORRSHIFTSZ-`Q_NF];
+ FpR = Mf[`CORRSHIFTSZ-`Q_NF-2];
end
2'h1: begin
- FpRound = Mf[`CORRSHIFTSZ-`D_NF-1];
- FpLSBRes = Mf[`CORRSHIFTSZ-`D_NF];
- FpUfRound = Mf[`CORRSHIFTSZ-`D_NF-2];
+ FpG = Mf[`CORRSHIFTSZ-`D_NF-1];
+ FpL = Mf[`CORRSHIFTSZ-`D_NF];
+ FpR = Mf[`CORRSHIFTSZ-`D_NF-2];
end
2'h0: begin
- FpRound = Mf[`CORRSHIFTSZ-`S_NF-1];
- FpLSBRes = Mf[`CORRSHIFTSZ-`S_NF];
- FpUfRound = Mf[`CORRSHIFTSZ-`S_NF-2];
+ FpG = Mf[`CORRSHIFTSZ-`S_NF-1];
+ FpL = Mf[`CORRSHIFTSZ-`S_NF];
+ FpR = Mf[`CORRSHIFTSZ-`S_NF-2];
end
2'h2: begin
- FpRound = Mf[`CORRSHIFTSZ-`H_NF-1];
- FpLSBRes = Mf[`CORRSHIFTSZ-`H_NF];
- FpUfRound = Mf[`CORRSHIFTSZ-`H_NF-2];
+ FpG = Mf[`CORRSHIFTSZ-`H_NF-1];
+ FpL = Mf[`CORRSHIFTSZ-`H_NF];
+ FpR = Mf[`CORRSHIFTSZ-`H_NF-2];
end
endcase
end
- assign R = ToInt&CvtOp ? Mf[`CORRSHIFTSZ-`XLEN-1] : FpRound;
- assign L = ToInt&CvtOp ? Mf[`CORRSHIFTSZ-`XLEN] : FpLSBRes;
- assign UfR = ToInt&CvtOp ? Mf[`CORRSHIFTSZ-`XLEN-2] : FpUfRound;
-
- // used to determine underflow flag
- assign UfL = FpRound;
- // determine sticky
- assign S = UfS | UfR;
+ assign G = ToInt&CvtOp ? Mf[`CORRSHIFTSZ-`XLEN-1] : FpG;
+ assign L = ToInt&CvtOp ? Mf[`CORRSHIFTSZ-`XLEN] : FpL;
+ assign R = ToInt&CvtOp ? Mf[`CORRSHIFTSZ-`XLEN-2] : FpR;
always_comb begin
// Determine if you add 1
case (Frm)
- 3'b000: CalcPlus1 = R & (S| L);//round to nearest even
+ 3'b000: CalcPlus1 = G & (R|S|L);//round to nearest even
3'b001: CalcPlus1 = 0;//round to zero
3'b010: CalcPlus1 = Ms;//round down
3'b011: CalcPlus1 = ~Ms;//round up
- 3'b100: CalcPlus1 = R;//round to nearest max magnitude
+ 3'b100: CalcPlus1 = G;//round to nearest max magnitude
default: CalcPlus1 = 1'bx;
endcase
// Determine if you add 1 (for underflow flag)
case (Frm)
- 3'b000: UfCalcPlus1 = UfR & (UfS| UfL);//round to nearest even
+ 3'b000: UfCalcPlus1 = R & (S|G);//round to nearest even
3'b001: UfCalcPlus1 = 0;//round to zero
3'b010: UfCalcPlus1 = Ms;//round down
3'b011: UfCalcPlus1 = ~Ms;//round up
- 3'b100: UfCalcPlus1 = UfR;//round to nearest max magnitude
+ 3'b100: UfCalcPlus1 = R;//round to nearest max magnitude
default: UfCalcPlus1 = 1'bx;
endcase
end
// If an answer is exact don't round
- assign Plus1 = CalcPlus1 & (S | R);
+ assign Plus1 = CalcPlus1 & (S|R|G);
assign FpPlus1 = Plus1&~(ToInt&CvtOp);
- assign UfPlus1 = UfCalcPlus1 & S; // UfR is part of sticky
+ assign UfPlus1 = UfCalcPlus1 & (S|R);
// Compute rounded result
if (`FPSIZES == 1) begin
diff --git a/pipelined/src/fpu/srtfsm.sv b/pipelined/src/fpu/srtfsm.sv
index a24fb526a..0e6ec51af 100644
--- a/pipelined/src/fpu/srtfsm.sv
+++ b/pipelined/src/fpu/srtfsm.sv
@@ -73,11 +73,11 @@ module srtfsm(
// radix-4 division can't create a QM that continually adds 0's
if (`RADIX == 2) begin
logic [`DIVb+3:0] FZero, FSticky;
- logic [`DIVb+3:0] LastK, FirstK;
- assign LastK = ({4'b1111, LastC} & ~({4'b1111, LastC} << 1));
- assign FirstK = ({4'b1111, FirstC<<1} & ~({4'b1111, FirstC<<1} << 1));
- assign FZero = SqrtM ? {{2{LastSM[`DIVb]}}, LastSM, 2'b0} | {LastK,1'b0} : {4'b1,D,{`DIVb-`DIVN+2{1'b0}}};
- assign FSticky = SqrtM ? {FirstSM, 2'b0} | {FirstK,1'b0} : {4'b1,D,{`DIVb-`DIVN+2{1'b0}}};
+ logic [`DIVb+2:0] LastK, FirstK;
+ assign LastK = ({3'b111, LastC} & ~({3'b111, LastC} << 1));
+ assign FirstK = ({3'b111, FirstC<<1} & ~({3'b111, FirstC<<1} << 1));
+ assign FZero = SqrtM ? {LastSM[`DIVb], LastSM, 2'b0} | {LastK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
+ assign FSticky = SqrtM ? {FirstSM[`DIVb], FirstSM, 2'b0} | {FirstK,1'b0} : {3'b1,D,{`DIVb-`DIVN+2{1'b0}}};
// *** |... for continual -1 is not efficent fix - also only needed for radix-2
assign WZero = ((NextWSN^NextWCN)=={NextWSN[`DIVb+2:0]|NextWCN[`DIVb+2:0], 1'b0})|(((NextWSN+NextWCN+FZero)==0)&qn[`DIVCOPIES-1]);
assign DivSE = |W&~((W+FSticky)==0); //***not efficent fix == and need the & qn