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Merge pull request #830 from davidharrishmc/dev

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Regression improvement and FPU simplification
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Rose Thompson 2024-06-11 13:18:11 -07:00 committed by GitHub
commit 46cc64b76f
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4 changed files with 54 additions and 38 deletions
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30
bin/regression-wally
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@ -99,6 +99,29 @@ derivconfigtests = [
["zaamo_rv32gc", ["arch32i", "arch32a_amo"]], ["zaamo_rv32gc", ["arch32i", "arch32a_amo"]],
["zalrsc_rv32gc", ["arch32i", "wally32a_lrsc"]], ["zalrsc_rv32gc", ["arch32i", "wally32a_lrsc"]],
# Bit manipulation and crypto variants
["zba_rv32gc", ["arch32i", "arch32zba"]],
["zbb_rv32gc", ["arch32i", "arch32zbb"]],
["zbc_rv32gc", ["arch32i", "arch32zbc"]],
["zbs_rv32gc", ["arch32i", "arch32zbs"]],
["zbkb_rv32gc", ["arch32i", "arch32zbkb"]],
["zbkc_rv32gc", ["arch32i", "arch32zbkc"]],
["zbkx_rv32gc", ["arch32i", "arch32zbkx"]],
["zkne_rv32gc", ["arch32i", "arch32zkne"]],
["zknd_rv32gc", ["arch32i", "arch32zknd"]],
["zknh_rv32gc", ["arch32i", "arch32zknh"]],
["zba_rv64gc", ["arch64i", "arch64zba"]],
["zbb_rv64gc", ["arch64i", "arch64zbb"]],
["zbc_rv64gc", ["arch64i", "arch64zbc"]],
["zbs_rv64gc", ["arch64i", "arch64zbs"]],
["zbkb_rv64gc", ["arch64i", "arch64zbkb"]],
["zbkc_rv64gc", ["arch64i", "arch64zbkc"]],
["zbkx_rv64gc", ["arch64i", "arch64zbkx"]],
["zkne_rv64gc", ["arch64i", "arch64zkne"]],
["zknd_rv64gc", ["arch64i", "arch64zknd"]],
["zknh_rv64gc", ["arch64i", "arch64zknh"]],
### add misaligned tests ### add misaligned tests
# fp/int divider permutations # fp/int divider permutations
@ -325,7 +348,8 @@ else:
# run derivative configurations in nightly regression # run derivative configurations in nightly regression
if (nightly): if (nightly):
addTests(tests_buildrootboot, defaultsim) # addTests(tests_buildrootboot, defaultsim)
addTests(tests_buildrootshort, defaultsim)
addTests(derivconfigtests, defaultsim) addTests(derivconfigtests, defaultsim)
else: else:
addTests(tests_buildrootshort, defaultsim) addTests(tests_buildrootshort, defaultsim)
@ -389,7 +413,7 @@ if (testfloat or nightly): # for nightly, run testfloat along with othres
tc = TestCase( tc = TestCase(
name=test, name=test,
variant=config, variant=config,
cmd="wsim --tb testbench_fp --sim questa " + config + " " + test + " > " + sim_log, cmd="wsim --tb testbench_fp " + config + " " + test + " > " + sim_log,
grepstr="All Tests completed with 0 errors", grepstr="All Tests completed with 0 errors",
grepfile = WALLY + "/sim/questa/logs/"+config+"_"+test+".log") grepfile = WALLY + "/sim/questa/logs/"+config+"_"+test+".log")
configs.append(tc) configs.append(tc)
@ -415,7 +439,7 @@ def main():
elif '--nightly' in sys.argv: elif '--nightly' in sys.argv:
TIMEOUT_DUR = 60*1440 # 1 day TIMEOUT_DUR = 60*1440 # 1 day
elif '--testfloat' in sys.argv: elif '--testfloat' in sys.argv:
TIMEOUT_DUR = 5*60 # seconds TIMEOUT_DUR = 30*60 # seconds
else: else:
TIMEOUT_DUR = 10*60 # seconds TIMEOUT_DUR = 10*60 # seconds

4
src/fpu/postproc/divshiftcalc.sv
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@ -28,10 +28,8 @@
//////////////////////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////////////////////
module divshiftcalc import cvw::*; #(parameter cvw_t P) ( module divshiftcalc import cvw::*; #(parameter cvw_t P) (
input logic [P.DIVb:0] DivUm, // divsqrt significand
input logic [P.NE+1:0] DivUe, // divsqrt exponent input logic [P.NE+1:0] DivUe, // divsqrt exponent
output logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt, // divsqrt shift amount output logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt, // divsqrt shift amount
output logic [P.NORMSHIFTSZ-1:0] DivShiftIn, // divsqrt shift input
output logic DivResSubnorm, // is the divsqrt result subnormal output logic DivResSubnorm, // is the divsqrt result subnormal
output logic DivSubnormShiftPos // is the subnormal shift amount positive output logic DivSubnormShiftPos // is the subnormal shift amount positive
); );
@ -68,6 +66,4 @@ module divshiftcalc import cvw::*; #(parameter cvw_t P) (
assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[P.LOGNORMSHIFTSZ-1:0] : '0; assign DivSubnormShiftAmt = DivSubnormShiftPos ? DivSubnormShift[P.LOGNORMSHIFTSZ-1:0] : '0;
assign DivShiftAmt = DivResSubnorm ? DivSubnormShiftAmt : NormShift; assign DivShiftAmt = DivResSubnorm ? DivSubnormShiftAmt : NormShift;
// pre-shift the divider result for normalization
assign DivShiftIn = {{P.NF{1'b0}}, DivUm, {P.NORMSHIFTSZ-P.DIVb-1-P.NF{1'b0}}};
endmodule endmodule

28
src/fpu/postproc/fmashiftcalc.sv
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@ -35,8 +35,7 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) (
output logic [P.NE+1:0] NormSumExp, // exponent of the normalized sum not taking into account Subnormal or zero results output logic [P.NE+1:0] NormSumExp, // exponent of the normalized sum not taking into account Subnormal or zero results
output logic FmaSZero, // is the sum zero output logic FmaSZero, // is the sum zero
output logic FmaPreResultSubnorm, // is the result subnormal - calculated before LZA corection output logic FmaPreResultSubnorm, // is the result subnormal - calculated before LZA corection
output logic [$clog2(P.FMALEN+1)-1:0] FmaShiftAmt, // normalization shift count output logic [$clog2(P.FMALEN+1)-1:0] FmaShiftAmt // normalization shift count
output logic [P.FMALEN+1:0] FmaShiftIn
); );
logic [P.NE+1:0] PreNormSumExp; // the exponent of the normalized sum with the P.FLEN bias logic [P.NE+1:0] PreNormSumExp; // the exponent of the normalized sum with the P.FLEN bias
logic [P.NE+1:0] BiasCorr; // correction for bias logic [P.NE+1:0] BiasCorr; // correction for bias
@ -54,6 +53,7 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) (
//convert the sum's exponent into the proper precision //convert the sum's exponent into the proper precision
if (P.FPSIZES == 1) begin if (P.FPSIZES == 1) begin
assign NormSumExp = PreNormSumExp; assign NormSumExp = PreNormSumExp;
assign BiasCorr = '0;
end else if (P.FPSIZES == 2) begin end else if (P.FPSIZES == 2) begin
assign BiasCorr = Fmt ? (P.NE+2)'(0) : (P.NE+2)'(P.BIAS1-P.BIAS); assign BiasCorr = Fmt ? (P.NE+2)'(0) : (P.NE+2)'(P.BIAS1-P.BIAS);
assign NormSumExp = PreNormSumExp+BiasCorr; assign NormSumExp = PreNormSumExp+BiasCorr;
@ -79,19 +79,19 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) (
assign NormSumExp = PreNormSumExp+BiasCorr; assign NormSumExp = PreNormSumExp+BiasCorr;
end end
// determine if the result is subnormal: (NormSumExp <= 0) & (NormSumExp >= -FracLen) & ~FmaSZero // determine if the result is subnormal: (NormSumExp <= 0) & (NormSumExp >= -FracLen)
if (P.FPSIZES == 1) begin if (P.FPSIZES == 1) begin
logic Sum0LEZ, Sum0GEFL; logic Sum0LEZ, Sum0GEFL;
assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp; assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); // changed from -2 dh 4/3/24 for issue 655 assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); // changed from -2 dh 4/3/24 for issue 655
assign FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero; assign FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL;
end else if (P.FPSIZES == 2) begin end else if (P.FPSIZES == 2) begin
logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL; logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL;
assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp; assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); // changed from -2 dh 4/3/24 for issue 655 assign Sum0GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF-1)); // changed from -2 dh 4/3/24 for issue 655
assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS1)); assign Sum1LEZ = $signed(PreNormSumExp) <= $signed((P.NE+2)'(P.BIAS-P.BIAS1));
assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-1+P.BIAS-P.BIAS1)) | ~|PreNormSumExp; assign Sum1GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF1-1+P.BIAS-P.BIAS1)) | ~|PreNormSumExp;
assign FmaPreResultSubnorm = (Fmt ? Sum0LEZ : Sum1LEZ) & (Fmt ? Sum0GEFL : Sum1GEFL) & ~FmaSZero; assign FmaPreResultSubnorm = (Fmt ? Sum0LEZ : Sum1LEZ) & (Fmt ? Sum0GEFL : Sum1GEFL);
end else if (P.FPSIZES == 3) begin end else if (P.FPSIZES == 3) begin
logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL; logic Sum0LEZ, Sum0GEFL, Sum1LEZ, Sum1GEFL, Sum2LEZ, Sum2GEFL;
assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp; assign Sum0LEZ = PreNormSumExp[P.NE+1] | ~|PreNormSumExp;
@ -102,9 +102,9 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) (
assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF2-1+P.BIAS-P.BIAS2)) | ~|PreNormSumExp; assign Sum2GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.NF2-1+P.BIAS-P.BIAS2)) | ~|PreNormSumExp;
always_comb begin always_comb begin
case (Fmt) case (Fmt)
P.FMT: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL; // & ~FmaSZero; // checking sum is not zero is harmless but turns out to be unnecessary P.FMT: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL;
P.FMT1: FmaPreResultSubnorm = Sum1LEZ & Sum1GEFL; // & ~FmaSZero; P.FMT1: FmaPreResultSubnorm = Sum1LEZ & Sum1GEFL;
P.FMT2: FmaPreResultSubnorm = Sum2LEZ & Sum2GEFL; // & ~FmaSZero; P.FMT2: FmaPreResultSubnorm = Sum2LEZ & Sum2GEFL;
default: FmaPreResultSubnorm = 1'bx; default: FmaPreResultSubnorm = 1'bx;
endcase endcase
end end
@ -120,17 +120,15 @@ module fmashiftcalc import cvw::*; #(parameter cvw_t P) (
assign Sum3GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.H_NF-1+P.BIAS-P.H_BIAS)) | ~|PreNormSumExp; assign Sum3GEFL = $signed(PreNormSumExp) >= $signed((P.NE+2)'(-P.H_NF-1+P.BIAS-P.H_BIAS)) | ~|PreNormSumExp;
always_comb begin always_comb begin
case (Fmt) case (Fmt)
2'h3: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL & ~FmaSZero; 2'h3: FmaPreResultSubnorm = Sum0LEZ & Sum0GEFL;
2'h1: FmaPreResultSubnorm = Sum1LEZ & Sum1GEFL & ~FmaSZero; 2'h1: FmaPreResultSubnorm = Sum1LEZ & Sum1GEFL;
2'h0: FmaPreResultSubnorm = Sum2LEZ & Sum2GEFL & ~FmaSZero; 2'h0: FmaPreResultSubnorm = Sum2LEZ & Sum2GEFL;
2'h2: FmaPreResultSubnorm = Sum3LEZ & Sum3GEFL & ~FmaSZero; 2'h2: FmaPreResultSubnorm = Sum3LEZ & Sum3GEFL;
endcase endcase
end end
end end
// set and calculate the shift input and amount // set and calculate the shift input and amount
// - shift once if killing a product and the result is subnormal // - shift once if killing a product and the result is subnormal
assign FmaShiftIn = {2'b0, FmaSm}; assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(P.FMALEN-1)-1:0]+($clog2(P.FMALEN-1))'(P.NF+3)+BiasCorr[$clog2(P.FMALEN-1)-1:0]: FmaSCnt+1;
if (P.FPSIZES == 1) assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(P.FMALEN-1)-1:0]+($clog2(P.FMALEN-1))'(P.NF+3): FmaSCnt+1;
else assign FmaShiftAmt = FmaPreResultSubnorm ? FmaSe[$clog2(P.FMALEN-1)-1:0]+($clog2(P.FMALEN-1))'(P.NF+3)+BiasCorr[$clog2(P.FMALEN-1)-1:0]: FmaSCnt+1;
endmodule endmodule

12
src/fpu/postproc/postprocess.sv
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@ -86,13 +86,11 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
// fma signals // fma signals
logic [P.NE+1:0] FmaMe; // exponent of the normalized sum logic [P.NE+1:0] FmaMe; // exponent of the normalized sum
logic FmaSZero; // is the sum zero logic FmaSZero; // is the sum zero
logic [P.FMALEN+1:0] FmaShiftIn; // fma shift input
logic [P.NE+1:0] NormSumExp; // exponent of the normalized sum not taking into account Subnormal or zero results logic [P.NE+1:0] NormSumExp; // exponent of the normalized sum not taking into account Subnormal or zero results
logic FmaPreResultSubnorm; // is the result subnormal - calculated before LZA corection logic FmaPreResultSubnorm; // is the result subnormal - calculated before LZA corection
logic [$clog2(P.FMALEN+1)-1:0] FmaShiftAmt; // normalization shift amount for fma logic [$clog2(P.FMALEN+1)-1:0] FmaShiftAmt; // normalization shift amount for fma
// division signals // division signals
logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt; // divsqrt shif amount logic [P.LOGNORMSHIFTSZ-1:0] DivShiftAmt; // divsqrt shif amount
logic [P.NORMSHIFTSZ-1:0] DivShiftIn; // divsqrt shift input
logic [P.NE+1:0] Ue; // divsqrt corrected exponent after corretion shift logic [P.NE+1:0] Ue; // divsqrt corrected exponent after corretion shift
logic DivByZero; // divide by zero flag logic DivByZero; // divide by zero flag
logic DivResSubnorm; // is the divsqrt result subnormal logic DivResSubnorm; // is the divsqrt result subnormal
@ -145,17 +143,17 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
cvtshiftcalc #(P) cvtshiftcalc(.ToInt, .CvtCe, .CvtResSubnormUf, .Xm, .CvtLzcIn, cvtshiftcalc #(P) cvtshiftcalc(.ToInt, .CvtCe, .CvtResSubnormUf, .Xm, .CvtLzcIn,
.XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn); .XZero, .IntToFp, .OutFmt, .CvtResUf, .CvtShiftIn);
fmashiftcalc #(P) fmashiftcalc(.FmaSm, .FmaSCnt, .Fmt, .NormSumExp, .FmaSe, fmashiftcalc #(P) fmashiftcalc(.FmaSCnt, .Fmt, .NormSumExp, .FmaSe, .FmaSm,
.FmaSZero, .FmaPreResultSubnorm, .FmaShiftAmt, .FmaShiftIn); .FmaSZero, .FmaPreResultSubnorm, .FmaShiftAmt);
divshiftcalc #(P) divshiftcalc(.DivUe, .DivUm, .DivResSubnorm, .DivSubnormShiftPos, .DivShiftAmt, .DivShiftIn); divshiftcalc #(P) divshiftcalc(.DivUe, .DivResSubnorm, .DivSubnormShiftPos, .DivShiftAmt);
// select which unit's output to shift // select which unit's output to shift
always_comb always_comb
case(PostProcSel) case(PostProcSel)
2'b10: begin // fma 2'b10: begin // fma
ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(P.FMALEN-1){1'b0}}, FmaShiftAmt}; ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(P.FMALEN-1){1'b0}}, FmaShiftAmt};
ShiftIn = {FmaShiftIn, {P.NORMSHIFTSZ-(P.FMALEN+2){1'b0}}}; ShiftIn = {{2'b00, FmaSm}, {P.NORMSHIFTSZ-(P.FMALEN+2){1'b0}}};
end end
2'b00: begin // cvt 2'b00: begin // cvt
ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(P.CVTLEN+1){1'b0}}, CvtShiftAmt}; ShiftAmt = {{P.LOGNORMSHIFTSZ-$clog2(P.CVTLEN+1){1'b0}}, CvtShiftAmt};
@ -163,7 +161,7 @@ module postprocess import cvw::*; #(parameter cvw_t P) (
end end
2'b01: begin //divsqrt 2'b01: begin //divsqrt
ShiftAmt = DivShiftAmt; ShiftAmt = DivShiftAmt;
ShiftIn = DivShiftIn; ShiftIn = {{P.NF{1'b0}}, DivUm, {P.NORMSHIFTSZ-P.DIVb-1-P.NF{1'b0}}};
end end
default: begin default: begin
ShiftAmt = {P.LOGNORMSHIFTSZ{1'bx}}; ShiftAmt = {P.LOGNORMSHIFTSZ{1'bx}};