mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Fixed another bug with the atomic instrucitons implemention in the dcache.
This commit is contained in:
Ross Thompson
parent
20a04d8cee
commit
467e24c05c
@ -13,41 +13,41 @@ add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/InstrM
|
|||||||
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
|
add wave -noupdate -expand -group {Memory Stage} /testbench/dut/hart/lsu/MemAdrM
|
||||||
add wave -noupdate -expand -group {WriteBack stage} /testbench/dut/hart/ieu/InstrValidW
|
add wave -noupdate -expand -group {WriteBack stage} /testbench/dut/hart/ieu/InstrValidW
|
||||||
add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW
|
add wave -noupdate -expand -group {WriteBack stage} /testbench/PCW
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrMisalignedFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrAccessFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/IllegalInstrFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/BreakpointFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadMisalignedFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreMisalignedFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadAccessFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StoreAccessFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/EcallFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InstrPageFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/LoadPageFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/StorePageFaultM
|
||||||
add wave -noupdate -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
|
add wave -noupdate -expand -group HDU -group traps /testbench/dut/hart/priv/trap/InterruptM
|
||||||
add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
|
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/PendingIntsM
|
||||||
add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
|
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/CommittedM
|
||||||
add wave -noupdate -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
|
add wave -noupdate -expand -group HDU -group interrupts /testbench/dut/hart/priv/trap/InstrValidM
|
||||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/BPPredWrongE
|
||||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/CSRWritePendingDEM
|
||||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/RetM
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/RetM
|
||||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/TrapM
|
||||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LoadStallD
|
||||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/StoreStallD
|
||||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/ICacheStallF
|
||||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/hzu/LSUStall
|
||||||
add wave -noupdate -group HDU -group hazards /testbench/dut/hart/MulDivStallD
|
add wave -noupdate -expand -group HDU -group hazards /testbench/dut/hart/MulDivStallD
|
||||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
|
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/hzu/FlushF
|
||||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
|
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushD
|
||||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
|
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushE
|
||||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
|
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushM
|
||||||
add wave -noupdate -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
|
add wave -noupdate -expand -group HDU -expand -group Flush -color Yellow /testbench/dut/hart/FlushW
|
||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
|
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallF
|
||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
|
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallD
|
||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
|
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallE
|
||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
|
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallM
|
||||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
|
add wave -noupdate -expand -group HDU -expand -group Stall -color Orange /testbench/dut/hart/StallW
|
||||||
add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
|
add wave -noupdate -group Bpred -color Orange /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/GHR
|
||||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
|
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} /testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/BPPredF
|
||||||
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
|
add wave -noupdate -group Bpred -expand -group {branch update selection inputs} {/testbench/dut/hart/ifu/bpred/bpred/Predictor/DirPredictor/InstrClassE[0]}
|
||||||
@ -115,19 +115,19 @@ add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
|
|||||||
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
|
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
|
||||||
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
|
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
|
||||||
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
|
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
|
||||||
add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
|
add wave -noupdate -expand -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf
|
||||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
|
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
|
||||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
|
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
|
||||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
|
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
|
||||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
|
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
|
||||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
|
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
|
||||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
|
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
|
||||||
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
|
add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
|
||||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
|
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
|
||||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
|
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
|
||||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
|
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
|
||||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
|
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
|
||||||
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
|
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
|
||||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
|
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/a
|
||||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
|
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/b
|
||||||
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
|
add wave -noupdate -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
|
||||||
@ -290,17 +290,17 @@ add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM w
|
|||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[2]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word2 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[2]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[3]/CacheDataMem/WriteEnable}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[3]/CacheDataMem/WriteEnable}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[3]/CacheDataMem/StoredData}
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM writes} -expand -group way1 -expand -group Way1Word3 {/testbench/dut/hart/lsu/dcache/CacheWays[1]/MemWay/word[3]/CacheDataMem/StoredData}
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/SRAMAdr
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockWayMaskedM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockSetsM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataBlockSetsM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadDataWordM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/ReadTag
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/BlockReplacementBits
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/BlockReplacementBits
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/WayHit
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Dirty
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -expand -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid
|
add wave -noupdate -expand -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/hart/lsu/dcache/Valid
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBLockWayMaskedM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimReadDataBlockM
|
||||||
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
|
add wave -noupdate -expand -group lsu -expand -group dcache -group Victim /testbench/dut/hart/lsu/dcache/VictimTag
|
||||||
@ -351,19 +351,19 @@ add wave -noupdate -expand -group lsu -group pma /testbench/dut/hart/lsu/dmmu/PM
|
|||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPInstrAccessFaultF
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPLoadAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
|
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/hart/lsu/dmmu/PMPStoreAccessFaultM
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/hart/lsu/hptw/genblk1/WalkerState
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PCF
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/genblk1/TranslationVAdr
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/TranslationPAdr
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/HPTWReadPTE
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
|
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/hart/lsu/hptw/PTE
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBMissF
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBMissM
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/ITLBWriteF
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/DTLBWriteM
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerInstrPageFaultF
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerLoadPageFaultM
|
||||||
add wave -noupdate -expand -group lsu -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
|
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/hart/lsu/hptw/WalkerStorePageFaultM
|
||||||
add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW
|
add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/HPMCOUNTER_REGW
|
||||||
add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/MIP_REGW
|
add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/MIP_REGW
|
||||||
add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/genblk1/csrm/MSTATUS_REGW
|
add wave -noupdate -expand -group csr /testbench/dut/hart/priv/csr/genblk1/csrm/MSTATUS_REGW
|
||||||
@ -466,8 +466,8 @@ add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/Privilege
|
|||||||
add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/PrivilegedTrapVector
|
add wave -noupdate -group {pc selection} /testbench/dut/hart/priv/trap/PrivilegedTrapVector
|
||||||
add wave -noupdate -radix unsigned /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/INSTRET_REGW
|
add wave -noupdate -radix unsigned /testbench/dut/hart/priv/csr/genblk1/counters/genblk1/INSTRET_REGW
|
||||||
TreeUpdate [SetDefaultTree]
|
TreeUpdate [SetDefaultTree]
|
||||||
WaveRestoreCursors {{Cursor 6} {165345795 ns} 0} {{Cursor 6} {41705547 ns} 0} {{Cursor 7} {41639055 ns} 0}
|
WaveRestoreCursors {{Cursor 6} {165345948 ns} 0} {{Cursor 6} {41860237 ns} 0} {{Cursor 8} {165365597 ns} 0} {{Cursor 10} {41858928 ns} 0}
|
||||||
quietly wave cursor active 1
|
quietly wave cursor active 4
|
||||||
configure wave -namecolwidth 250
|
configure wave -namecolwidth 250
|
||||||
configure wave -valuecolwidth 297
|
configure wave -valuecolwidth 297
|
||||||
configure wave -justifyvalue left
|
configure wave -justifyvalue left
|
||||||
@ -482,4 +482,4 @@ configure wave -griddelta 40
|
|||||||
configure wave -timeline 0
|
configure wave -timeline 0
|
||||||
configure wave -timelineunits ns
|
configure wave -timelineunits ns
|
||||||
update
|
update
|
||||||
WaveRestoreZoom {165345739 ns} {165345955 ns}
|
WaveRestoreZoom {41858847 ns} {41859063 ns}
|
||||||
|
|||||||
29
wally-pipelined/src/cache/dcache.sv
vendored
29
wally-pipelined/src/cache/dcache.sv
vendored
@ -622,13 +622,26 @@ module dcache
|
|||||||
STATE_MISS_READ_WORD_DELAY: begin
|
STATE_MISS_READ_WORD_DELAY: begin
|
||||||
//SelAdrM = 2'b01;
|
//SelAdrM = 2'b01;
|
||||||
CommittedM = 1'b1;
|
CommittedM = 1'b1;
|
||||||
LRUWriteEn = 1'b1;
|
if(&MemRWM & AtomicM[1]) begin // amo write
|
||||||
if(StallWtoDCache) begin
|
|
||||||
NextState = STATE_CPU_BUSY;
|
|
||||||
SelAdrM = 2'b01;
|
SelAdrM = 2'b01;
|
||||||
end
|
if(StallWtoDCache) begin
|
||||||
else begin
|
NextState = STATE_CPU_BUSY_FINISH_AMO;
|
||||||
NextState = STATE_READY;
|
end
|
||||||
|
else begin
|
||||||
|
SRAMWordWriteEnableM = 1'b1;
|
||||||
|
SetDirtyM = 1'b1;
|
||||||
|
LRUWriteEn = 1'b1;
|
||||||
|
NextState = STATE_READY;
|
||||||
|
end
|
||||||
|
end else begin
|
||||||
|
LRUWriteEn = 1'b1;
|
||||||
|
if(StallWtoDCache) begin
|
||||||
|
NextState = STATE_CPU_BUSY;
|
||||||
|
SelAdrM = 2'b01;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
NextState = STATE_READY;
|
||||||
|
end
|
||||||
end
|
end
|
||||||
end
|
end
|
||||||
|
|
||||||
@ -808,9 +821,9 @@ module dcache
|
|||||||
|
|
||||||
STATE_CPU_BUSY_FINISH_AMO: begin
|
STATE_CPU_BUSY_FINISH_AMO: begin
|
||||||
CommittedM = 1'b1;
|
CommittedM = 1'b1;
|
||||||
|
SelAdrM = 2'b01;
|
||||||
if(StallWtoDCache) begin
|
if(StallWtoDCache) begin
|
||||||
NextState = STATE_CPU_BUSY;
|
NextState = STATE_CPU_BUSY_FINISH_AMO;
|
||||||
SelAdrM = 2'b01;
|
|
||||||
end
|
end
|
||||||
else begin
|
else begin
|
||||||
SRAMWordWriteEnableM = 1'b1;
|
SRAMWordWriteEnableM = 1'b1;
|
||||||
|
|||||||
@ -257,7 +257,7 @@ module testbench();
|
|||||||
end
|
end
|
||||||
// override on special conditions
|
// override on special conditions
|
||||||
if (ExpectedMemAdrM == 'h10000005) begin
|
if (ExpectedMemAdrM == 'h10000005) begin
|
||||||
$display("%t: Overwriting read data from CLINT.", $time);
|
//$display("%t: Overwriting read data from CLINT.", $time);
|
||||||
force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM;
|
force dut.hart.ieu.dp.ReadDataM = ExpectedMemReadDataM;
|
||||||
end
|
end
|
||||||
|
|
||||||
@ -266,7 +266,7 @@ module testbench();
|
|||||||
|
|
||||||
// step 1: register expected state into the write back stage.
|
// step 1: register expected state into the write back stage.
|
||||||
always @(posedge clk) begin
|
always @(posedge clk) begin
|
||||||
if (dut.hart.FlushW | reset) begin
|
if (reset) begin
|
||||||
ExpectedPCW <= '0;
|
ExpectedPCW <= '0;
|
||||||
ExpectedInstrW <= '0;
|
ExpectedInstrW <= '0;
|
||||||
textW <= "";
|
textW <= "";
|
||||||
@ -280,27 +280,40 @@ module testbench();
|
|||||||
NumCSRW <= '0;
|
NumCSRW <= '0;
|
||||||
end
|
end
|
||||||
else if(~dut.hart.StallW) begin
|
else if(~dut.hart.StallW) begin
|
||||||
ExpectedPCW <= ExpectedPCM;
|
if(dut.hart.FlushW) begin
|
||||||
ExpectedInstrW <= ExpectedInstrM;
|
ExpectedPCW <= '0;
|
||||||
textW <= textM;
|
ExpectedInstrW <= '0;
|
||||||
RegWriteW <= RegWriteM;
|
textW <= "";
|
||||||
ExpectedRegAdrW <= ExpectedRegAdrM;
|
RegWriteW <= "";
|
||||||
ExpectedRegValueW <= ExpectedRegValueM;
|
ExpectedRegAdrW <= '0;
|
||||||
ExpectedMemAdrW <= ExpectedMemAdrM;
|
ExpectedRegValueW <= '0;
|
||||||
MemOpW <= MemOpM;
|
ExpectedMemAdrW <= '0;
|
||||||
ExpectedMemWriteDataW <= ExpectedMemWriteDataM;
|
MemOpW <= "";
|
||||||
ExpectedMemReadDataW <= ExpectedMemReadDataM;
|
ExpectedMemWriteDataW <= '0;
|
||||||
NumCSRW <= NumCSRM;
|
ExpectedMemReadDataW <= '0;
|
||||||
|
NumCSRW <= '0;
|
||||||
|
end else begin
|
||||||
|
ExpectedPCW <= ExpectedPCM;
|
||||||
|
ExpectedInstrW <= ExpectedInstrM;
|
||||||
|
textW <= textM;
|
||||||
|
RegWriteW <= RegWriteM;
|
||||||
|
ExpectedRegAdrW <= ExpectedRegAdrM;
|
||||||
|
ExpectedRegValueW <= ExpectedRegValueM;
|
||||||
|
ExpectedMemAdrW <= ExpectedMemAdrM;
|
||||||
|
MemOpW <= MemOpM;
|
||||||
|
ExpectedMemWriteDataW <= ExpectedMemWriteDataM;
|
||||||
|
ExpectedMemReadDataW <= ExpectedMemReadDataM;
|
||||||
|
NumCSRW <= NumCSRM;
|
||||||
|
end
|
||||||
// override on special conditions
|
// override on special conditions
|
||||||
#1;
|
#1;
|
||||||
if(textM.substr(0,5) == "rdtime") begin
|
if(textM.substr(0,5) == "rdtime") begin
|
||||||
$display("%t: Overwrite register write on read of MTIME.", $time);
|
//$display("%t: Overwrite register write on read of MTIME.", $time);
|
||||||
force dut.hart.ieu.dp.regf.wd3 = ExpectedRegValueM;
|
force dut.hart.ieu.dp.regf.wd3 = ExpectedRegValueM;
|
||||||
end
|
end
|
||||||
|
|
||||||
if (ExpectedMemAdrM == 'h10000005) begin
|
if (ExpectedMemAdrM == 'h10000005) begin
|
||||||
$display("%t: releasing force of ReadDataM.", $time);
|
//$display("%t: releasing force of ReadDataM.", $time);
|
||||||
release dut.hart.ieu.dp.ReadDataM;
|
release dut.hart.ieu.dp.ReadDataM;
|
||||||
end
|
end
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user