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possible interrupt code

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This commit is contained in:
David Harris 2021-08-22 17:02:40 -04:00
parent ddbc659d7b
commit 4677b4bb38
1 changed files with 6 additions and 1 deletions
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wally-pipelined/src/privileged/csri.sv
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@ -51,13 +51,18 @@ module csri #(parameter
// assumes no N-mode user interrupts // assumes no N-mode user interrupts
always_comb begin always_comb begin
IntInM = 0; // *** does this overwriting technique really synthesize IntInM = 0;
IntInM[11] = ExtIntM & ~MIDELEG_REGW[9]; // MEIP IntInM[11] = ExtIntM & ~MIDELEG_REGW[9]; // MEIP
IntInM[9] = ExtIntM & MIDELEG_REGW[9]; // SEIP IntInM[9] = ExtIntM & MIDELEG_REGW[9]; // SEIP
IntInM[7] = TimerIntM & ~MIDELEG_REGW[5]; // MTIP IntInM[7] = TimerIntM & ~MIDELEG_REGW[5]; // MTIP
IntInM[5] = TimerIntM & MIDELEG_REGW[5]; // STIP IntInM[5] = TimerIntM & MIDELEG_REGW[5]; // STIP
IntInM[3] = SwIntM & ~MIDELEG_REGW[1]; // MSIP IntInM[3] = SwIntM & ~MIDELEG_REGW[1]; // MSIP
IntInM[1] = SwIntM & MIDELEG_REGW[1]; // SSIP IntInM[1] = SwIntM & MIDELEG_REGW[1]; // SSIP
/* maybe only machine mode interrupts should be directly triggered:
IntInM[11] = ExtIntM; // MEIP
IntInM[7] = TimerIntM; // MTIP
IntInM[3] = SwIntM; // MSIP
*/
end end
// Interrupt Write Enables // Interrupt Write Enables