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https://github.com/openhwgroup/cvw
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coremark directory changes
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@ -54,7 +54,7 @@ add wave -divider
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add wave -divider Fetch
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add wave -divider Fetch
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add wave -hex /testbench/dut/hart/ifu/PCF
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add wave -hex /testbench/dut/hart/ifu/PCF
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add wave -hex /testbench/dut/hart/ifu/InstrF
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add wave -hex /testbench/dut/hart/ifu/ic/InstrF
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add wave /testbench/InstrFName
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add wave /testbench/InstrFName
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add wave -divider Decode
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add wave -divider Decode
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add wave -hex /testbench/dut/hart/ifu/PCD
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add wave -hex /testbench/dut/hart/ifu/PCD
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@ -93,7 +93,7 @@ add wave -divider RAM
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add wave -hex -r /testbench/dut/uncore/dtim/RAM
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add wave -hex -r /testbench/dut/uncore/dtim/RAM
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add wave -divider Misc
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add wave -divider Misc
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add wave -divider
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add wave -divider
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#add wave -hex -r /testbench/*
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add wave -hex -r /testbench/*
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-- Set Wave Output Items
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-- Set Wave Output Items
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TreeUpdate [SetDefaultTree]
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TreeUpdate [SetDefaultTree]
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@ -48,7 +48,7 @@ module testbench();
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// pick tests based on modes supported
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// pick tests based on modes supported
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initial
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initial
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tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremark.RV64IM.bare.elf.memfile", "1000"};
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tests = {"../../imperas-riscv-tests/riscv-ovpsim-plus/examples/CoreMark/coremarkcodemod.bare.riscv.memfile", "1000"};
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string signame, memfilename;
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string signame, memfilename;
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logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
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logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
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logic UARTSin, UARTSout;
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logic UARTSin, UARTSout;
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@ -65,7 +65,7 @@ module testbench();
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// Track names of instructions
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// Track names of instructions
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instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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dut.hart.ifu.InstrF,
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dut.hart.ifu.ic.InstrF,
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dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
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dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
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dut.hart.ifu.InstrM, InstrW,
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dut.hart.ifu.InstrM, InstrW,
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InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
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