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LSU name cleanup

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This commit is contained in:
David Harris 2022-04-18 03:18:38 +00:00
parent a99466a487
commit 462158ea92
5 changed files with 15 additions and 16 deletions
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1
pipelined/src/lsu/lsu.sv
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@ -145,6 +145,7 @@ module lsu (
assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM; assign CommittedM = SelHPTW | DCacheCommittedM | BusCommittedM;
// MMU and Misalignment fault logic required if privileged unit exists // MMU and Misalignment fault logic required if privileged unit exists
// *** DH: This is too strong a requirement. Separate MMU in `VIRTMEM_SUPPORTED from simpler faults in `ZICSR_SUPPORTED
if(`ZICSR_SUPPORTED == 1) begin : dmmu if(`ZICSR_SUPPORTED == 1) begin : dmmu
logic DisableTranslation; logic DisableTranslation;
assign DisableTranslation = SelHPTW | FlushDCacheM; assign DisableTranslation = SelHPTW | FlushDCacheM;

3
pipelined/src/lsu/subwordwrite.sv
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@ -39,8 +39,7 @@ module subwordwrite (
); );
// Compute byte masks // Compute byte masks
swbytemask swbytemask(.HSIZED({LSUFunct3M[2], 1'b0, LSUFunct3M[1:0]}), .HADDRD(LSUPAdrM), swbytemask swbytemask(.Size(LSUFunct3M[1:0]), .Adr(LSUPAdrM), .ByteMask(ByteMaskM));
.ByteMask(ByteMaskM));
// Replicate data for subword writes // Replicate data for subword writes
if (`XLEN == 64) begin:sww if (`XLEN == 64) begin:sww

22
pipelined/src/lsu/swbytemask.sv
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@ -31,32 +31,32 @@
`include "wally-config.vh" `include "wally-config.vh"
module swbytemask ( module swbytemask (
input logic [3:0] HSIZED, input logic [1:0] Size,
input logic [2:0] HADDRD, input logic [2:0] Adr,
output logic [`XLEN/8-1:0] ByteMask); output logic [`XLEN/8-1:0] ByteMask);
if(`XLEN == 64) begin if(`XLEN == 64) begin
always_comb begin always_comb begin
case(HSIZED[1:0]) case(Size[1:0])
2'b00: begin ByteMask = 8'b00000000; ByteMask[HADDRD[2:0]] = 1; end // sb 2'b00: begin ByteMask = 8'b00000000; ByteMask[Adr[2:0]] = 1; end // sb
2'b01: case (HADDRD[2:1]) 2'b01: case (Adr[2:1])
2'b00: ByteMask = 8'b0000_0011; 2'b00: ByteMask = 8'b0000_0011;
2'b01: ByteMask = 8'b0000_1100; 2'b01: ByteMask = 8'b0000_1100;
2'b10: ByteMask = 8'b0011_0000; 2'b10: ByteMask = 8'b0011_0000;
2'b11: ByteMask = 8'b1100_0000; 2'b11: ByteMask = 8'b1100_0000;
endcase endcase
2'b10: if (HADDRD[2]) ByteMask = 8'b11110000; 2'b10: if (Adr[2]) ByteMask = 8'b11110000;
else ByteMask = 8'b00001111; else ByteMask = 8'b00001111;
2'b11: ByteMask = 8'b1111_1111; 2'b11: ByteMask = 8'b1111_1111;
endcase endcase
end end
end else begin end else begin
always_comb begin always_comb begin
case(HSIZED[1:0]) case(Size[1:0])
2'b00: begin ByteMask = 4'b0000; ByteMask[HADDRD[1:0]] = 1; end // sb 2'b00: begin ByteMask = 4'b0000; ByteMask[Adr[1:0]] = 1; end // sb
2'b01: if (HADDRD[1]) ByteMask = 4'b1100; 2'b01: if (Adr[1]) ByteMask = 4'b1100;
else ByteMask = 4'b0011; else ByteMask = 4'b0011;
2'b10: ByteMask = 4'b1111; 2'b10: ByteMask = 4'b1111;
default: ByteMask = 4'b1111; default: ByteMask = 4'b1111;
endcase endcase

3
pipelined/src/uncore/clint.sv
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@ -66,8 +66,7 @@ module clint (
if (`XLEN==64) assign #2 entry = {HADDR[15:3], 3'b000}; if (`XLEN==64) assign #2 entry = {HADDR[15:3], 3'b000};
else assign #2 entry = {HADDR[15:2], 2'b00}; else assign #2 entry = {HADDR[15:2], 2'b00};
swbytemask swbytemask(.HSIZED, .HADDRD(entryd[2:0]), .ByteMask(ByteMaskM)); swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(entryd[2:0]), .ByteMask(ByteMaskM));
// DH 2/20/21: Eventually allow MTIME to run off a separate clock // DH 2/20/21: Eventually allow MTIME to run off a separate clock
// This will require synchronizing MTIME to the system clock // This will require synchronizing MTIME to the system clock

2
pipelined/src/uncore/ram.sv
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@ -56,7 +56,7 @@ module ram #(parameter BASE=0, RANGE = 65535) (
logic memwrite; logic memwrite;
logic [3:0] busycount; logic [3:0] busycount;
swbytemask swbytemask(.HSIZED, .HADDRD(HWADDR[2:0]), .ByteMask(ByteMaskM)); swbytemask swbytemask(.Size(HSIZED[1:0]), .Adr(HWADDR[2:0]), .ByteMask(ByteMaskM));
assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00); assign initTrans = HREADY & HSELRam & (HTRANS != 2'b00);