diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh index 081b549a0..e0c786110 100644 --- a/pipelined/config/rv64fp/wally-config.vh +++ b/pipelined/config/rv64fp/wally-config.vh @@ -94,11 +94,11 @@ // *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? `define DTIM_SUPPORTED 0 -`define DTIM_BASE 34'h80000000 -`define DTIM_RANGE 34'h00001FFF +`define DTIM_BASE 56'h80000000 +`define DTIM_RANGE 56'h00001FFF `define IROM_SUPPORTED 0 -`define IROM_BASE 34'h80000000 -`define IROM_RANGE 34'h00001FFF +`define IROM_BASE 56'h80000000 +`define IROM_RANGE 56'h00001FFF `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTROM_RANGE 56'h00000FFF diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh index cc7093346..4310f6369 100644 --- a/pipelined/config/rv64fpquad/wally-config.vh +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -93,11 +93,11 @@ // *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? `define DTIM_SUPPORTED 0 -`define DTIM_BASE 34'h80000000 -`define DTIM_RANGE 34'h00001FFF +`define DTIM_BASE 56'h80000000 +`define DTIM_RANGE 56'h00001FFF `define IROM_SUPPORTED 0 -`define IROM_BASE 34'h80000000 -`define IROM_RANGE 34'h00001FFF +`define IROM_BASE 56'h80000000 +`define IROM_RANGE 56'h00001FFF `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTROM_RANGE 56'h00000FFF diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index eea36a99f..b4bce027e 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -93,11 +93,11 @@ // *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? `define DTIM_SUPPORTED 0 -`define DTIM_BASE 34'h80000000 -`define DTIM_RANGE 34'h00001FFF +`define DTIM_BASE 56'h80000000 +`define DTIM_RANGE 56'h00001FFF `define IROM_SUPPORTED 0 -`define IROM_BASE 34'h80000000 -`define IROM_RANGE 34'h00001FFF +`define IROM_BASE 56'h80000000 +`define IROM_RANGE 56'h00001FFF `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTROM_RANGE 56'h00000FFF diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index e7d337847..b67c0711b 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -93,11 +93,11 @@ // *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? `define DTIM_SUPPORTED 0 -`define DTIM_BASE 34'h80000000 -`define DTIM_RANGE 34'h00001FFF +`define DTIM_BASE 56'h80000000 +`define DTIM_RANGE 56'h00001FFF `define IROM_SUPPORTED 0 -`define IROM_BASE 34'h80000000 -`define IROM_RANGE 34'h00001FFF +`define IROM_BASE 56'h80000000 +`define IROM_RANGE 56'h00001FFF `define BOOTROM_SUPPORTED 1'b1 `define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTROM_RANGE 56'h00000FFF diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index c8c616ea9..3d14a7d7b 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -93,11 +93,11 @@ // *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? `define DTIM_SUPPORTED 1 -`define DTIM_BASE 34'h80000000 -`define DTIM_RANGE 34'h00001FFF -`define IROM_SUPPORTED 1 -`define IROM_BASE 34'h80000000 -`define IROM_RANGE 34'h00001FFF +`define DTIM_BASE 56'h80000000 +`define DTIM_RANGE 56'h00001FFF +`define IROM_SUPPORTED 01 +`define IROM_BASE 56'h80000000 +`define IROM_RANGE 56'h00001FFF `define BOOTROM_SUPPORTED 1'b0 `define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder `define BOOTROM_RANGE 56'h00000FFF diff --git a/pipelined/src/mmu/adrdecs.sv b/pipelined/src/mmu/adrdecs.sv index 8c31ada25..187e10111 100644 --- a/pipelined/src/mmu/adrdecs.sv +++ b/pipelined/src/mmu/adrdecs.sv @@ -35,22 +35,24 @@ module adrdecs ( input logic [`PA_BITS-1:0] PhysicalAddress, input logic AccessRW, AccessRX, AccessRWX, input logic [1:0] Size, - output logic [8:0] SelRegions + output logic [10:0] SelRegions ); localparam logic [3:0] SUPPORTED_SIZE = (`LLEN == 32 ? 4'b0111 : 4'b1111); // Determine which region of physical memory (if any) is being accessed - adrdec ddr4dec(PhysicalAddress, `EXT_MEM_BASE, `EXT_MEM_RANGE, `EXT_MEM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[7]); - adrdec boottimdec(PhysicalAddress, `BOOTROM_BASE, `BOOTROM_RANGE, `BOOTROM_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[6]); - adrdec timdec(PhysicalAddress, `UNCORE_RAM_BASE, `UNCORE_RAM_RANGE, `UNCORE_RAM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[5]); + adrdec ddr4dec(PhysicalAddress, `EXT_MEM_BASE, `EXT_MEM_RANGE, `EXT_MEM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[9]); + adrdec bootromdec(PhysicalAddress, `BOOTROM_BASE, `BOOTROM_RANGE, `BOOTROM_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[8]); + adrdec uncoreramdec(PhysicalAddress, `UNCORE_RAM_BASE, `UNCORE_RAM_RANGE, `UNCORE_RAM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[7]); + adrdec clintdec(PhysicalAddress, `CLINT_BASE, `CLINT_RANGE, `CLINT_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[6]); + adrdec gpiodec(PhysicalAddress, `GPIO_BASE, `GPIO_RANGE, `GPIO_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[5]); + adrdec uartdec(PhysicalAddress, `UART_BASE, `UART_RANGE, `UART_SUPPORTED, AccessRW, Size, 4'b0001, SelRegions[4]); + adrdec plicdec(PhysicalAddress, `PLIC_BASE, `PLIC_RANGE, `PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[3]); + adrdec sdcdec(PhysicalAddress, `SDC_BASE, `SDC_RANGE, `SDC_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE & 4'b1100, SelRegions[2]); - adrdec clintdec(PhysicalAddress, `CLINT_BASE, `CLINT_RANGE, `CLINT_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE, SelRegions[4]); - adrdec gpiodec(PhysicalAddress, `GPIO_BASE, `GPIO_RANGE, `GPIO_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[3]); - adrdec uartdec(PhysicalAddress, `UART_BASE, `UART_RANGE, `UART_SUPPORTED, AccessRW, Size, 4'b0001, SelRegions[2]); - adrdec plicdec(PhysicalAddress, `PLIC_BASE, `PLIC_RANGE, `PLIC_SUPPORTED, AccessRW, Size, 4'b0100, SelRegions[1]); - adrdec sdcdec(PhysicalAddress, `SDC_BASE, `SDC_RANGE, `SDC_SUPPORTED, AccessRW, Size, SUPPORTED_SIZE & 4'b1100, SelRegions[0]); + adrdec iromdec(PhysicalAddress, `IROM_BASE, `IROM_RANGE, `IROM_SUPPORTED, AccessRX, Size, SUPPORTED_SIZE, SelRegions[1]); + adrdec dtimdec(PhysicalAddress, `DTIM_BASE, `DTIM_RANGE, `DTIM_SUPPORTED, AccessRWX, Size, SUPPORTED_SIZE, SelRegions[0]); - assign SelRegions[8] = ~|(SelRegions[7:0]); + assign SelRegions[10] = ~|(SelRegions[7:2]); // none of the bus regions are selected endmodule diff --git a/pipelined/src/mmu/pmachecker.sv b/pipelined/src/mmu/pmachecker.sv index 0d3c41549..c11b8bcdb 100644 --- a/pipelined/src/mmu/pmachecker.sv +++ b/pipelined/src/mmu/pmachecker.sv @@ -46,7 +46,7 @@ module pmachecker ( logic PMAAccessFault; logic AccessRW, AccessRWX, AccessRX; - logic [8:0] SelRegions; + logic [10:0] SelRegions; // Determine what type of access is being made assign AccessRW = ReadAccessM | WriteAccessM; @@ -56,14 +56,13 @@ module pmachecker ( // Determine which region of physical memory (if any) is being accessed adrdecs adrdecs(PhysicalAddress, AccessRW, AccessRX, AccessRWX, Size, SelRegions); - // Only RAM memory regions are cacheable - // *** Ross Thompson fix these. They should be part of adrdec - assign Cacheable = SelRegions[7] | SelRegions[6] | SelRegions[5]; - assign Idempotent = SelRegions[7] | SelRegions[5]; - assign AtomicAllowed = SelRegions[7] | SelRegions[5]; + // Only non-core RAM/ROM memory regions are cacheable + assign Cacheable = SelRegions[9] | SelRegions[8] | SelRegions[7]; + assign Idempotent = SelRegions[9] | SelRegions[7]; + assign AtomicAllowed = SelRegions[9] | SelRegions[7]; // Detect access faults - assign PMAAccessFault = SelRegions[8] & AccessRWX; + assign PMAAccessFault = SelRegions[10] & AccessRWX; assign PMAInstrAccessFaultF = ExecuteAccessF & PMAAccessFault; assign PMALoadAccessFaultM = ReadAccessM & PMAAccessFault; assign PMAStoreAmoAccessFaultM = WriteAccessM & PMAAccessFault; diff --git a/pipelined/src/uncore/uncore.sv b/pipelined/src/uncore/uncore.sv index ecb2fe130..1eec29f82 100644 --- a/pipelined/src/uncore/uncore.sv +++ b/pipelined/src/uncore/uncore.sv @@ -67,7 +67,7 @@ module uncore ( logic [`XLEN-1:0] HREADRam, HREADSDC; - logic [8:0] HSELRegions; + logic [10:0] HSELRegions; logic HSELRam, HSELCLINT, HSELPLIC, HSELGPIO, HSELUART, HSELSDC; logic HSELEXTD, HSELRamD, HSELCLINTD, HSELPLICD, HSELGPIOD, HSELUARTD, HSELSDCD; logic HRESPRam, HRESPSDC; @@ -93,7 +93,7 @@ module uncore ( adrdecs adrdecs(HADDR, 1'b1, 1'b1, 1'b1, HSIZE[1:0], HSELRegions); // unswizzle HSEL signals - assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[7:0]; + assign {HSELEXT, HSELBootRom, HSELRam, HSELCLINT, HSELGPIO, HSELUART, HSELPLIC, HSELSDC} = HSELRegions[9:2]; // AHB -> APB bridge ahbapbbridge #(4) ahbapbbridge @@ -197,7 +197,7 @@ module uncore ( HSELNoneD; // don't lock up the bus if no region is being accessed // Address Decoder Delay (figure 4-2 in spec) - flopr #(9) hseldelayreg(HCLK, ~HRESETn, HSELRegions, {HSELNoneD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD}); + flopr #(9) hseldelayreg(HCLK, ~HRESETn, HSELRegions[10:2], {HSELNoneD, HSELEXTD, HSELBootRomD, HSELRamD, HSELCLINTD, HSELGPIOD, HSELUARTD, HSELPLICD, HSELSDCD}); flopr #(1) hselbridgedelayreg(HCLK, ~HRESETn, HSELBRIDGE, HSELBRIDGED); endmodule