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mod 2 of fpdivsqrt update
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James E. Stine
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151
wally-pipelined/src/fpu/fpdiv.sv
Executable file
151
wally-pipelined/src/fpu/fpdiv.sv
Executable file
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//
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// File name : fpdiv
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// Title : Floating-Point Divider/Square-Root
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// project : FPU
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// Library : fpdiv
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// Author(s) : James E. Stine, Jr.
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// Purpose : definition of main unit to floating-point div/sqrt
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// notes :
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//
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// Copyright Oklahoma State University
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//
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// Basic Operations
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//
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// Step 1: Load operands, set flags, and convert SP to DP
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// Step 2: Check for special inputs ( +/- Infinity, NaN)
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// Step 3: Exponent Logic
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// Step 4: Divide/Sqrt using Goldschmidt
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// Step 5: Normalize the result.//
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// Shift left until normalized. Normalized when the value to the
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// left of the binrary point is 1.
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// Step 6: Round the result.//
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// Step 7: Put quotient/remainder onto output.
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//
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`timescale 1ps/1ps
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module fpdiv (done, AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn,
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start, reset, clk);
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input [63:0] op1; // 1st input operand (A)
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input [63:0] op2; // 2nd input operand (B)
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input [1:0] rm; // Rounding mode - specify values
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input op_type; // Function opcode
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input P; // Result Precision (0 for double, 1 for single)
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input OvEn; // Overflow trap enabled
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input UnEn; // Underflow trap enabled
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input start;
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input reset;
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input clk;
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output [63:0] AS_Result; // Result of operation
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output [4:0] Flags; // IEEE exception flags
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output Denorm; // Denorm on input or output
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output done;
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supply1 vdd;
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supply0 vss;
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wire [63:0] Float1;
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wire [63:0] Float2;
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wire [63:0] IntValue;
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wire [12:0] exp1, exp2, expF;
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wire [12:0] exp_diff, bias;
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wire [13:0] exp_sqrt;
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wire [12:0] exp_s;
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wire [12:0] exp_c;
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wire [10:0] exponent, exp_pre;
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wire [63:0] Result;
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wire [52:0] mantissaA;
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wire [52:0] mantissaB;
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wire [63:0] sum, sum_tc, sum_corr, sum_norm;
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wire [5:0] align_shift;
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wire [5:0] norm_shift;
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wire [2:0] sel_inv;
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wire op1_Norm, op2_Norm;
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wire opA_Norm, opB_Norm;
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wire Invalid;
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wire DenormIn, DenormIO;
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wire [4:0] FlagsIn;
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wire exp_gt63;
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wire Sticky_out;
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wire signResult, sign_corr;
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wire corr_sign;
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wire zeroB;
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wire convert;
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wire swap;
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wire sub;
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wire [63:0] q1, qm1, qp1, q0, qm0, qp0;
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wire [63:0] rega_out, regb_out, regc_out, regd_out;
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wire [127:0] regr_out;
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wire [2:0] sel_muxa, sel_muxb;
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wire sel_muxr;
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wire load_rega, load_regb, load_regc, load_regd, load_regr;
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wire donev, sel_muxrv, sel_muxsv;
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wire [1:0] sel_muxav, sel_muxbv;
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wire load_regav, load_regbv, load_regcv;
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wire load_regrv, load_regsv;
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// Convert the input operands to their appropriate forms based on
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// the orignal operands, the op_type , and their precision P.
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// Single precision inputs are converted to double precision
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// and the sign of the first operand is set appropratiately based on
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// if the operation is absolute value or negation.
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convert_inputs_div conv1 (Float1, Float2, op1, op2, op_type, P);
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// Test for exceptions and return the "Invalid Operation" and
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// "Denormalized" Input Flags. The "sel_inv" is used in
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// the third pipeline stage to select the result. Also, op1_Norm
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// and op2_Norm are one if op1 and op2 are not zero or denormalized.
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// sub is one if the effective operation is subtaction.
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exception_div exc1 (sel_inv, Invalid, DenormIn, op1_Norm, op2_Norm,
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Float1, Float2, op_type);
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// Determine Sign/Mantissa
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assign signResult = ((Float1[63]^Float2[63])&~op_type) | Float1[63]&op_type;
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assign mantissaA = {vdd, Float1[51:0]};
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assign mantissaB = {vdd, Float2[51:0]};
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// Perform Exponent Subtraction - expA - expB + Bias
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assign exp1 = {2'b0, Float1[62:52]};
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assign exp2 = {2'b0, Float2[62:52]};
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// bias : DP = 2^{11-1}-1 = 1023
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assign bias = {3'h0, 10'h3FF};
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// Divide exponent
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csa #(13) csa1 (exp1, ~exp2, bias, exp_s, exp_c);
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adder #(14) explogic1 ({vss, exp_s}, {vss, exp_c}, 1'b1, {open, exp_diff}, exp_cout1);
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// Sqrt exponent (check if exponent is odd)
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assign exp_odd = Float1[52] ? vss : vdd;
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adder #(14) explogic2 ({vss, exp1}, {4'h0, 10'h3ff}, exp_odd, exp_sqrt, exp_cout2);
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// Choose correct exponent
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assign expF = op_type ? exp_sqrt[13:1] : exp_diff;
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// Main Goldschmidt/Division Routine
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divconv goldy (q1, qm1, qp1, q0, qm0, qp0, rega_out, regb_out, regc_out, regd_out,
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regr_out, mantissaB, mantissaA, sel_muxa, sel_muxb, sel_muxr,
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reset, clk, load_rega, load_regb, load_regc, load_regd,
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load_regr, load_regs, P, op_type, exp_odd);
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// FSM : control divider
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fsm_div control (done, load_rega, load_regb, load_regc, load_regd,
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load_regr, load_regs, sel_muxa, sel_muxb, sel_muxr,
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clk, reset, start, error, op_type);
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// Round the mantissa to a 52-bit value, with the leading one
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// removed. The rounding units also handles special cases and
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// set the exception flags.
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rounder_div round1 (Result, DenormIO, FlagsIn,
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rm, P, OvEn, UnEn, expF,
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sel_inv, Invalid, DenormIn, signResult,
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q1, qm1, qp1, q0, qm0, qp0, regr_out);
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// Store the final result and the exception flags in registers.
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flopenr #(64) rega (clk, reset, done, Result, AS_Result);
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flopenr #(1) regb (clk, reset, done, DenormIO, Denorm);
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flopenr #(5) regc (clk, reset, done, FlagsIn, Flags);
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endmodule // fpadd
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@ -109,16 +109,8 @@ module fpu (
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logic [4:0] FPUFlagsW;
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//DECODE STAGE
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// top-level controller for FPU
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fctrl fctrl (.Funct7D(InstrD[31:25]), .OpD(InstrD[6:0]), .Rs2D(InstrD[24:20]), .Funct3D(InstrD[14:12]),
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.FRM_REGW, .IllegalFPUInstrD, .FRegWriteD, .FDivStartD, .FResultSelD, .FOpCtrlD, .FResSelD,
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@ -130,14 +122,6 @@ module fpu (
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FPUResultW,
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FRD1D, FRD2D, FRD3D);
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//*****************
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// D/E pipe registers
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//*****************
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@ -152,18 +136,6 @@ module fpu (
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{FRegWriteE, FResultSelE, FResSelE, FIntResSelE, FrmE, FmtE, RdE, FOpCtrlE, FWriteIntE});
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//EXECUTION STAGE
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// Hazard unit for FPU
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@ -198,12 +170,10 @@ module fpu (
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.en(~HoldInputs), .clear(FDivSqrtDoneE),
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.reset(reset), .clk(clk));
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fdivsqrt fdivsqrt (.DivOpType(FOpCtrlE[0]), .clk(fpdivClk), .FmtE(~FmtE), .DivInput1E, .DivInput2E,
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fpdiv fdivsqrt (.DivOpType(FOpCtrlE[0]), .clk(fpdivClk), .FmtE(~FmtE), .DivInput1E, .DivInput2E,
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.FrmE, .DivOvEn(1'b1), .DivUnEn(1'b1), .FDivStartE, .FDivResultM, .FDivSqrtFlgM,
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.FDivSqrtDoneE, .FDivBusyE, .HoldInputs, .reset);
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// first of two-stage instance of floating-point add/cvt unit
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faddcvt faddcvt (.clk, .reset, .FlushM, .StallM, .FrmM, .FOpCtrlM, .FmtE, .FmtM,
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.SrcXE, .SrcYE, .FOpCtrlE, .FAddResM, .FAddFlgM);
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@ -224,15 +194,6 @@ module fpu (
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// mux2 #(`XLEN) FWriteDataMux({{`XLEN-32{1'b0}}, SrcYE[63:32]}, SrcYE[63:64-`XLEN], FmtE, FWriteDataE);
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assign FWriteDataE = SrcYE[`XLEN-1:0];
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//*****************
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// E/M pipe registers
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//*****************
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@ -256,35 +217,17 @@ module fpu (
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flopenrc #(64) EMRegClass(clk, reset, FlushM, ~StallM, ClassResE, ClassResM);
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//BEGIN MEMORY STAGE
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mux4 #(64) FResMux(AlignedSrcAM, SgnResM, CmpResM, CvtResM, FResSelM, FResM);
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mux4 #(5) FFlgMux(5'b0, {4'b0, SgnNVM}, {4'b0, CmpNVM}, CvtFlgM, FResSelM, FFlgM);
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// mux2 #(`XLEN) SrcXAlignedMux({{`XLEN-32{1'b0}}, SrcXM[63:32]}, SrcXM[63:64-`XLEN], FmtM, SrcXMAligned);
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mux4 #(`XLEN) IntResMux(CmpResM[`XLEN-1:0], SrcXM[`XLEN-1:0], ClassResM[`XLEN-1:0], CvtResM[`XLEN-1:0], FIntResSelM, FIntResM);
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// Align SrcA to MSB when single precicion
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mux2 #(64) SrcAMux({{32{1'b1}}, SrcAM[31:0]}, {{64-`XLEN{1'b1}}, SrcAM}, FmtM, AlignedSrcAM);
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mux5 #(5) FPUFlgMux(5'b0, FMAFlgM, FAddFlgM, FDivSqrtFlgM, FFlgM, FResultSelW, SetFflagsM);
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//*****************
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// M/W pipe registers
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//*****************
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@ -302,16 +245,10 @@ module fpu (
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{FRegWriteM, FResultSelM, RdM, FmtM, FWriteIntM},
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{FRegWriteW, FResultSelW, RdW, FmtW, FWriteIntW});
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//#########################################
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// BEGIN WRITEBACK STAGE
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//#########################################
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mux2 #(64) ReadResMux({{32{1'b1}}, ReadDataW[31:0]}, {{64-`XLEN{1'b1}}, ReadDataW}, FmtW, ReadResW);
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mux5 #(64) FPUResultMux(ReadResW, FMAResW, FAddResW, FDivResultW, FResW, FResultSelW, FPUResultW);
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@ -330,4 +267,3 @@ module fpu (
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endgenerate
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endmodule // fpu
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