diff --git a/.gitignore b/.gitignore index c01ccb392..2bf93defb 100644 --- a/.gitignore +++ b/.gitignore @@ -75,6 +75,7 @@ synthDC/alib-52 synthDC/*.log synthDC/*.svf synthDC/runs/ +synthDC/PPAruns synthDC/plots/ synthDC/runArchive synthDC/hdl diff --git a/pipelined/config/buildroot/wally-config.vh b/pipelined/config/buildroot/wally-config.vh index dc6c9bb00..f11b71c0a 100644 --- a/pipelined/config/buildroot/wally-config.vh +++ b/pipelined/config/buildroot/wally-config.vh @@ -124,8 +124,6 @@ `define PLIC_NUM_SRC 53 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/buildroot/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/buildroot/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 diff --git a/pipelined/config/rv32e/wally-config.vh b/pipelined/config/rv32e/wally-config.vh index 15b2e08e7..7d083f3b5 100644 --- a/pipelined/config/rv32e/wally-config.vh +++ b/pipelined/config/rv32e/wally-config.vh @@ -130,8 +130,6 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt" `define BPRED_ENABLED 0 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 diff --git a/pipelined/config/rv32gc/wally-config.vh b/pipelined/config/rv32gc/wally-config.vh index 3522fd1e6..70124d551 100644 --- a/pipelined/config/rv32gc/wally-config.vh +++ b/pipelined/config/rv32gc/wally-config.vh @@ -128,8 +128,6 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 diff --git a/pipelined/config/rv32i/wally-config.vh b/pipelined/config/rv32i/wally-config.vh index 80d167a3d..d44072d6a 100644 --- a/pipelined/config/rv32i/wally-config.vh +++ b/pipelined/config/rv32i/wally-config.vh @@ -130,8 +130,6 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv32i/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv32i/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 diff --git a/pipelined/config/rv32ic/wally-config.vh b/pipelined/config/rv32ic/wally-config.vh index 13b2eb747..e42fd3100 100644 --- a/pipelined/config/rv32ic/wally-config.vh +++ b/pipelined/config/rv32ic/wally-config.vh @@ -128,8 +128,6 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv32ic/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv32ic/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 diff --git a/pipelined/config/rv64BP/wally-config.vh b/pipelined/config/rv64BP/wally-config.vh index 82f8446bb..3bc745eb1 100644 --- a/pipelined/config/rv64BP/wally-config.vh +++ b/pipelined/config/rv64BP/wally-config.vh @@ -130,8 +130,6 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv64BP/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv64BP/BTBPredictor.txt" `define BPRED_ENABLED 1 //`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE `define BPTYPE "BPGSHARE" // BPTWOBIT or "BPGLOBAL" or BPLOCALPAg or BPGSHARE diff --git a/pipelined/config/rv64fp/wally-config.vh b/pipelined/config/rv64fp/wally-config.vh index 68b3b84c3..cc8d1b2b8 100644 --- a/pipelined/config/rv64fp/wally-config.vh +++ b/pipelined/config/rv64fp/wally-config.vh @@ -132,8 +132,6 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/shared/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/shared/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 diff --git a/pipelined/config/rv64fpquad/wally-config.vh b/pipelined/config/rv64fpquad/wally-config.vh index 08e8006ce..0dee000e2 100644 --- a/pipelined/config/rv64fpquad/wally-config.vh +++ b/pipelined/config/rv64fpquad/wally-config.vh @@ -131,8 +131,6 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/shared/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/shared/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 diff --git a/pipelined/config/rv64gc/wally-config.vh b/pipelined/config/rv64gc/wally-config.vh index 042364aca..9afa1a679 100644 --- a/pipelined/config/rv64gc/wally-config.vh +++ b/pipelined/config/rv64gc/wally-config.vh @@ -131,8 +131,6 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/shared/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/shared/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 diff --git a/pipelined/config/rv64i/wally-config.vh b/pipelined/config/rv64i/wally-config.vh index 402c3b364..67ca51a7a 100644 --- a/pipelined/config/rv64i/wally-config.vh +++ b/pipelined/config/rv64i/wally-config.vh @@ -131,8 +131,6 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv64i/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv64i/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 diff --git a/pipelined/config/rv64ic/wally-config.vh b/pipelined/config/rv64ic/wally-config.vh index 491759359..fca1f2609 100644 --- a/pipelined/config/rv64ic/wally-config.vh +++ b/pipelined/config/rv64ic/wally-config.vh @@ -131,8 +131,6 @@ `define PLIC_GPIO_ID 3 `define PLIC_UART_ID 10 -`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt" -`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt" `define BPRED_ENABLED 1 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE `define TESTSBP 0 diff --git a/synthDC/Makefile b/synthDC/Makefile index 193153cac..3de666659 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -15,6 +15,7 @@ export MAXCORES ?= 4 # MAXOPT turns on flattening, boundary optimization, and retiming # The output netlist is hard to interpret, but significantly better PPA export MAXOPT ?= 0 +export DRIVE ?= FLOP time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD) diff --git a/synthDC/extractSummary.py b/synthDC/extractSummary.py index 85ab99ec6..8cfa48b1a 100755 --- a/synthDC/extractSummary.py +++ b/synthDC/extractSummary.py @@ -1,29 +1,171 @@ #!/usr/bin/python3 # Shreya Sanghai (ssanghai@hmc.edu) 2/28/2022 +# Madeleine Masser-Frye (mmmasserfrye@hmc.edu) 06/2022 +from collections import namedtuple import glob import re import csv +import subprocess +from matplotlib.cbook import flatten +import matplotlib.pyplot as plt +import matplotlib.lines as lines +import numpy as np -field_names = [ 'Name', 'Critical Path Length', 'Cell Area', 'Synth Time'] -data = [] -for name in glob.glob("/home/ssanghai/riscv-wally/synthDC/runs/*/reports/wallypipelinedcore_qor.rep"): - f = open(name, 'r') - # trimName = re.search("runs\/(.*?)\/reports", name).group(1) - trimName = re.search("wallypipelinedcore_(.*?)_sky9",name).group(1) - for line in f: - if "Critical Path Length" in line: - pathLen = re.search("Length: *(.*?)\\n", line).group(1) - if "Cell Area" in line: - area = re.search("Area: *(.*?)\\n", line).group(1) - if "Overall Compile Time" in line: - time = re.search("Time: *(.*?)\\n", line).group(1) - data += [{'Name' : trimName, 'Critical Path Length': pathLen, 'Cell Area' : area, 'Synth Time' :time}] +# field_names = [ 'Name', 'Critical Path Length', 'Cell Area', 'Synth Time'] +# data = [] +# for name in glob.glob("/home/ssanghai/riscv-wally/synthDC/runs/*/reports/wallypipelinedcore_qor.rep"): +# f = open(name, 'r') +# # trimName = re.search("runs\/(.*?)\/reports", name).group(1) +# trimName = re.search("wallypipelinedcore_(.*?)_sky9",name).group(1) +# for line in f: +# if "Critical Path Length" in line: +# pathLen = re.search("Length: *(.*?)\\n", line).group(1) +# if "Cell Area" in line: +# area = re.search("Area: *(.*?)\\n", line).group(1) +# if "Overall Compile Time" in line: +# time = re.search("Time: *(.*?)\\n", line).group(1) +# data += [{'Name' : trimName, 'Critical Path Length': pathLen, 'Cell Area' : area, 'Synth Time' :time}] -with open('Summary.csv', 'w') as csvfile: - writer = csv.DictWriter(csvfile, fieldnames=field_names) - writer.writeheader() - writer.writerows(data) +def synthsintocsv(): + ''' writes a CSV with one line for every available synthesis + each line contains the module, tech, width, target freq, and resulting metrics + ''' + print("This takes a moment...") + bashCommand = "find . -path '*runs/wallypipelinedcore_*' -prune" + output = subprocess.check_output(['bash','-c', bashCommand]) + allSynths = output.decode("utf-8").split('\n')[:-1] + specReg = re.compile('[a-zA-Z0-9]+') + metricReg = re.compile('-?\d+\.\d+[e]?[-+]?\d*') + file = open("Summary.csv", "w") + writer = csv.writer(file) + writer.writerow(['Width', 'Config', 'Special', 'Tech', 'Target Freq', 'Delay', 'Area']) + + for oneSynth in allSynths: + descrip = specReg.findall(oneSynth) + width = descrip[2][:4] + config = descrip[2][4:] + if descrip[3][-2:] == 'nm': + special = '' + else: + special = descrip[3] + descrip = descrip[1:] + tech = descrip[3][:-2] + freq = descrip[4] + metrics = [] + for phrase in ['Path Slack', 'Design Area']: + bashCommand = 'grep "{}" '+ oneSynth[2:]+'/reports/*qor*' + bashCommand = bashCommand.format(phrase) + try: + output = subprocess.check_output(['bash','-c', bashCommand]) + nums = metricReg.findall(str(output)) + nums = [float(m) for m in nums] + metrics += nums + except: + print(config + tech + freq + " doesn't have reports") + if metrics == []: + pass + else: + delay = 1000/int(freq) - metrics[0] + area = metrics[1] + writer.writerow([width, config, special, tech, freq, delay, area]) + file.close() + +def synthsfromcsv(filename): + Synth = namedtuple("Synth", " width config special tech freq delay area") + with open(filename, newline='') as csvfile: + csvreader = csv.reader(csvfile) + global allSynths + allSynths = list(csvreader)[1:] + for i in range(len(allSynths)): + for j in range(len(allSynths[0])): + try: allSynths[i][j] = int(allSynths[i][j]) + except: + try: allSynths[i][j] = float(allSynths[i][j]) + except: pass + allSynths[i] = Synth(*allSynths[i]) + return allSynths + +def freqPlot(tech, width, config): + ''' plots delay, area for syntheses with specified tech, module, width + ''' + + freqsL, delaysL, areasL = ([[], []] for i in range(3)) + for oneSynth in allSynths: + if (width == oneSynth.width) & (config == oneSynth.config) & (tech == oneSynth.tech) & (oneSynth.special == ''): + ind = (1000/oneSynth.delay < oneSynth.freq) # when delay is within target clock period + freqsL[ind] += [oneSynth.freq] + delaysL[ind] += [oneSynth.delay] + areasL[ind] += [oneSynth.area] + + f, (ax1, ax2) = plt.subplots(2, 1, sharex=True) + for ax in (ax1, ax2): + ax.ticklabel_format(useOffset=False, style='plain') + + for ind in [0,1]: + areas = areasL[ind] + delays = delaysL[ind] + freqs = freqsL[ind] + + c = 'blue' if ind else 'green' + ax1.scatter(freqs, delays, color=c) + ax2.scatter(freqs, areas, color=c) + + freqs = list(flatten(freqsL)) + delays = list(flatten(delaysL)) + areas = list(flatten(areasL)) + + legend_elements = [lines.Line2D([0], [0], color='green', ls='', marker='o', label='timing achieved'), + lines.Line2D([0], [0], color='blue', ls='', marker='o', label='slack violated')] + + ax1.legend(handles=legend_elements) + ax2.set_xlabel("Target Freq (MHz)") + ax1.set_ylabel('Delay (ns)') + ax2.set_ylabel('Area (sq microns)') + ax1.set_title(tech + ' ' + width +config) + plt.savefig('./plots/wally/' + tech + '_' + width + config + '.png') + # plt.show() + +def areaDelay(width, tech, freq, config=None, special=None): + delays, areas, labels = ([] for i in range(3)) + + for oneSynth in allSynths: + if (width == oneSynth.width) & (tech == oneSynth.tech) & (freq == oneSynth.freq): + if (special != None) & (oneSynth.special == special): + delays += [oneSynth.delay] + areas += [oneSynth.area] + labels += [oneSynth.config] + elif (config != None) & (oneSynth.config == config): + delays += [oneSynth.delay] + areas += [oneSynth.area] + labels += [oneSynth.special] + else: + delays += [oneSynth.delay] + areas += [oneSynth.area] + labels += [oneSynth.config + '_' + oneSynth.special] + + f, (ax1) = plt.subplots(1, 1) + plt.scatter(delays, areas) + plt.xlabel('Delay (ns)') + plt.ylabel('Area (sq microns)') + titleStr = tech + ' ' +width + if config: titleStr += config + if special: titleStr += special + titleStr = titleStr + ' (target freq: ' + str(freq) + ')' + plt.title(titleStr) + + for i in range(len(labels)): + plt.annotate(labels[i], (delays[i], areas[i]), textcoords="offset points", xytext=(0,10), ha='center') + + plt.savefig('./plots/wally/areaDelay ' + titleStr + '.png') + +# ending freq in 42 means fpu was turned off manually + +if __name__ == '__main__': + synthsintocsv() + synthsfromcsv('Summary.csv') + freqPlot('tsmc28', 'rv64', 'gc') + areaDelay('rv32', 'tsmc28', 4200, config='gc') + areaDelay('rv32', 'tsmc28', 3042, special='') - \ No newline at end of file diff --git a/synthDC/runConfigsSynth.sh b/synthDC/runConfigsSynth.sh index 40c4b6a8f..84e1f6d77 100755 --- a/synthDC/runConfigsSynth.sh +++ b/synthDC/runConfigsSynth.sh @@ -1,5 +1,5 @@ #!/usr/bin/bash -rm -r runs/* +# rm -r runs/* make clean make del make copy diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 5ceb577b7..4d444682a 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -119,12 +119,14 @@ if {$tech == "sky130"} { } elseif {$tech == "sky90"} { if {$drive == "INV"} { set_driving_cell -lib_cell scc9gena_inv_1 -pin Y $all_in_ex_clk - } else { + } elseif {$drive == "FLOP"} { set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk } } elseif {$tech == "tsmc28"} { if {$drive == "INV"} { set_driving_cell -lib_cell INVD1BWP30P140 -pin ZN $all_in_ex_clk + } elseif {$drive == "FLOP"} { + set_driving_cell -lib_cell DFQD1BWP30P140 -pin Q $all_in_ex_clk } } @@ -138,12 +140,14 @@ if {$tech == "sky130"} { } elseif {$tech == "sky90"} { if {$drive == "INV"} { set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_inv_4/A] * 1] [all_outputs] - } else { + } elseif {$drive == "FLOP"} { set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs] } } elseif {$tech == "tsmc28"} { if {$drive == "INV"} { set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/INVD4BWP30P140/I] * 1] [all_outputs] + } elseif {$drive == "FLOP"} { + set_load [expr [load_of tcbn28hpcplusbwp30p140tt0p9v25c/DFQD1BWP30P140/D] * 1] [all_outputs] } }