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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

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Kip Macsai-Goren 2021-05-25 15:28:19 -04:00
commit 45e7628e90
5 changed files with 693 additions and 649 deletions
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54
wally-pipelined/src/fpu/FPregfile.sv Normal file
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@ -0,0 +1,54 @@
///////////////////////////////////////////
// regfile.sv
//
// Written: David_Harris@hmc.edu 9 January 2021
// Modified:
//
// Purpose: 4-port register file
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
module FPregfile (
input logic clk, reset,
input logic we4,
input logic [ 4:0] a1, a2, a3, a4,
input logic [`XLEN-1:0] wd4,
output logic [`XLEN-1:0] rd1, rd2, rd3);
logic [`XLEN-1:0] rf[31:0];
integer i;
// three ported register file
// read three ports combinationally (A1/RD1, A2/RD2, A3/RD3)
// write fourth port on rising edge of clock (A4/WD4/WE4)
// write occurs on falling edge of clock
// reset is intended for simulation only, not synthesis
always_ff @(negedge clk or posedge reset)
if (reset) for(i=0; i<32; i++) rf[i] <= 0;
else if (we4) rf[a4] <= wd4;
assign #2 rd1 = rf[a1];
assign #2 rd2 = rf[a2];
assign #2 rd3 = rf[a3];
endmodule // regfile

52
wally-pipelined/src/fpu/FPregfile.sv~ Normal file
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@ -0,0 +1,52 @@
///////////////////////////////////////////
// regfile.sv
//
// Written: David_Harris@hmc.edu 9 January 2021
// Modified:
//
// Purpose: 3-port register file
//
// A component of the Wally configurable RISC-V project.
//
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
//
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
// is furnished to do so, subject to the following conditions:
//
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
///////////////////////////////////////////
`include "wally-config.vh"
module regfile (
input logic clk, reset,
input logic we3,
input logic [ 4:0] a1, a2, a3,
input logic [`XLEN-1:0] wd3,
output logic [`XLEN-1:0] rd1, rd2);
logic [`XLEN-1:0] rf[31:1];
integer i;
// three ported register file
// read two ports combinationally (A1/RD1, A2/RD2)
// write third port on rising edge of clock (A3/WD3/WE3)
// write occurs on falling edge of clock
// register 0 hardwired to 0
// reset is intended for simulation only, not synthesis
always_ff @(negedge clk or posedge reset)
if (reset) for(i=1; i<32; i++) rf[i] <= 0;
else if (we3) rf[a3] <= wd3;
assign #2 rd1 = (a1 != 0) ? rf[a1] : 0;
assign #2 rd2 = (a2 != 0) ? rf[a2] : 0;
endmodule

160
wally-pipelined/src/fpu/fpu.sv
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@ -61,10 +61,7 @@ module fpu (
integer XLENDIFFN; integer XLENDIFFN;
assign XLENDIFFN = 63 - `XLEN; assign XLENDIFFN = 63 - `XLEN;
//#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*# // BEGIN PIPELINE CONTROL LOGIC
//BEGIN PIPELINE CONTROL LOGIC
//
logic PipeEnableDE; logic PipeEnableDE;
logic PipeEnableEM; logic PipeEnableEM;
logic PipeEnableMW; logic PipeEnableMW;
@ -77,25 +74,15 @@ module fpu (
localparam PipeClear = 1'b0; localparam PipeClear = 1'b0;
localparam PipeEnable = 1'b1; localparam PipeEnable = 1'b1;
always_comb begin always_comb begin
PipeEnableDE = ~StallE; PipeEnableDE = ~StallE;
PipeEnableEM = ~StallM; PipeEnableEM = ~StallM;
PipeEnableMW = ~StallW; PipeEnableMW = ~StallW;
PipeClearDE = FlushE; PipeClearDE = FlushE;
PipeClearEM = FlushM; PipeClearEM = FlushM;
PipeClearMW = FlushW; PipeClearMW = FlushW;
end end
// // Wally-spec D stage control logic signal instantiation
//END PIPELINE CONTROL LOGIC
//#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#*#
//#########################################
//BEGIN DECODE STAGE
//
//wally-spec D stage control logic signal instantiation
logic FRegWriteD; logic FRegWriteD;
logic [2:0] FResultSelD; logic [2:0] FResultSelD;
logic [2:0] FrmD; logic [2:0] FrmD;
@ -110,6 +97,7 @@ module fpu (
logic [1:0] Input1MuxD, Input2MuxD; logic [1:0] Input1MuxD, Input2MuxD;
logic Input3MuxD; logic Input3MuxD;
logic In2UsedD, In3UsedD; logic In2UsedD, In3UsedD;
//Hazard unit for FPU //Hazard unit for FPU
fpuhazard hazard(.Adr1(InstrD[19:15]), .Adr2(InstrD[24:20]), .Adr3(InstrD[31:27]), .*); fpuhazard hazard(.Adr1(InstrD[19:15]), .Adr2(InstrD[24:20]), .Adr3(InstrD[31:27]), .*);
@ -127,20 +115,17 @@ module fpu (
logic [`XLEN-1:0] ReadData1D, ReadData2D, ReadData3D; logic [`XLEN-1:0] ReadData1D, ReadData2D, ReadData3D;
//regfile instantiation //regfile instantiation
freg3adr fpregfile (FmtW, reset, PipeClear, clk, RdW, FRegWriteW, InstrD[19:15], InstrD[24:20], InstrD[31:27], FPUResultDirW, ReadData1D, ReadData2D, ReadData3D); //freg3adr fpregfile (FmtW, reset, PipeClear, clk, RdW,
// FRegWriteW,
// InstrD[19:15], InstrD[24:20], InstrD[31:27],
// FPUResultDirW,
// ReadData1D, ReadData2D, ReadData3D);
FPregfile fpregfile (clk, reset, FRegWriteW,
InstrD[19:15], InstrD[24:20], InstrD[31:27], RdW,
FPUResultDirW,
ReadData1D, ReadData2D, ReadData3D);
//always_comb begin // wally-spec E stage control logic signal instantiation
// FrmW = InstrD[14:12];
//end
//
//END DECODE STAGE
//#########################################
//*****************************************
//BEGIN D/E PIPE
//
//wally-spec E stage control logic signal instantiation
logic FRegWriteE; logic FRegWriteE;
logic [2:0] FResultSelE; logic [2:0] FResultSelE;
logic [2:0] FrmE; logic [2:0] FrmE;
@ -249,32 +234,24 @@ module fpu (
flopenrc #(1) DEReg16(clk, reset, PipeClearDE, PipeEnableDE, OutputInput2D, OutputInput2E); flopenrc #(1) DEReg16(clk, reset, PipeClearDE, PipeEnableDE, OutputInput2D, OutputInput2E);
flopenrc #(2) DEReg17(clk, reset, PipeClearDE, PipeEnableDE, FMemRWD, FMemRWE); flopenrc #(2) DEReg17(clk, reset, PipeClearDE, PipeEnableDE, FMemRWD, FMemRWE);
//
//END D/E PIPE
//*****************************************
//#########################################
//BEGIN EXECUTION STAGE
//
// input muxs for forwarding // input muxs for forwarding
mux4 #(64) Input1Emux(ReadData1E, FPUResultDirW, FPUResultDirE, SrcAM, Input1MuxE, Input1tmpE); mux4 #(64) Input1Emux(ReadData1E, FPUResultDirW, FPUResultDirE, SrcAM, Input1MuxE, Input1tmpE);
mux3 #(64) Input2Emux(ReadData2E, FPUResultDirW, FPUResultDirE, Input2MuxE, Input2E); mux3 #(64) Input2Emux(ReadData2E, FPUResultDirW, FPUResultDirE, Input2MuxE, Input2E);
mux2 #(64) Input3Emux(ReadData3E, FPUResultDirE, Input3MuxE, Input3E); mux2 #(64) Input3Emux(ReadData3E, FPUResultDirE, Input3MuxE, Input3E);
mux2 #(64) OutputInput2mux(Input1tmpE, Input2E, OutputInput2E, Input1E); mux2 #(64) OutputInput2mux(Input1tmpE, Input2E, OutputInput2E, Input1E);
fma1 fma1 (.*); fma1 fma1 (.*);
//first and only instance of floating-point divider //first and only instance of floating-point divider
fpdiv fpdivsqrt (.*); fpdiv fpdivsqrt (.*);
//first of two-stage instance of floating-point add/cvt unit //first of two-stage instance of floating-point add/cvt unit
fpuaddcvt1 fpadd1 (AddSumE, AddSumTcE, AddSelInvE, AddExpPostSumE, AddCorrSignE, AddOp1NormE, AddOp2NormE, AddOpANormE, AddOpBNormE, AddInvalidE, AddDenormInE, AddConvertE, AddSwapE, AddNormOvflowE, AddSignAE, AddFloat1E, AddFloat2E, AddExp1DenormE, AddExp2DenormE, AddExponentE, Input1E, Input2E, FrmE, OpCtrlE, FmtE); fpuaddcvt1 fpadd1 (AddSumE, AddSumTcE, AddSelInvE, AddExpPostSumE,
AddCorrSignE, AddOp1NormE, AddOp2NormE, AddOpANormE,
AddOpBNormE, AddInvalidE, AddDenormInE, AddConvertE,
AddSwapE, AddNormOvflowE, AddSignAE, AddFloat1E, AddFloat2E,
AddExp1DenormE, AddExp2DenormE, AddExponentE,
Input1E, Input2E, FrmE, OpCtrlE, FmtE);
//first of two-stage instance of floating-point comparator //first of two-stage instance of floating-point comparator
fpucmp1 fpcmp1 (WE, XE, ANaNE, BNaNE, AzeroE, BzeroE, Input1E, Input2E, OpCtrlE[1:0]); fpucmp1 fpcmp1 (WE, XE, ANaNE, BNaNE, AzeroE, BzeroE, Input1E, Input2E, OpCtrlE[1:0]);
@ -290,27 +267,27 @@ module fpu (
//truncate to 64 bits //truncate to 64 bits
//(causes warning during compilation - case never reached) //(causes warning during compilation - case never reached)
// if(`XLEN > 64) begin // ***KEP this isn't usedand it causes a lint error // if(`XLEN > 64) begin // ***KEP this isn't usedand it causes a lint error
// DivOp1 = Input1E[`XLEN-1:`XLEN-64]; // DivOp1 = Input1E[`XLEN-1:`XLEN-64];
// DivOp2 = Input2E[`XLEN-1:`XLEN-64]; // DivOp2 = Input2E[`XLEN-1:`XLEN-64];
// AddOp1E = Input1E[`XLEN-1:`XLEN-64]; // AddOp1E = Input1E[`XLEN-1:`XLEN-64];
// AddOp2E = Input2E[`XLEN-1:`XLEN-64]; // AddOp2E = Input2E[`XLEN-1:`XLEN-64];
// CmpOp1E = Input1E[`XLEN-1:`XLEN-64]; // CmpOp1E = Input1E[`XLEN-1:`XLEN-64];
// CmpOp2E = Input2E[`XLEN-1:`XLEN-64]; // CmpOp2E = Input2E[`XLEN-1:`XLEN-64];
// SgnOp1E = Input1E[`XLEN-1:`XLEN-64]; // SgnOp1E = Input1E[`XLEN-1:`XLEN-64];
// SgnOp2E = Input2E[`XLEN-1:`XLEN-64]; // SgnOp2E = Input2E[`XLEN-1:`XLEN-64];
// end // end
// //zero extend to 64 bits // //zero extend to 64 bits
// else begin // else begin
// DivOp1 = {Input1E,{64-`XLEN{1'b0}}}; // DivOp1 = {Input1E,{64-`XLEN{1'b0}}};
// DivOp2 = {Input2E,{64-`XLEN{1'b0}}}; // DivOp2 = {Input2E,{64-`XLEN{1'b0}}};
// AddOp1E = {Input1E,{64-`XLEN{1'b0}}}; // AddOp1E = {Input1E,{64-`XLEN{1'b0}}};
// AddOp2E = {Input2E,{64-`XLEN{1'b0}}}; // AddOp2E = {Input2E,{64-`XLEN{1'b0}}};
// CmpOp1E = {Input1E,{64-`XLEN{1'b0}}}; // CmpOp1E = {Input1E,{64-`XLEN{1'b0}}};
// CmpOp2E = {Input2E,{64-`XLEN{1'b0}}}; // CmpOp2E = {Input2E,{64-`XLEN{1'b0}}};
// SgnOp1E = {Input1E,{64-`XLEN{1'b0}}}; // SgnOp1E = {Input1E,{64-`XLEN{1'b0}}};
// SgnOp2E = {Input2E,{64-`XLEN{1'b0}}}; // SgnOp2E = {Input2E,{64-`XLEN{1'b0}}};
// end // end
//assign op codes //assign op codes
AddOpTypeE[3:0] = OpCtrlE[3:0]; AddOpTypeE[3:0] = OpCtrlE[3:0];
@ -323,14 +300,6 @@ module fpu (
//E stage control signal interfacing between wally spec and OSU fp hardware //E stage control signal interfacing between wally spec and OSU fp hardware
//op codes //op codes
//
//END EXECUTION STAGE
//#########################################
//*****************************************
//BEGIN E/M PIPE
//
//wally-spec M stage control logic signal instantiation //wally-spec M stage control logic signal instantiation
logic FRegWriteM; logic FRegWriteM;
logic [2:0] FResultSelM; logic [2:0] FResultSelM;
@ -499,19 +468,8 @@ module fpu (
flopenrc #(1) EMReg7(clk, reset, PipeClearEM, PipeEnableEM, FWriteIntE, FWriteIntM); flopenrc #(1) EMReg7(clk, reset, PipeClearEM, PipeEnableEM, FWriteIntE, FWriteIntM);
flopenrc #(2) EMReg8(clk, reset, PipeClearEM, PipeEnableEM, FMemRWE, FMemRWM); flopenrc #(2) EMReg8(clk, reset, PipeClearEM, PipeEnableEM, FMemRWE, FMemRWM);
//
//END E/M PIPE
//*****************************************
//#########################################
//BEGIN MEMORY STAGE
//
assign FWriteDataM = Input1M; assign FWriteDataM = Input1M;
mux2 #(64) LoadStoreResultMux(HRDATA, Input1M, |OpCtrlM[2:1], LoadStoreResultM); mux2 #(64) LoadStoreResultMux(HRDATA, Input1M, |OpCtrlM[2:1], LoadStoreResultM);
fma2 fma2(.*); fma2 fma2(.*);
//second instance of two-stage floating-point add/cvt unit //second instance of two-stage floating-point add/cvt unit
@ -520,15 +478,6 @@ module fpu (
//second instance of two-stage floating-point comparator //second instance of two-stage floating-point comparator
fpucmp2 fpcmp2 (CmpInvalidM, CmpFCCM, ANaNM, BNaNM, AzeroM, BzeroM, WM, XM, CmpSelM, CmpOp1M, CmpOp2M); fpucmp2 fpcmp2 (CmpInvalidM, CmpFCCM, ANaNM, BNaNM, AzeroM, BzeroM, WM, XM, CmpSelM, CmpOp1M, CmpOp2M);
//
//END MEMORY STAGE
//#########################################
//*****************************************
//BEGIN M/W PIPE
//
//wally-spec W stage control logic signal instantiation //wally-spec W stage control logic signal instantiation
logic [2:0] FResultSelW; logic [2:0] FResultSelW;
@ -606,14 +555,6 @@ module fpu (
flopenrc #(64) MWReg6(clk, reset, PipeClearMW, PipeEnableMW, LoadStoreResultM, LoadStoreResultW); flopenrc #(64) MWReg6(clk, reset, PipeClearMW, PipeEnableMW, LoadStoreResultM, LoadStoreResultW);
flopenrc #(1) MWReg7(clk, reset, PipeClearMW, PipeEnableMW, FWriteIntM, FWriteIntW); flopenrc #(1) MWReg7(clk, reset, PipeClearMW, PipeEnableMW, FWriteIntM, FWriteIntW);
////END M/W PIPE
//*****************************************
//#########################################
//BEGIN WRITEBACK STAGE
//
//flag signal mux via in-line ternaries //flag signal mux via in-line ternaries
logic [4:0] FPUFlagsW; logic [4:0] FPUFlagsW;
//if bit 2 is active set to sign flags - otherwise: //if bit 2 is active set to sign flags - otherwise:
@ -622,10 +563,10 @@ module fpu (
//iff bit one is low - if bit zero is active set to add/cvt flags - otherwise //iff bit one is low - if bit zero is active set to add/cvt flags - otherwise
//set to div/sqrt flags //set to div/sqrt flags
//assign FPUFlagsW = (FResultSelW[2]) ? (SgnFlagsW) : ( //assign FPUFlagsW = (FResultSelW[2]) ? (SgnFlagsW) : (
// (FResultSelW[1]) ? // (FResultSelW[1]) ?
// ( (FResultSelW[0]) ? (FmaFlagsW) : ({CmpInvalidW,4'b0000}) ) // ( (FResultSelW[0]) ? (FmaFlagsW) : ({CmpInvalidW,4'b0000}) )
// : ( (FResultSelW[0]) ? (AddFlagsW) : (DivFlagsW) ) // : ( (FResultSelW[0]) ? (AddFlagsW) : (DivFlagsW) )
// ); // );
always_comb begin always_comb begin
case (FResultSelW) case (FResultSelW)
// div/sqrt // div/sqrt
@ -686,9 +627,9 @@ module fpu (
//zero extension //zero extension
// Teo 04/13/2021 // Teo 04/13/2021
// Commented out XLENDIFF{1'b0} due to error: // Commented out XLENDIFF{1'b0} due to error:
// Repetition multiplier must be constant. // Repetition multiplier must be constant.
//if(`XLEN > 64) begin //if(`XLEN > 64) begin
// FPUResultW = {FPUResultDirW,{XLENDIFF{1'b0}}}; // FPUResultW = {FPUResultDirW,{XLENDIFF{1'b0}}};
@ -701,10 +642,5 @@ module fpu (
end end
// endmodule // fpu
//END WRITEBACK STAGE
//#########################################
endmodule

1
wally-pipelined/src/ifu/bpred.sv
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@ -75,6 +75,7 @@ module bpred
if (`BPTYPE == "BPTWOBIT") begin:Predictor if (`BPTYPE == "BPTWOBIT") begin:Predictor
twoBitPredictor DirPredictor(.clk(clk), twoBitPredictor DirPredictor(.clk(clk),
.reset(reset), .reset(reset),
.StallF(StallF),
.LookUpPC(PCNextF), .LookUpPC(PCNextF),
.Prediction(BPPredF), .Prediction(BPPredF),
// update // update

5
wally-pipelined/src/ifu/twoBitPredictor.sv
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@ -32,6 +32,7 @@ module twoBitPredictor
) )
(input logic clk, (input logic clk,
input logic reset, input logic reset,
input logic StallF,
input logic [`XLEN-1:0] LookUpPC, input logic [`XLEN-1:0] LookUpPC,
output logic [1:0] Prediction, output logic [1:0] Prediction,
// update // update
@ -54,11 +55,11 @@ module twoBitPredictor
assign LookUpPCIndex = {LookUpPC[Depth+1] ^ LookUpPC[1], LookUpPC[Depth:2]}; assign LookUpPCIndex = {LookUpPC[Depth+1] ^ LookUpPC[1], LookUpPC[Depth:2]};
SRAM2P1R1W #(Depth, 2) memory(.clk(clk), SRAM2P1R1W #(Depth, 2) PHT(.clk(clk),
.reset(reset), .reset(reset),
.RA1(LookUpPCIndex), .RA1(LookUpPCIndex),
.RD1(PredictionMemory), .RD1(PredictionMemory),
.REN1(1'b1), .REN1(~StallF),
.WA1(UpdatePCIndex), .WA1(UpdatePCIndex),
.WD1(UpdatePrediction), .WD1(UpdatePrediction),
.WEN1(UpdateEN), .WEN1(UpdateEN),