From c1c564d54c4a3e98dc345d38c1936d5f16bb2279 Mon Sep 17 00:00:00 2001 From: Kip Macsai-Goren Date: Mon, 19 Jul 2021 15:06:14 -0400 Subject: [PATCH 1/3] added changes to priority encoders from synthesis branch (correctly this time I hope) --- wally-pipelined/src/mmu/pmpadrdec.sv | 39 ++++++++++++------- wally-pipelined/src/mmu/pmpchecker.sv | 11 ++---- .../{tlbpriority.sv => prioritycircuit.sv} | 18 +++++++-- wally-pipelined/src/mmu/tlblru.sv | 2 +- 4 files changed, 45 insertions(+), 25 deletions(-) rename wally-pipelined/src/mmu/{tlbpriority.sv => prioritycircuit.sv} (81%) diff --git a/wally-pipelined/src/mmu/pmpadrdec.sv b/wally-pipelined/src/mmu/pmpadrdec.sv index 5d2174f47..0fe2b2d7a 100644 --- a/wally-pipelined/src/mmu/pmpadrdec.sv +++ b/wally-pipelined/src/mmu/pmpadrdec.sv @@ -34,9 +34,10 @@ module pmpadrdec ( input logic [7:0] PMPCfg, input logic [`XLEN-1:0] PMPAdr, input logic PAgePMPAdrIn, - input logic NoLowerMatchIn, +// input logic NoLowerMatchIn, + input logic FirstMatch, output logic PAgePMPAdrOut, - output logic NoLowerMatchOut, +// output logic NoLowerMatchOut, output logic Match, Active, output logic L, X, W, R ); @@ -47,7 +48,7 @@ module pmpadrdec ( logic TORMatch, NAMatch; logic PAltPMPAdr; - logic FirstMatch; +// logic FirstMatch; logic [`PA_BITS-1:0] CurrentAdrFull; logic [1:0] AdrMode; @@ -69,16 +70,30 @@ module pmpadrdec ( // verilator lint_off UNOPTFLAT logic [`PA_BITS-1:0] Mask; - genvar i; + //genvar i; // create a mask of which bits to ignore - generate - assign Mask[1:0] = 2'b11; - assign Mask[2] = (AdrMode == NAPOT); // mask has 0s in upper bis for NA4 region - for (i=3; i < `PA_BITS; i=i+1) begin:mask - assign Mask[i] = Mask[i-1] & PMPAdr[i-3]; // NAPOT mask: 1's indicate bits to ignore - end - endgenerate + // generate + // assign Mask[1:0] = 2'b11; + // assign Mask[2] = (AdrMode == NAPOT); // mask has 0s in upper bis for NA4 region + // for (i=3; i < `PA_BITS; i=i+1) begin:mask + // assign Mask[i] = Mask[i-1] & PMPAdr[i-3]; // NAPOT mask: 1's indicate bits to ignore + // end + // endgenerate + prioritycircuit #(.ENTRIES(`PA_BITS-2), .FINAL_OP("NONE")) maskgen(.a(~PMPAdr[`PA_BITS-3:0]), .FirstPin(AdrMode==NAPOT), .y(Mask[`PA_BITS-1:2])); + assign Mask[1:0] = 2'b11; + + // *** possible experiments: + /* PA < PMP addr could be in its own module, + preeserving hierarchy so we can know if this is the culprit on the critical path + Should take logarthmic time, so more like 6 levels than 40 should be expected + + update mask generation + Should be concurrent with the subtraction/comparison + if one is the critical path, the other shouldn't be which makes us think the mask generation is the culprit. + + Hopefully just use the priority circuit here + */ // verilator lint_on UNOPTFLAT assign NAMatch = &((PhysicalAddress ~^ CurrentAdrFull) | Mask); @@ -87,8 +102,6 @@ module pmpadrdec ( (AdrMode == NA4 || AdrMode == NAPOT) ? NAMatch : 0; - assign FirstMatch = NoLowerMatchIn & Match; - assign NoLowerMatchOut = NoLowerMatchIn & ~Match; assign L = PMPCfg[7] & FirstMatch; assign X = PMPCfg[2] & FirstMatch; assign W = PMPCfg[1] & FirstMatch; diff --git a/wally-pipelined/src/mmu/pmpchecker.sv b/wally-pipelined/src/mmu/pmpchecker.sv index 9c7f11da4..eac4cc475 100644 --- a/wally-pipelined/src/mmu/pmpchecker.sv +++ b/wally-pipelined/src/mmu/pmpchecker.sv @@ -55,12 +55,9 @@ module pmpchecker ( // Bit i is high when the address falls in PMP region i logic EnforcePMP; logic [7:0] PMPCfg[`PMP_ENTRIES-1:0]; - logic [`PMP_ENTRIES-1:0] Match; // PMP Entry matches + logic [`PMP_ENTRIES-1:0] Match, FirstMatch; // PMP Entry matches logic [`PMP_ENTRIES-1:0] Active; // PMP register i is non-null logic [`PMP_ENTRIES-1:0] L, X, W, R; // PMP matches and has flag set - // verilator lint_off UNOPTFLAT - logic [`PMP_ENTRIES-1:0] NoLowerMatch; // None of the lower PMP entries match - // verilator lint_on UNOPTFLAT logic [`PMP_ENTRIES-1:0] PAgePMPAdr; // for TOR PMP matching, PhysicalAddress > PMPAdr[i] genvar i,j; @@ -70,9 +67,9 @@ module pmpchecker ( .PMPAdr(PMPADDR_ARRAY_REGW), .PAgePMPAdrIn({PAgePMPAdr[`PMP_ENTRIES-2:0], 1'b1}), .PAgePMPAdrOut(PAgePMPAdr), - .NoLowerMatchIn({NoLowerMatch[`PMP_ENTRIES-2:0], 1'b1}), - .NoLowerMatchOut(NoLowerMatch), - .Match, .Active, .L, .X, .W, .R); + .FirstMatch, .Match, .Active, .L, .X, .W, .R); + + prioritycircuit #(.ENTRIES(`PMP_ENTRIES), .FINAL_OP("AND")) pmppriority(.a(Match), .FirstPin(1'b1), .y(FirstMatch)); // Take the ripple gates/signals out of the pmpadrdec and into another unit. // Only enforce PMP checking for S and U modes when at least one PMP is active or in Machine mode when L bit is set in selected region assign EnforcePMP = (PrivilegeModeW == `M_MODE) ? |L : |Active; diff --git a/wally-pipelined/src/mmu/tlbpriority.sv b/wally-pipelined/src/mmu/prioritycircuit.sv similarity index 81% rename from wally-pipelined/src/mmu/tlbpriority.sv rename to wally-pipelined/src/mmu/prioritycircuit.sv index 5096cae60..df44b35f9 100644 --- a/wally-pipelined/src/mmu/tlbpriority.sv +++ b/wally-pipelined/src/mmu/prioritycircuit.sv @@ -1,5 +1,5 @@ /////////////////////////////////////////// -// tlbpriority.sv +// prioritycircuit.sv // // Written: tfleming@hmc.edu & jtorrey@hmc.edu 7 April 2021 // Modified: Teo Ene 15 Apr 2021: @@ -30,8 +30,10 @@ `include "wally-config.vh" -module tlbpriority #(parameter ENTRIES = 8) ( +module prioritycircuit #(parameter ENTRIES = 8, + parameter FINAL_OP = "AND") ( input logic [ENTRIES-1:0] a, + input logic FirstPin, output logic [ENTRIES-1:0] y ); // verilator lint_off UNOPTFLAT @@ -40,11 +42,19 @@ module tlbpriority #(parameter ENTRIES = 8) ( // generate thermometer code mask genvar i; generate - assign nolower[0] = 1; + assign nolower[0] = FirstPin; for (i=1; i Date: Mon, 19 Jul 2021 16:19:24 -0400 Subject: [PATCH 2/3] put MTIMECMP's reset value back to 0 because the reset value of -1 broke the MCAUSE tests --- wally-pipelined/src/uncore/clint.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/wally-pipelined/src/uncore/clint.sv b/wally-pipelined/src/uncore/clint.sv index 79f68087a..817096d30 100644 --- a/wally-pipelined/src/uncore/clint.sv +++ b/wally-pipelined/src/uncore/clint.sv @@ -82,7 +82,7 @@ module clint ( always_ff @(posedge HCLK or negedge HRESETn) if (~HRESETn) begin MSIP <= 0; - MTIMECMP <= (64)'(-1); + MTIMECMP <= (64)'(0); // MTIMECMP is not reset end else if (memwrite) begin if (entryd == 16'h0000) MSIP <= HWDATA[0]; @@ -112,7 +112,7 @@ module clint ( always_ff @(posedge HCLK or negedge HRESETn) if (~HRESETn) begin MSIP <= 0; - MTIMECMP <= (64)'(-1); + MTIMECMP <= (64)'(0); // MTIMECMP is not reset end else if (memwrite) begin if (entryd == 16'h0000) MSIP <= HWDATA[0]; From bb2e3b1e023fd49e7e8b960c682c24edb70d30bc Mon Sep 17 00:00:00 2001 From: bbracker Date: Mon, 19 Jul 2021 16:22:05 -0400 Subject: [PATCH 3/3] remove busybear from regression because it is not keeping up with buildroot's changes to testbench-linux --- wally-pipelined/regression/regression-wally.py | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/wally-pipelined/regression/regression-wally.py b/wally-pipelined/regression/regression-wally.py index 234c869a8..2cd2d77ec 100755 --- a/wally-pipelined/regression/regression-wally.py +++ b/wally-pipelined/regression/regression-wally.py @@ -23,11 +23,11 @@ TestCase = namedtuple("TestCase", ['name', 'cmd', 'grepstr']) # edit this list to add more test cases configs = [ - TestCase( - name="busybear", - cmd="vsim -do wally-busybear-batch.do -c > {}", - grepstr="loaded 100000 instructions" - ), + #TestCase( + # name="busybear", + # cmd="vsim -do wally-busybear-batch.do -c > {}", + # grepstr="loaded 100000 instructions" + #), TestCase( name="buildroot", cmd="vsim -do wally-buildroot-batch.do -c > {}",