From 84ffdfc8c4da81929c18d8cc891215d040a2aa52 Mon Sep 17 00:00:00 2001 From: bbracker Date: Wed, 9 Feb 2022 02:29:47 +0000 Subject: [PATCH 01/14] add tracegen support for interrupt parsing --- linux/testvector-generation/genTrace.sh | 10 +++++-- .../testvector-generation/parseGDBtoTrace.py | 28 +++++++++++++++---- linux/testvector-generation/parseQemuToGDB.py | 1 - 3 files changed, 30 insertions(+), 9 deletions(-) diff --git a/linux/testvector-generation/genTrace.sh b/linux/testvector-generation/genTrace.sh index 82f9e48be..e085251ba 100755 --- a/linux/testvector-generation/genTrace.sh +++ b/linux/testvector-generation/genTrace.sh @@ -4,10 +4,12 @@ imageDir=$RISCV/buildroot/output/images outDir=$RISCV/linux-testvectors recordFile="$outDir/all.qemu" traceFile="$outDir/all.txt" +interruptsFile="$outDir/interrupts.txt" read -p "Warning: running this script will overwrite the contents of: * $recordFile * $traceFile + * $interruptsFile Would you like to proceed? (y/n) " -n 1 -r echo if [[ $REPLY =~ ^[Yy]$ ]] @@ -17,8 +19,10 @@ then sudo chown cad $outDir sudo touch $recordFile sudo touch $traceFile + sudo touch $interruptsFile sudo chmod a+rw $recordFile sudo chmod a+rw $traceFile + sudo chmod a+rw $interruptsFile # Compile Devicetree from Source dtc -I dts -O dtb ../devicetree/virt-trimmed.dts > ../devicetree/virt-trimmed.dtb @@ -29,15 +33,17 @@ then -nographic -serial /dev/null \ -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ -singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=record,rrfile=$recordFile \ - -d nochain,cpu,in_asm \ + -d nochain,cpu,in_asm,int \ -gdb tcp::$tcpPort -S \ - 2>&1 >/dev/null | ./parseQemuToGDB.py | ./parseGDBtoTrace.py | ./remove_dup.awk > $traceFile) \ + 2>&1 >/dev/null | ./parseQemuToGDB.py | ./parseGDBtoTrace.py $interruptsFile | ./remove_dup.awk > $traceFile) \ & riscv64-unknown-elf-gdb -quiet -x genTrace.gdb -ex "genTrace $tcpPort \"$imageDir/vmlinux\"" # Cleanup sudo chown cad $recordFile sudo chown cad $traceFile + sudo chown cad $interruptsFile sudo chmod o-w $recordFile sudo chmod o-w $traceFile + sudo chmod o-w $interruptsFile fi diff --git a/linux/testvector-generation/parseGDBtoTrace.py b/linux/testvector-generation/parseGDBtoTrace.py index ab63330fd..69bdfceb9 100755 --- a/linux/testvector-generation/parseGDBtoTrace.py +++ b/linux/testvector-generation/parseGDBtoTrace.py @@ -130,6 +130,13 @@ def PrintInstr(instr, fp): fp.write(' CSR {}'.format(CSRStr)) fp.write('\n') +# ========= +# Main Code +# ========= +# Parse argument for interrupt file +if len(sys.argv) != 2: + sys.exit('Error parseGDBtoTrace.py expects 1 arg:\n >') +interruptFname = sys.argv[1] # reg number RegNumber = {'zero': 0, 'ra': 1, 'sp': 2, 'gp': 3, 'tp': 4, 't0': 5, 't1': 6, 't2': 7, 's0': 8, 's1': 9, 'a0': 10, 'a1': 11, 'a2': 12, 'a3': 13, 'a4': 14, 'a5': 15, 'a6': 16, 'a7': 17, 's2': 18, 's3': 19, 's4': 20, 's5': 21, 's6': 22, 's7': 23, 's8': 24, 's9': 25, 's10': 26, 's11': 27, 't3': 28, 't4': 29, 't5': 30, 't6': 31, 'mhartid': 32, 'mstatus': 33, 'mip': 34, 'mie': 35, 'mideleg': 36, 'medeleg': 37, 'mtvec': 38, 'stvec': 39, 'mepc': 40, 'sepc': 41, 'mcause': 42, 'scause': 43, 'mtval': 44, 'stval': 45} # initial state @@ -144,14 +151,23 @@ numInstrs = 0 #instructions = [] MemAdr = 0 lines = [] -interrupts=open('interrupts.txt','w') +interrupts=open(interruptFname,'w') interrupts.close() for line in fileinput.input('-'): if line.startswith('riscv_cpu_do_interrupt'): - with open('interrupts.txt','a') as interrupts: - interrupts.write(str(numInstrs)+': '+line.strip('riscv_cpu_do_interrupt')) - break + with open(interruptFname,'a') as interrupts: + # Write line + # Example line: hart:0, async:0, cause:0000000000000002, epc:0x0000000080008548, tval:0x0000000000000000, desc=illegal_instruction + interrupts.write(line) + # Write instruction count + interrupts.write(str(numInstrs)+'\n') + # Convert line to rows of info for easier Verilog parsing + vals=line.strip('riscv_cpu_do_interrupt: ').strip('\n').split(',') + vals=[val.split(':')[-1].strip(' ').strip('desc=') for val in vals] + for val in vals: + interrupts.write(val+'\n') + continue lines.insert(lineNum, line) if InstrStartDelim in line: lineNum = 0 @@ -204,8 +220,8 @@ for line in fileinput.input('-'): #instructions.append(MoveInstrToRegWriteLst) PrintInstr(MoveInstrToRegWriteLst, sys.stdout) numInstrs +=1 - if (numInstrs % 1e4 == 0): - sys.stderr.write('Trace parser reached '+str(numInstrs/1.0e6)+' million instrs.\n') + if (numInstrs % 1e5 == 0): + sys.stderr.write('GDB trace parser reached '+str(numInstrs/1.0e6)+' million instrs.\n') sys.stderr.flush() lineNum += 1 diff --git a/linux/testvector-generation/parseQemuToGDB.py b/linux/testvector-generation/parseQemuToGDB.py index 932761db7..fa2646abe 100755 --- a/linux/testvector-generation/parseQemuToGDB.py +++ b/linux/testvector-generation/parseQemuToGDB.py @@ -115,7 +115,6 @@ for l in fileinput.input(): if l.startswith('riscv_cpu_do_interrupt'): sys.stderr.write(l) interrupt_line = l.strip('\n') - continue elif l.startswith('qemu-system-riscv64: QEMU: Terminated via GDBstub'): break elif l.startswith('IN:'): From 440cac9f7737438d72905c12dd0e3b7583058a42 Mon Sep 17 00:00:00 2001 From: bbracker Date: Wed, 9 Feb 2022 02:56:39 +0000 Subject: [PATCH 02/14] minor interrupt syntax fix --- linux/testvector-generation/parseGDBtoTrace.py | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/linux/testvector-generation/parseGDBtoTrace.py b/linux/testvector-generation/parseGDBtoTrace.py index 69bdfceb9..db444f696 100755 --- a/linux/testvector-generation/parseGDBtoTrace.py +++ b/linux/testvector-generation/parseGDBtoTrace.py @@ -164,7 +164,8 @@ for line in fileinput.input('-'): interrupts.write(str(numInstrs)+'\n') # Convert line to rows of info for easier Verilog parsing vals=line.strip('riscv_cpu_do_interrupt: ').strip('\n').split(',') - vals=[val.split(':')[-1].strip(' ').strip('desc=') for val in vals] + vals=[val.split(':')[-1].strip(' ') for val in vals] + vals=[val.split('=')[-1].strip(' ') for val in vals] for val in vals: interrupts.write(val+'\n') continue From cb86e1cda93dc40cf23c53cb955606f3fd7f5f6a Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 9 Feb 2022 19:47:50 +0000 Subject: [PATCH 03/14] Merged synthesiss scripts into main --- synthDC/.synopsys_dc.setup | 11 ++- synthDC/scripts/synth.tcl | 176 ++++++++++++++++++++++++++++++++----- 2 files changed, 162 insertions(+), 25 deletions(-) diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index f5d7f0ece..f3c9458b8 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -3,8 +3,12 @@ set CURRENT_DIR [exec pwd] set search_path [list "./" ] -set s8lib ../addins/sky130_osu_sc_t12/12T_ms/lib -lappend search_path $s8lib +#set timing_lib "$::env(RISCV)/cad/lib" +set timing_lib "/opt/riscv/cad/lib" +lappend search_path $timing_lib +#set s8lib ../addins/sky130_osu_sc_t12/12T_ms/lib +#lappend search_path $s8lib + # Synthetic libraries set synthetic_library [list dw_foundation.sldb] @@ -12,7 +16,8 @@ set synthetic_library [list dw_foundation.sldb] # Set OKSTATE standard cell libraries set target_library [list] -lappend target_library sky130_osu_sc_12T_ms_TT_1P8_25C.ccs.db +lappend target_library scc9gena_tt_1.2v_25C.db +#lappend target_library sky130_osu_sc_12T_ms_TT_1P8_25C.ccs.db # Set Link Library set link_library "$target_library $synthetic_library" diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 23a305937..81bf1cea5 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -1,13 +1,14 @@ # -# Main Synopsys Flow -# james.stine@okstate.edu 26 Jan 2022 +# OKSTATE Main Synopsys Flow +# Updated Sep 27, 2015 jes # # Config -set hdl_src "../pipelined/src" +set hdl_src "../../../pipelined/src" +set cfg "${hdl_src}/../config/rv32e/wally-config.vh" -eval file copy -force ${hdl_src}/../config/rv32e/wally-config.vh {hdl/} -eval file copy -force ${hdl_src}/../config/rv32e/wally-config.vh {reports/} +eval file copy -force ${cfg} {hdl/} +eval file copy -force ${cfg} {reports/} eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/} eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/} @@ -16,7 +17,7 @@ eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/} set my_verilog_files [glob hdl/*] # Set toplevel -set my_toplevel wallypipelinedcore +set my_toplevel $::env(DESIGN) # Set number of significant digits set report_default_significant_digits 6 @@ -25,7 +26,6 @@ set report_default_significant_digits 6 set verilogout_show_unconnected_pins "true" set vhdlout_show_unconnected_pins "true" -# # Due to parameterized Verilog must use analyze/elaborate and not # read_verilog/vhdl (change to pull in Verilog and/or VHDL) # @@ -45,11 +45,14 @@ link # Reset all constraints reset_design +# Set reset false path +set_false_path -from [get_ports reset_ext] + # Set Frequency in [MHz] or [ps] set my_clock_pin clk -set my_clk_freq_MHz 500 -set my_period [expr 1000 / $my_clk_freq_MHz] -set my_uncertainty [expr .1 * $my_period] +set my_uncertainty 0.0 +set my_clk_freq_MHz $::env(FREQ) +set my_period [expr 1000.0 / $my_clk_freq_MHz] # Create clock object set find_clock [ find port [list $my_clock_pin] ] @@ -65,25 +68,25 @@ if { $find_clock != [list] } { } # Partitioning - flatten or hierarchically synthesize -#ungroup -flatten -simple_names { dp* } -#ungroup -flatten -simple_names { c* } #ungroup -all -flatten -simple_names # Set input pins except clock set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]] # Specifies delays be propagated through the clock network -set_propagated_clock [get_clocks $my_clk] +#set_propagated_clock [get_clocks $my_clk] # Setting constraints on input ports -set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk +set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk +#set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk # Set input/output delay set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk set_output_delay 0.0 -max -clock $my_clk [all_outputs] # Setting load constraint on output ports -set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs] +set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs] +#set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs] # Set the wire load model set_wire_load_mode "top" @@ -95,7 +98,7 @@ set_wire_load_mode "top" set_max_fanout 6 $all_in_ex_clk # Fix hold time violations -set_fix_hold [all_clocks] +#set_fix_hold [all_clocks] # Deal with constants and buffers to isolate ports set_fix_multiple_port_nets -all -buffer_constants @@ -109,8 +112,7 @@ set_fix_multiple_port_nets -all -buffer_constants set filename [format "%s%s%s" "unmapped/" $my_toplevel ".ddc"] write_file -format ddc -hierarchy -o $filename -# Compile statements - either compile or compile_ultra -# compile -scan -incr -map_effort low +# Compile statements compile_ultra -no_seq_output_inversion -no_boundary_optimization # Eliminate need for assign statements (yuck!) @@ -161,6 +163,137 @@ redirect $filename { report_clock } set filename [format "%s%s%s" "reports/" $my_toplevel "_timing.rep"] redirect $filename { report_timing -capacitance -transition_time -nets -nworst 1 } +set filename [format "%s%s%s" "reports/" $my_toplevel "_per_module_timing.rep"] +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through ifu ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through ieu ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through lsu ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {lsu/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through ebu (ahblite) ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ebu/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through mdu ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through hzu ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {hzu/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through priv ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through fpu ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/*} -nworst 1 } + +set filename [format "%s%s%s" "reports/" $my_toplevel "_mdu_timing.rep"] +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through entire mdu ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through multiply unit ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through redundant multiplier ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/bigmul/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through ProdM (mul output) ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.ProdM} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through PP0E (mul partial product) ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.mul/PP0E} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through divide unit ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through QuotM (div output) ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.QuotM} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through RemM (div output) ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.RemM} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through div/WNextE ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/WNextE} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through div/XQNextE ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/XQNextE} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through div/DAbsBE ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/DAbsBE} -nworst 1 } + +# set filename [format "%s%s%s" "reports/" $my_toplevel "_fpu_timing.rep"] +# redirect $filename { echo "\n\n\n//////////////// Critical paths through fma ////////////////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/*} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//////////////// Critical paths through fpdiv ////////////////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fdivsqrt/*} -nworst 1 } +# redirect -append $filename { echo "\n\n\n//////////////// Critical paths through faddcvt ////////////////\n\n\n" } +# redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.faddcvt/*} -nworst 1 } + +set filename [format "%s%s%s" "reports/" $my_toplevel "_ifu_timing.rep"] +redirect -append $filename { echo "\n\n\n//////////////// Critical path through PCF ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCF} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through PCNextF ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCNextF} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through FinalInstrRawF ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/FinalInstrRawF} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through InstrD ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/decomp/InstrD} -nworst 1 } + +set filename [format "%s%s%s" "reports/" $my_toplevel "_stall_flush_timing.rep"] +redirect -append $filename { echo "\n\n\n//////////////// Critical path through StallD ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallD} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through StallE ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallE} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through StallM ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallM} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through StallW ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallW} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through FlushD ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushD} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through FlushE ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushE} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through FlushM ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushM} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through FlushW ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushW} -nworst 1 } + +set filename [format "%s%s%s" "reports/" $my_toplevel "_ieu_timing.rep"] +redirect -append $filename { echo "\n\n\n//////////////// Critical path through datapath/RD1D ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/RD1D} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through datapath/RD2D ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/RD2D} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through datapath/PreSrcAE ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/PreSrcAE} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through datapath/SrcAE ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/SrcAE} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through datapath/ALUResultE ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ALUResultE} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through datapath/WriteDataE ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/WriteDataE} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through dataphath/ResultM ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ResultM} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through datapath/WriteDataW ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/WriteDataW} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical path through datapath/ReadDataM ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ReadDataM} -nworst 1 } + +set filename [format "%s%s%s" "reports/" $my_toplevel "_fpu_timing.rep"] +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through fma ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through fpdiv ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fdivsqrt/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through faddcvt ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.faddcvt/*} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through FMAResM ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FMAResM} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through FDivResM ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FDivResM} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through FResE ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.FResE} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through fma/SumE ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/SumE} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through fma/ProdExpE ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/ProdExpE} -nworst 1 } + +set filename [format "%s%s%s" "reports/" $my_toplevel "_mmu_timing.rep"] +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through immu/physicaladdress ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/immu/PhysicalAddress} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through dmmu/physicaladdress ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {lsu/dmmu/PhysicalAddress} -nworst 1 } + +set filename [format "%s%s%s" "reports/" $my_toplevel "_priv_timing.rep"] +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through priv/TrapM ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/TrapM} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through priv/CSRReadValM ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/csr/CSRReadValM} -nworst 1 } +redirect -append $filename { echo "\n\n\n//////////////// Critical paths through priv/CSRReadValW ////////////////\n\n\n" } +redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/CSRReadValW} -nworst 1 } + + set filename [format "%s%s%s" "reports/" $my_toplevel "_min_timing.rep"] redirect $filename { report_timing -delay min } @@ -171,7 +304,7 @@ set filename [format "%s%s%s" "reports/" $my_toplevel "_cell.rep"] redirect $filename { report_cell [get_cells -hier *] } set filename [format "%s%s%s" "reports/" $my_toplevel "_power.rep"] -redirect $filename { report_power } +redirect $filename { report_power -hierarchy -levels 1 } set filename [format "%s%s%s" "reports/" $my_toplevel "_constraint.rep"] redirect $filename { report_constraint } @@ -179,6 +312,5 @@ redirect $filename { report_constraint } set filename [format "%s%s%s" "reports/" $my_toplevel "_hier.rep"] redirect $filename { report_hierarchy } -# Quit -quit - +#Quit +#quit # *** commented out so we can stay in the synopsis terminal after synthesis is done. From 04cf60a6bf12b9be148c818a81d6af01766b6eae Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 9 Feb 2022 15:06:42 -0600 Subject: [PATCH 04/14] Updated synthesis and Makefile to output into binned directories. --- synthDC/.synopsys_dc.setup | 11 +++--- synthDC/Makefile | 18 +++++++--- synthDC/scripts/synth.tcl | 69 ++++++++++++++++++++------------------ 3 files changed, 55 insertions(+), 43 deletions(-) diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index f3c9458b8..67c19d941 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -3,11 +3,10 @@ set CURRENT_DIR [exec pwd] set search_path [list "./" ] -#set timing_lib "$::env(RISCV)/cad/lib" -set timing_lib "/opt/riscv/cad/lib" +set timing_lib $::env(RISCV)/cad/lib lappend search_path $timing_lib -#set s8lib ../addins/sky130_osu_sc_t12/12T_ms/lib -#lappend search_path $s8lib +set s8lib $timing_lib/sky130_osu_sc_t12/12T_ms/lib +lappend search_path $s8lib # Synthetic libraries @@ -16,8 +15,8 @@ set synthetic_library [list dw_foundation.sldb] # Set OKSTATE standard cell libraries set target_library [list] -lappend target_library scc9gena_tt_1.2v_25C.db -#lappend target_library sky130_osu_sc_12T_ms_TT_1P8_25C.ccs.db +#lappend target_library scc9gena_tt_1.2v_25C.db +lappend target_library sky130_osu_sc_12T_ms_TT_1P8_25C.ccs.db # Set Link Library set link_library "$target_library $synthetic_library" diff --git a/synthDC/Makefile b/synthDC/Makefile index 35caad119..3af767878 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -3,7 +3,15 @@ # NAME := synth +#instead of variant can we select 130nm, 90nm, or 28nm? VARIANT := 18T_ms +# defaults +export DESIGN ?= wallypipelinedcore +export FREQ ?= 500 + +time := $(shell date +%F-%H-%M) +hash := $(shell git rev-parse --short HEAD) +export OUTPUTDIR := runs/$(DESIGN)_$(FREQ)_MHz_$(time)_$(hash) default: @echo "Basic synthesis procedure for OSU/HMC/UNLV:" @@ -11,11 +19,13 @@ default: @echo synth: - @sed -i 's/18T_ms/${VARIANT}/g' scripts/synth.tcl - @sed -i 's/18T_ms/${VARIANT}/g' .synopsys_dc.setup +# @sed -i 's/18T_ms/${VARIANT}/g' scripts/synth.tcl +# @sed -i 's/18T_ms/${VARIANT}/g' .synopsys_dc.setup @echo "DC Synthesis" - @mkdir -p reports - @mkdir -p mapped + @mkdir -p $(OUTPUTDIR) + @mkdir -p $(OUTPUTDIR)/reports + @mkdir -p $(OUTPUTDIR)/mapped + @mkdir -p $(OUTPUTDIR)/unmapped dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(NAME).out # @cp mapped/*.sdc ../../outputs/ # @cp mapped/*.vh ../../outputs/ diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 81bf1cea5..dc2763ac7 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -2,17 +2,20 @@ # OKSTATE Main Synopsys Flow # Updated Sep 27, 2015 jes # +# get outputDir from environment (Makefile) +set outputDir $::env(OUTPUTDIR) # Config -set hdl_src "../../../pipelined/src" +set hdl_src "../pipelined/src" set cfg "${hdl_src}/../config/rv32e/wally-config.vh" eval file copy -force ${cfg} {hdl/} -eval file copy -force ${cfg} {reports/} +eval file copy -force ${cfg} $outputDir eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/} eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/} + # Verilog files set my_verilog_files [glob hdl/*] @@ -46,7 +49,7 @@ link reset_design # Set reset false path -set_false_path -from [get_ports reset_ext] +set_false_path -from [get_ports reset] # Set Frequency in [MHz] or [ps] set my_clock_pin clk @@ -77,16 +80,16 @@ set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]] #set_propagated_clock [get_clocks $my_clk] # Setting constraints on input ports -set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk -#set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk +#set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk +set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk # Set input/output delay set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk set_output_delay 0.0 -max -clock $my_clk [all_outputs] # Setting load constraint on output ports -set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs] -#set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs] +#set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs] +set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs] # Set the wire load model set_wire_load_mode "top" @@ -109,7 +112,7 @@ set_fix_multiple_port_nets -all -buffer_constants #group_path -name COMBO -from [all_inputs] -to [all_outputs] # Save Unmapped Design -set filename [format "%s%s%s" "unmapped/" $my_toplevel ".ddc"] +set filename [format "%s%s%s%s" $outputDir "/unmapped/" $my_toplevel ".ddc"] write_file -format ddc -hierarchy -o $filename # Compile statements @@ -130,40 +133,40 @@ set write_cst 1 ;# generate report of constraints set write_hier 1 ;# generate hierarchy report # Report Constraint Violators -set filename [format "%s%s%s" "reports/" $my_toplevel "_constraint_all_violators.rpt"] +set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_constraint_all_violators.rpt"] redirect $filename {report_constraint -all_violators} # Check design -redirect reports/check_design.rpt { check_design } +redirect $outputDir/reports/check_design.rpt { check_design } # Report Final Netlist (Hierarchical) -set filename [format "%s%s%s" "mapped/" $my_toplevel ".vh"] +set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".vh"] write_file -f verilog -hierarchy -output $filename -set filename [format "%s%s%s" "mapped/" $my_toplevel ".sdc"] +set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdc"] write_sdc $filename -set filename [format "%s%s%s" "mapped/" $my_toplevel ".ddc"] +set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".ddc"] write_file -format ddc -hierarchy -o $filename -set filename [format "%s%s%s" "mapped/" $my_toplevel ".sdf"] +set filename [format "%s%s%s%s" $outputDir "/mapped/" $my_toplevel ".sdf"] write_sdf $filename # QoR -set filename [format "%s%s%s" "reports/" $my_toplevel "_qor.rep"] +set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_qor.rep"] redirect $filename { report_qor } # Report Timing -set filename [format "%s%s%s" "reports/" $my_toplevel "_reportpath.rep"] +set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_reportpath.rep"] redirect $filename { report_path_group } -set filename [format "%s%s%s" "reports/" $my_toplevel "_report_clock.rep"] +set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_report_clock.rep"] redirect $filename { report_clock } -set filename [format "%s%s%s" "reports/" $my_toplevel "_timing.rep"] +set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_timing.rep"] redirect $filename { report_timing -capacitance -transition_time -nets -nworst 1 } -set filename [format "%s%s%s" "reports/" $my_toplevel "_per_module_timing.rep"] +set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_per_module_timing.rep"] redirect -append $filename { echo "\n\n\n//////////////// Critical paths through ifu ////////////////\n\n\n" } redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/*} -nworst 1 } redirect -append $filename { echo "\n\n\n//////////////// Critical paths through ieu ////////////////\n\n\n" } @@ -181,7 +184,7 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets - redirect -append $filename { echo "\n\n\n//////////////// Critical paths through fpu ////////////////\n\n\n" } redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/*} -nworst 1 } -set filename [format "%s%s%s" "reports/" $my_toplevel "_mdu_timing.rep"] +set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_mdu_timing.rep"] redirect -append $filename { echo "\n\n\n//////////////// Critical paths through entire mdu ////////////////\n\n\n" } redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/*} -nworst 1 } redirect -append $filename { echo "\n\n\n//////////////// Critical paths through multiply unit ////////////////\n\n\n" } @@ -205,7 +208,7 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets - redirect -append $filename { echo "\n\n\n//////////////// Critical path through div/DAbsBE ////////////////\n\n\n" } redirect -append $filename { report_timing -capacitance -transition_time -nets -through {mdu/genblk1.div/DAbsBE} -nworst 1 } -# set filename [format "%s%s%s" "reports/" $my_toplevel "_fpu_timing.rep"] +# set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_fpu_timing.rep"] # redirect $filename { echo "\n\n\n//////////////// Critical paths through fma ////////////////\n\n\n" } # redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/*} -nworst 1 } # redirect -append $filename { echo "\n\n\n//////////////// Critical paths through fpdiv ////////////////\n\n\n" } @@ -213,7 +216,7 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets - # redirect -append $filename { echo "\n\n\n//////////////// Critical paths through faddcvt ////////////////\n\n\n" } # redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.faddcvt/*} -nworst 1 } -set filename [format "%s%s%s" "reports/" $my_toplevel "_ifu_timing.rep"] +set filename [format "%s%s%s%s" $outputDir "reports/" $my_toplevel "_ifu_timing.rep"] redirect -append $filename { echo "\n\n\n//////////////// Critical path through PCF ////////////////\n\n\n" } redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCF} -nworst 1 } redirect -append $filename { echo "\n\n\n//////////////// Critical path through PCNextF ////////////////\n\n\n" } @@ -223,7 +226,7 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets - redirect -append $filename { echo "\n\n\n//////////////// Critical path through InstrD ////////////////\n\n\n" } redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/decomp/InstrD} -nworst 1 } -set filename [format "%s%s%s" "reports/" $my_toplevel "_stall_flush_timing.rep"] +set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_stall_flush_timing.rep"] redirect -append $filename { echo "\n\n\n//////////////// Critical path through StallD ////////////////\n\n\n" } redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/StallD} -nworst 1 } redirect -append $filename { echo "\n\n\n//////////////// Critical path through StallE ////////////////\n\n\n" } @@ -241,7 +244,7 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets - redirect -append $filename { echo "\n\n\n//////////////// Critical path through FlushW ////////////////\n\n\n" } redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/FlushW} -nworst 1 } -set filename [format "%s%s%s" "reports/" $my_toplevel "_ieu_timing.rep"] +set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_ieu_timing.rep"] redirect -append $filename { echo "\n\n\n//////////////// Critical path through datapath/RD1D ////////////////\n\n\n" } redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/RD1D} -nworst 1 } redirect -append $filename { echo "\n\n\n//////////////// Critical path through datapath/RD2D ////////////////\n\n\n" } @@ -261,7 +264,7 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets - redirect -append $filename { echo "\n\n\n//////////////// Critical path through datapath/ReadDataM ////////////////\n\n\n" } redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ieu/dp/ReadDataM} -nworst 1 } -set filename [format "%s%s%s" "reports/" $my_toplevel "_fpu_timing.rep"] +set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_fpu_timing.rep"] redirect -append $filename { echo "\n\n\n//////////////// Critical paths through fma ////////////////\n\n\n" } redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/*} -nworst 1 } redirect -append $filename { echo "\n\n\n//////////////// Critical paths through fpdiv ////////////////\n\n\n" } @@ -279,13 +282,13 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets - redirect -append $filename { echo "\n\n\n//////////////// Critical paths through fma/ProdExpE ////////////////\n\n\n" } redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.fma/ProdExpE} -nworst 1 } -set filename [format "%s%s%s" "reports/" $my_toplevel "_mmu_timing.rep"] +set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_mmu_timing.rep"] redirect -append $filename { echo "\n\n\n//////////////// Critical paths through immu/physicaladdress ////////////////\n\n\n" } redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/immu/PhysicalAddress} -nworst 1 } redirect -append $filename { echo "\n\n\n//////////////// Critical paths through dmmu/physicaladdress ////////////////\n\n\n" } redirect -append $filename { report_timing -capacitance -transition_time -nets -through {lsu/dmmu/PhysicalAddress} -nworst 1 } -set filename [format "%s%s%s" "reports/" $my_toplevel "_priv_timing.rep"] +set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_priv_timing.rep"] redirect -append $filename { echo "\n\n\n//////////////// Critical paths through priv/TrapM ////////////////\n\n\n" } redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/TrapM} -nworst 1 } redirect -append $filename { echo "\n\n\n//////////////// Critical paths through priv/CSRReadValM ////////////////\n\n\n" } @@ -294,22 +297,22 @@ redirect -append $filename { echo "\n\n\n//////////////// Critical paths through redirect -append $filename { report_timing -capacitance -transition_time -nets -through {priv/CSRReadValW} -nworst 1 } -set filename [format "%s%s%s" "reports/" $my_toplevel "_min_timing.rep"] +set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_min_timing.rep"] redirect $filename { report_timing -delay min } -set filename [format "%s%s%s" "reports/" $my_toplevel "_area.rep"] +set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_area.rep"] redirect $filename { report_area -hierarchy -nosplit -physical -designware} -set filename [format "%s%s%s" "reports/" $my_toplevel "_cell.rep"] +set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_cell.rep"] redirect $filename { report_cell [get_cells -hier *] } -set filename [format "%s%s%s" "reports/" $my_toplevel "_power.rep"] +set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_power.rep"] redirect $filename { report_power -hierarchy -levels 1 } -set filename [format "%s%s%s" "reports/" $my_toplevel "_constraint.rep"] +set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_constraint.rep"] redirect $filename { report_constraint } -set filename [format "%s%s%s" "reports/" $my_toplevel "_hier.rep"] +set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_hier.rep"] redirect $filename { report_hierarchy } #Quit From ed4e912413b5467990b149af0a3fbf415a4ec4ba Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 9 Feb 2022 15:18:49 -0600 Subject: [PATCH 05/14] Cleaned up synthesis flow. --- .gitignore | 7 ++++++- synthDC/Makefile | 11 ++++++----- synthDC/scripts/synth.tcl | 4 ++-- 3 files changed, 14 insertions(+), 8 deletions(-) diff --git a/.gitignore b/.gitignore index eae7c79e8..09761c023 100644 --- a/.gitignore +++ b/.gitignore @@ -52,7 +52,12 @@ examples/asm/sumtest/sumtest examples/asm/example/example examples/C/sum/sum examples/C/fir/fir -synthDC/hdl/*.sv linux/devicetree/debug/* !linux/devicetree/debug/dumpdts.sh *.dtb +synthDC/WORK +synthDC/alib-52 +synthDC/*.log +synthDC/*.svf +synthDC/runs/ +synthDC/hdl diff --git a/synthDC/Makefile b/synthDC/Makefile index 3af767878..33670429b 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -3,15 +3,16 @@ # NAME := synth -#instead of variant can we select 130nm, 90nm, or 28nm? +# *** instead of variant can we select 130nm, 90nm, or 28nm? VARIANT := 18T_ms # defaults export DESIGN ?= wallypipelinedcore export FREQ ?= 500 +export CONFIG ?= rv32e time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD) -export OUTPUTDIR := runs/$(DESIGN)_$(FREQ)_MHz_$(time)_$(hash) +export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(FREQ)_MHz_$(time)_$(hash) default: @echo "Basic synthesis procedure for OSU/HMC/UNLV:" @@ -22,19 +23,19 @@ synth: # @sed -i 's/18T_ms/${VARIANT}/g' scripts/synth.tcl # @sed -i 's/18T_ms/${VARIANT}/g' .synopsys_dc.setup @echo "DC Synthesis" + @mkdir -p hdl/ @mkdir -p $(OUTPUTDIR) @mkdir -p $(OUTPUTDIR)/reports @mkdir -p $(OUTPUTDIR)/mapped @mkdir -p $(OUTPUTDIR)/unmapped - dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(NAME).out + dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out # @cp mapped/*.sdc ../../outputs/ # @cp mapped/*.vh ../../outputs/ # @sed -i 's/${VARIANT}/18T_ms/g' scripts/synth.tcl # @sed -i 's/${VARIANT}/18T_ms/g' .synopsys_dc.setup clean: - rm -rf alib-52 WORK mapped unmapped reports analyzed $(NAME).out - mkdir mapped unmapped reports + rm -rf alib-52 WORK analyzed $(NAME).out rm -f hdl/* rm -f default.svf rm -f command.log diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index dc2763ac7..18d12494f 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -4,10 +4,10 @@ # # get outputDir from environment (Makefile) set outputDir $::env(OUTPUTDIR) - +set cfgName $::env(CONFIG) # Config set hdl_src "../pipelined/src" -set cfg "${hdl_src}/../config/rv32e/wally-config.vh" +set cfg "${hdl_src}/../config/${cfgName}/wally-config.vh" eval file copy -force ${cfg} {hdl/} eval file copy -force ${cfg} $outputDir From 216e050ecfdea46a2f1c1c539d888314615750ce Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Wed, 9 Feb 2022 16:04:20 -0600 Subject: [PATCH 06/14] Add power analysis to synth.tcl --- synthDC/scripts/synth.tcl | 29 +++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 18d12494f..4dec4baf1 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -1,7 +1,11 @@ # -# OKSTATE Main Synopsys Flow -# Updated Sep 27, 2015 jes +# Synthesis Synopsys Flow +# james.stine@okstate.edu 27 Sep 2015 # + +# Enables name mapping +saif_map -start + # get outputDir from environment (Makefile) set outputDir $::env(OUTPUTDIR) set cfgName $::env(CONFIG) @@ -15,7 +19,6 @@ eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/} eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/} - # Verilog files set my_verilog_files [glob hdl/*] @@ -48,6 +51,12 @@ link # Reset all constraints reset_design +# SAIF power prediction (optional) +# set_power_prediction + +# Power Dissipation Analysis +# read_saif -input vcd/mult.saif -instance_name stimulus/dut -auto_map_names -verbose + # Set reset false path set_false_path -from [get_ports reset] @@ -71,16 +80,16 @@ if { $find_clock != [list] } { } # Partitioning - flatten or hierarchically synthesize -#ungroup -all -flatten -simple_names +# ungroup -all -flatten -simple_names # Set input pins except clock set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]] # Specifies delays be propagated through the clock network -#set_propagated_clock [get_clocks $my_clk] +# set_propagated_clock [get_clocks $my_clk] # Setting constraints on input ports -#set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk +# set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk # Set input/output delay @@ -88,7 +97,7 @@ set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk set_output_delay 0.0 -max -clock $my_clk [all_outputs] # Setting load constraint on output ports -#set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs] +# set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs] set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs] # Set the wire load model @@ -107,9 +116,9 @@ set_max_fanout 6 $all_in_ex_clk set_fix_multiple_port_nets -all -buffer_constants # setting up the group paths to find out the required timings -#group_path -name OUTPUTS -to [all_outputs] -#group_path -name INPUTS -from [all_inputs] -#group_path -name COMBO -from [all_inputs] -to [all_outputs] +# group_path -name OUTPUTS -to [all_outputs] +# group_path -name INPUTS -from [all_inputs] +# group_path -name COMBO -from [all_inputs] -to [all_outputs] # Save Unmapped Design set filename [format "%s%s%s%s" $outputDir "/unmapped/" $my_toplevel ".ddc"] From bb092a9dffa0be87dbc9620050d5f681d40d3d08 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 9 Feb 2022 16:06:27 -0600 Subject: [PATCH 07/14] Added support for 90nm. --- synthDC/.synopsys_dc.setup | 17 ++++++++++++++--- synthDC/Makefile | 3 ++- synthDC/scripts/synth.tcl | 17 +++++++++++++---- 3 files changed, 29 insertions(+), 8 deletions(-) diff --git a/synthDC/.synopsys_dc.setup b/synthDC/.synopsys_dc.setup index 67c19d941..efc21508e 100755 --- a/synthDC/.synopsys_dc.setup +++ b/synthDC/.synopsys_dc.setup @@ -3,11 +3,18 @@ set CURRENT_DIR [exec pwd] set search_path [list "./" ] +set tech $::env(TECH) + set timing_lib $::env(RISCV)/cad/lib lappend search_path $timing_lib -set s8lib $timing_lib/sky130_osu_sc_t12/12T_ms/lib -lappend search_path $s8lib +if {$tech == 130} { + set s8lib $timing_lib/sky130_osu_sc_t12/12T_ms/lib + lappend search_path $s8lib +} elseif {$tech == 90} { + set s9lib $timing_lib/sky90/tech_files + lappend search_path $s9lib +} # Synthetic libraries set synthetic_library [list dw_foundation.sldb] @@ -16,7 +23,11 @@ set synthetic_library [list dw_foundation.sldb] set target_library [list] #lappend target_library scc9gena_tt_1.2v_25C.db -lappend target_library sky130_osu_sc_12T_ms_TT_1P8_25C.ccs.db +if {$tech == 130} { + lappend target_library sky130_osu_sc_12T_ms_TT_1P8_25C.ccs.db +} elseif {$tech == 90} { + lappend target_library scc9gena_tt_1.2v_25C.db +} # Set Link Library set link_library "$target_library $synthetic_library" diff --git a/synthDC/Makefile b/synthDC/Makefile index 33670429b..3979f48df 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -9,10 +9,11 @@ VARIANT := 18T_ms export DESIGN ?= wallypipelinedcore export FREQ ?= 500 export CONFIG ?= rv32e +export TECH ?= 130 time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD) -export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(FREQ)_MHz_$(time)_$(hash) +export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(hash) default: @echo "Basic synthesis procedure for OSU/HMC/UNLV:" diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index 18d12494f..0a41aaf5b 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -81,7 +81,11 @@ set all_in_ex_clk [remove_from_collection [all_inputs] [get_ports $my_clk]] # Setting constraints on input ports #set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk -set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk +if {$tech == "130"} { + set_driving_cell -lib_cell sky130_osu_sc_12T_ms__dff_1 -pin Q $all_in_ex_clk +} elseif {$tech == "90"} { + set_driving_cell -lib_cell scc9gena_dfxbp_1 -pin Q $all_in_ex_clk +} # Set input/output delay set_input_delay 0.0 -max -clock $my_clk $all_in_ex_clk @@ -89,7 +93,12 @@ set_output_delay 0.0 -max -clock $my_clk [all_outputs] # Setting load constraint on output ports #set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs] -set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs] +if {$tech == "130"} { + set_load [expr [load_of sky130_osu_sc_12T_ms_TT_1P8_25C.ccs/sky130_osu_sc_12T_ms__dff_1/D] * 1] [all_outputs] +} elseif {$tech == "90"} { + set_load [expr [load_of scc9gena_tt_1.2v_25C/scc9gena_dfxbp_1/D] * 1] [all_outputs] +} + # Set the wire load model set_wire_load_mode "top" @@ -216,7 +225,7 @@ redirect -append $filename { report_timing -capacitance -transition_time -nets - # redirect -append $filename { echo "\n\n\n//////////////// Critical paths through faddcvt ////////////////\n\n\n" } # redirect -append $filename { report_timing -capacitance -transition_time -nets -through {fpu/fpu.faddcvt/*} -nworst 1 } -set filename [format "%s%s%s%s" $outputDir "reports/" $my_toplevel "_ifu_timing.rep"] +set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_ifu_timing.rep"] redirect -append $filename { echo "\n\n\n//////////////// Critical path through PCF ////////////////\n\n\n" } redirect -append $filename { report_timing -capacitance -transition_time -nets -through {ifu/PCF} -nworst 1 } redirect -append $filename { echo "\n\n\n//////////////// Critical path through PCNextF ////////////////\n\n\n" } @@ -316,4 +325,4 @@ set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_hier.rep" redirect $filename { report_hierarchy } #Quit -#quit # *** commented out so we can stay in the synopsis terminal after synthesis is done. +quit From 13e826561f4421e30505d5290ec05240d9262c70 Mon Sep 17 00:00:00 2001 From: "James E. Stine" Date: Wed, 9 Feb 2022 16:20:05 -0600 Subject: [PATCH 08/14] Update on README.md for synthDC --- synthDC/README.md | 37 ++++++++----------------------------- 1 file changed, 8 insertions(+), 29 deletions(-) diff --git a/synthDC/README.md b/synthDC/README.md index 12db0a524..201eeadc8 100644 --- a/synthDC/README.md +++ b/synthDC/README.md @@ -1,34 +1,13 @@ +Synthesis for RISC-V Microprocessor System-on-Chip Design + This subdirectory contains synthesis scripts for use with Synopsys -Design Compiler (DC). The scripts are separated into two distinct -sections: user and technology setups. The technology setup is found -in .synopsys_dc.setup file. Key items within this technology setup -are the location of the PDK and standard cell libraries. +(snps) Design Compiler (DC). Synthesis commands are found in +scripts/synth.tcl. -We are using the Skywater Technology 130nm process for the synthesis. -The Oklahoma State University standard-cell libraries for this process -are located via the target_library keyword. There are currently three -versions of the standard-cell libraries available (see -http://stineje.github.io) for dowload locations. Currently, the TT 18 -track OSU standard-cell library is utilized. +Example Usage +make synth DESIGN=wallypipelinedcore FREQ=300 -There are other useful elements within the technology setup file, as -well. These include user information as well as search path -information. Good tool flows usually rely on finding the right files -correctly and having a search path set correctly is importantly. +Libraries in .synopsys_dc.setup file +set s8lib $timing_lib/sky130_osu_sc_t12/12T_ms/lib -The user setup is found in two main areas. The scripts/ and hdl/ -directories. The scripts directory contains a basic DC synthesis Tcl -script that is involved when synthesis is run. Please modify this -synth.tcl file to add information about PPA and information about your -design (e.g., top-level name, SV files). The SV is found within the -hdl/ subdirectory. Just put all your synthesis-friendly files in this -directory or allude to the correct location in the synthesis Tcl -script. -After synthesis completes, always check your synthesis log file that -will be called synth.log. Good tool flow starts and ends with -understanding what is happening during a specific part of the flow. -This can only be done through interpreting what the Electronic Design -Automation (EDA) tool is doing. So, always check this file for any -possible warnings or errors after completion. All output of synthesis -is found in the reports/ subdirectory. \ No newline at end of file From c7a2e6cb06900b7c6ab72f45aa71d7f43838fedd Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 9 Feb 2022 16:44:26 -0600 Subject: [PATCH 09/14] Commented quit. --- synthDC/scripts/synth.tcl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index a102d748f..dac48a5d7 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -333,4 +333,4 @@ set filename [format "%s%s%s%s" $outputDir "/reports/" $my_toplevel "_hier.rep" redirect $filename { report_hierarchy } #Quit -quit +#quit From 62d1ed65d40ffe83c5cd519e1c2a10999a538ff1 Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 10 Feb 2022 00:07:29 +0000 Subject: [PATCH 10/14] rename devicetree to wally-virt --- linux/devicetree/debug/dumpdts.sh | 6 ------ linux/devicetree/{virt-trimmed.dts => wally-virt.dts} | 0 linux/testvector-generation/genTrace.sh | 4 ++-- 3 files changed, 2 insertions(+), 8 deletions(-) delete mode 100755 linux/devicetree/debug/dumpdts.sh rename linux/devicetree/{virt-trimmed.dts => wally-virt.dts} (100%) diff --git a/linux/devicetree/debug/dumpdts.sh b/linux/devicetree/debug/dumpdts.sh deleted file mode 100755 index 70057a78f..000000000 --- a/linux/devicetree/debug/dumpdts.sh +++ /dev/null @@ -1,6 +0,0 @@ -#!/bin/bash -machine=virt - -qemu-system-riscv64 -M $machine,dumpdtb=$machine.dtb -bios $RISCV/buildroot/output/images/fw_jump.elf - -dtc -I dtb -O dts $machine.dtb > $machine.dts diff --git a/linux/devicetree/virt-trimmed.dts b/linux/devicetree/wally-virt.dts similarity index 100% rename from linux/devicetree/virt-trimmed.dts rename to linux/devicetree/wally-virt.dts diff --git a/linux/testvector-generation/genTrace.sh b/linux/testvector-generation/genTrace.sh index e085251ba..44ce1b822 100755 --- a/linux/testvector-generation/genTrace.sh +++ b/linux/testvector-generation/genTrace.sh @@ -25,11 +25,11 @@ then sudo chmod a+rw $interruptsFile # Compile Devicetree from Source - dtc -I dts -O dtb ../devicetree/virt-trimmed.dts > ../devicetree/virt-trimmed.dtb + dtc -I dts -O dtb ../devicetree/wally-virt.dts > ../devicetree/wally-virt.dtb # QEMU Simulation (qemu-system-riscv64 \ - -M virt -dtb ../devicetree/virt-trimmed.dtb \ + -M virt -dtb ../devicetree/wally-virt.dtb \ -nographic -serial /dev/null \ -bios $imageDir/fw_jump.elf -kernel $imageDir/Image -append "root=/dev/vda ro" -initrd $imageDir/rootfs.cpio \ -singlestep -rtc clock=vm -icount shift=0,align=off,sleep=on,rr=record,rrfile=$recordFile \ From f823338597e4345c6af6cf7bcb7308d918b6913a Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 10 Feb 2022 00:08:28 +0000 Subject: [PATCH 11/14] continue to rename devicetree to wally-virt --- linux/devicetree/wally-virt.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/linux/devicetree/wally-virt.dts b/linux/devicetree/wally-virt.dts index b517c3de5..f35848c59 100644 --- a/linux/devicetree/wally-virt.dts +++ b/linux/devicetree/wally-virt.dts @@ -3,8 +3,8 @@ / { #address-cells = <0x02>; #size-cells = <0x02>; - compatible = "riscv-virtio-trimmed"; - model = "riscv-virtio-trimmed,qemu"; + compatible = "wally-virt"; + model = "wally-virt,qemu"; chosen { linux,initrd-end = <0x85c43a00>; From 05dd37d3d6fc51603f966a5787cce312f3578a4a Mon Sep 17 00:00:00 2001 From: bbracker Date: Thu, 10 Feb 2022 00:10:09 +0000 Subject: [PATCH 12/14] rename dump-dts debug script --- .gitignore | 2 +- linux/devicetree/debug/dump-dts.sh | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) create mode 100755 linux/devicetree/debug/dump-dts.sh diff --git a/.gitignore b/.gitignore index 09761c023..94e8a7209 100644 --- a/.gitignore +++ b/.gitignore @@ -53,7 +53,7 @@ examples/asm/example/example examples/C/sum/sum examples/C/fir/fir linux/devicetree/debug/* -!linux/devicetree/debug/dumpdts.sh +!linux/devicetree/debug/dump-dts.sh *.dtb synthDC/WORK synthDC/alib-52 diff --git a/linux/devicetree/debug/dump-dts.sh b/linux/devicetree/debug/dump-dts.sh new file mode 100755 index 000000000..70057a78f --- /dev/null +++ b/linux/devicetree/debug/dump-dts.sh @@ -0,0 +1,6 @@ +#!/bin/bash +machine=virt + +qemu-system-riscv64 -M $machine,dumpdtb=$machine.dtb -bios $RISCV/buildroot/output/images/fw_jump.elf + +dtc -I dtb -O dts $machine.dtb > $machine.dts From 976cd5a88400a57f2031267751ba54c05445e9d0 Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 9 Feb 2022 18:42:48 -0600 Subject: [PATCH 13/14] Added saif to synthDC flow. --- synthDC/Makefile | 13 +++++-------- synthDC/scripts/synth.tcl | 16 ++++++++++------ 2 files changed, 15 insertions(+), 14 deletions(-) diff --git a/synthDC/Makefile b/synthDC/Makefile index 3979f48df..eecb952c6 100755 --- a/synthDC/Makefile +++ b/synthDC/Makefile @@ -3,8 +3,6 @@ # NAME := synth -# *** instead of variant can we select 130nm, 90nm, or 28nm? -VARIANT := 18T_ms # defaults export DESIGN ?= wallypipelinedcore export FREQ ?= 500 @@ -14,6 +12,7 @@ export TECH ?= 130 time := $(shell date +%F-%H-%M) hash := $(shell git rev-parse --short HEAD) export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(hash) +export SAIFPOWER ?= 0 default: @echo "Basic synthesis procedure for OSU/HMC/UNLV:" @@ -21,19 +20,16 @@ default: @echo synth: -# @sed -i 's/18T_ms/${VARIANT}/g' scripts/synth.tcl -# @sed -i 's/18T_ms/${VARIANT}/g' .synopsys_dc.setup @echo "DC Synthesis" @mkdir -p hdl/ @mkdir -p $(OUTPUTDIR) @mkdir -p $(OUTPUTDIR)/reports @mkdir -p $(OUTPUTDIR)/mapped @mkdir -p $(OUTPUTDIR)/unmapped +ifeq ($(SAIFPOWER), 1) + cp -f ../pipelined/regression/power.saif . +endif dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out -# @cp mapped/*.sdc ../../outputs/ -# @cp mapped/*.vh ../../outputs/ -# @sed -i 's/${VARIANT}/18T_ms/g' scripts/synth.tcl -# @sed -i 's/${VARIANT}/18T_ms/g' .synopsys_dc.setup clean: rm -rf alib-52 WORK analyzed $(NAME).out @@ -41,6 +37,7 @@ clean: rm -f default.svf rm -f command.log rm -f filenames*.log + rm -f power.saif diff --git a/synthDC/scripts/synth.tcl b/synthDC/scripts/synth.tcl index dac48a5d7..adcbe854e 100755 --- a/synthDC/scripts/synth.tcl +++ b/synthDC/scripts/synth.tcl @@ -3,8 +3,6 @@ # james.stine@okstate.edu 27 Sep 2015 # -# Enables name mapping -saif_map -start # get outputDir from environment (Makefile) set outputDir $::env(OUTPUTDIR) @@ -12,6 +10,7 @@ set cfgName $::env(CONFIG) # Config set hdl_src "../pipelined/src" set cfg "${hdl_src}/../config/${cfgName}/wally-config.vh" +set saifpower $::env(SAIFPOWER) eval file copy -force ${cfg} {hdl/} eval file copy -force ${cfg} $outputDir @@ -19,6 +18,11 @@ eval file copy -force [glob ${hdl_src}/../config/shared/*.vh] {hdl/} eval file copy -force [glob ${hdl_src}/*/*.sv] {hdl/} eval file copy -force [glob ${hdl_src}/*/flop/*.sv] {hdl/} +# Enables name mapping +if { $saifpower == 1 } { + saif_map -start +} + # Verilog files set my_verilog_files [glob hdl/*] @@ -51,11 +55,11 @@ link # Reset all constraints reset_design -# SAIF power prediction (optional) -# set_power_prediction - # Power Dissipation Analysis -# read_saif -input vcd/mult.saif -instance_name stimulus/dut -auto_map_names -verbose +######### OPTIONAL !!!!!!!!!!!!!!!! +if { $saifpower == 1 } { + read_saif -input power.saif -instance_name testbench/dut/core -auto_map_names -verbose +} # Set reset false path set_false_path -from [get_ports reset] From c015bae64a769c03c84093df2e501e44605fd6ac Mon Sep 17 00:00:00 2001 From: Ross Thompson Date: Wed, 9 Feb 2022 18:47:20 -0600 Subject: [PATCH 14/14] Added explainations of synthesis variables in README. --- synthDC/README.md | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/synthDC/README.md b/synthDC/README.md index 201eeadc8..12c9e5a0a 100644 --- a/synthDC/README.md +++ b/synthDC/README.md @@ -7,6 +7,33 @@ scripts/synth.tcl. Example Usage make synth DESIGN=wallypipelinedcore FREQ=300 +environment variables + +DESIGN + Design provides the name of the output log. Default is synth. + +FREQ + Frequency in Mhz. Default is 500 + +CONFIG + The wally configuration file. Default is rv32e. + Examples. + rv32e + rv64gc + rv32gc + +TECH + The target standard cell library. Default is 130. + 90: skywater 90nm tt 25C. + 130: skywater 130nm tt 25C. + +SAIFPOWER + Controls if power analysis is driven by switching factor or RTL modelsim simulation. + When enabled requires a saif file named power.saif. + Default is 0. + 0: switching factor power analysis + 1: RTL simulation driven power analysis. + Libraries in .synopsys_dc.setup file set s8lib $timing_lib/sky130_osu_sc_t12/12T_ms/lib