diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv
index 71b11abee..2d59ccfd7 100644
--- a/src/cache/cacheLRU.sv
+++ b/src/cache/cacheLRU.sv
@@ -142,7 +142,7 @@ module cacheLRU
   // This is a two port memory.
   // Every cycle must read from CacheSetData and each load/store must write the new LRU.
   always_ff @(posedge clk) begin
-    if (reset) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] = '0; // exclusion-tag: initialize
+    if (reset) for (int set = 0; set < NUMLINES; set++) LRUMemory[set] <= '0; // exclusion-tag: initialize
     if(CacheEn) begin
       if(LRUWriteEn)
         LRUMemory[PAdr] <= NextLRU;