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found the bug in the store modification

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This commit is contained in:
Katherine Parry 2022-07-12 22:42:19 +00:00
parent 2ada8a8bc1
commit 452b017f9a
2 changed files with 5 additions and 5 deletions
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4
pipelined/src/lsu/lsu.sv
View File

@ -235,8 +235,8 @@ module lsu (
.s(SelUncachedAdr), .y(LSUBusHWDATA)); .s(SelUncachedAdr), .y(LSUBusHWDATA));
if(CACHE_ENABLED) begin : dcache if(CACHE_ENABLED) begin : dcache
if (`LLEN>`FLEN) if (`LLEN>`XLEN)
mux2 #(`LLEN) datamux({{`LLEN-`XLEN{1'b0}}, IEUWriteDataM}, FWriteDataM, FpLoadStoreM, FinalWriteDataM); mux2 #(`LLEN) datamux({IEUWriteDataM, IEUWriteDataM}, FWriteDataM, FpLoadStoreM, FinalWriteDataM);
else else
assign FinalWriteDataM = {{`LLEN-`XLEN{1'b0}}, IEUWriteDataM}; assign FinalWriteDataM = {{`LLEN-`XLEN{1'b0}}, IEUWriteDataM};
cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN), cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),

6
tests/riscof/spike/spike_rv32imc_isa.yaml
View File

@ -1,11 +1,11 @@
hart_ids: [0] hart_ids: [0]
hart0: hart0:
ISA: RV32IMAFCZicsr_Zifencei ISA: RV32IMAFDCZicsr_Zifencei
physical_addr_sz: 32 physical_addr_sz: 32
User_Spec_Version: '2.3' User_Spec_Version: '2.3'
supported_xlen: [32] supported_xlen: [32]
misa: misa:
reset-val: 0x40001125 reset-val: 0x4000112D
rv32: rv32:
accessible: true accessible: true
mxl: mxl:
@ -23,6 +23,6 @@ hart0:
warl: warl:
dependency_fields: [] dependency_fields: []
legal: legal:
- extensions[25:0] bitmask [0x0001125, 0x0000000] - extensions[25:0] bitmask [0x000112D, 0x0000000]
wr_illegal: wr_illegal:
- Unchanged - Unchanged