First cut at removing the linux testbench and merging build root into the main testbench.

sim/wally-batch.do

@@ -51,35 +51,7 @@ if {$argc >= 3} {
 
 # default to config/rv64ic, but allow this to be overridden at the command line.  For example:
 # do wally-pipelined-batch.do ../config/rv32imc rv32imc
-if {$2 eq "buildroot"} {
+if {$2 eq "configOptions"} {
-    vlog -lint -work wkdir/work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../src/cvw.sv ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
-    # start and run simulation
-    if { $coverage } {
-        echo "wally-batch buildroot coverage"
-        vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -o testbenchopt +cover=sbecf
-        vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286  -fatal 7 -cover
-     } else {
-        vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -o testbenchopt 
-        vsim -lib wkdir/work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3691,13286  -fatal 7
-    }
-
-    run -all
-    run -all
-    exec ./slack-notifier/slack-notifier.py
-} elseif {$2 eq "buildroot-no-trace"} {
-    vlog -lint -work work_${1}_${2} +incdir+../config/$1 +incdir+../config/deriv/$1 +incdir+../config/shared ../testbench/testbench-linux.sv ../testbench/common/*.sv ../src/*/*.sv ../src/*/*/*.sv -suppress 2583
-    # start and run simulation
-    vopt +acc work_${1}_${2}.testbench -work work_${1}_${2} -G RISCV_DIR=$3 -G INSTR_LIMIT=$4 -G INSTR_WAVEON=$5 -G NO_SPOOFING=1 -o testbenchopt 
-    vsim -lib work_${1}_${2} testbenchopt -suppress 8852,12070,3084,3829,13286  -fatal 7
-
-    #-- Run the Simulation
-    echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
-    echo "Don't forget to change DEBUG_LEVEL = 0."
-    echo "!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!"
-    run -all
-    run -all
-    exec ./slack-notifier/slack-notifier.py
-} elseif {$2 eq "configOptions"} {
     # set arguments " "
     # for {set i 5} {$i <= $argc} {incr i} {
     # 	append arguments "\$$i "
@@ -111,12 +83,13 @@ if {$2 eq "buildroot"} {
         vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt +cover=sbecf
         vsim -lib wkdir/work_${1}_${2} testbenchopt  -fatal 7 -suppress 3829 -coverage
     } else {
-        vopt wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt
+        vopt +acc wkdir/work_${1}_${2}.testbench -work wkdir/work_${1}_${2} -G TEST=$2 -o testbenchopt
         vsim -lib wkdir/work_${1}_${2} testbenchopt  -fatal 7 -suppress 3829
     }
 #    vsim -lib wkdir/work_${1}_${2} testbenchopt  -fatal 7 -suppress 3829
     # power add generates the logging necessary for said generation.
     # power add -r /dut/core/*
+    do wave.do
     run -all
     # power off -r /dut/core/*
 } 

testbench/testbench.sv

@@ -40,6 +40,7 @@ module testbench;
   parameter BPRED_LOGGER=0;
   parameter I_CACHE_ADDR_LOGGER=0;
   parameter D_CACHE_ADDR_LOGGER=0;
+  parameter RISCV_DIR = "/opt/riscv";
  
 `include "parameter-defs.vh"
 
@@ -134,6 +135,7 @@ module testbench;
         "arch64zfh_divsqrt":     if (P.ZFH_SUPPORTED)     tests = arch64zfh_divsqrt;
         "arch64zfaf":    if (P.ZFA_SUPPORTED)     tests = arch64zfaf;
         "arch64zfad":    if (P.ZFA_SUPPORTED & P.D_SUPPORTED)  tests = arch64zfad;
+        "buildroot":                              tests = buildroot;
       endcase 
     end else begin // RV32
       case (TEST)
@@ -210,7 +212,7 @@ module testbench;
   logic        ResetCntRst;
   logic        CopyRAM;
 
-  string  signame, memfilename, pathname;
+  string  signame, memfilename, bootmemfilename, pathname;
   integer begin_signature_addr, end_signature_addr, signature_size;
 
   assign ResetThreshold = 3'd5;
@@ -279,7 +281,12 @@ module testbench;
   always @(posedge clk) begin
     if(SelectTest) begin
       if (riscofTest) memfilename = {pathname, tests[test], "/ref/ref.elf.memfile"};
+      else if(TEST == "buildroot") begin 
+        memfilename = {RISCV_DIR, "/linux-testvectors/ram.bin"};
+        bootmemfilename = {RISCV_DIR, "/linux-testvectors/bootmem.bin"};
+      end
       else            memfilename = {pathname, tests[test], ".elf.memfile"};
+      $display("!!!!!!!!!!!!!!!!!!!!!memfilename is %s \n", memfilename);
       if (riscofTest) begin
         ProgramAddrMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.addr"};
         ProgramLabelMapFile = {pathname, tests[test], "/ref/ref.elf.objdump.lab"};
@@ -352,6 +359,8 @@ module testbench;
   integer StartIndex;
   integer EndIndex;
   integer BaseIndex;
+  integer memFile;
+  integer readResult;
   if (P.SDC_SUPPORTED) begin
     always @(posedge clk) begin
       if (LoadMem) begin
@@ -373,7 +382,16 @@ module testbench;
   end else if (P.BUS_SUPPORTED) begin : bus_supported
     always @(posedge clk) begin
       if (LoadMem) begin
-        $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+        if (TEST == "buildroot") begin
+          memFile = $fopen(bootmemfilename, "rb");
+          readResult = $fread(dut.uncore.uncore.ram.ram.memory.RAM, memFile);
+          $fclose(memFile);
+          memFile = $fopen(memfilename, "rb");
+          readResult = $fread(dut.uncore.uncore.bootrom.bootrom.memory.ROM, memFile);
+          $fclose(memFile);
+        end else 
+          $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
+        if (TEST == "embench") $display("Read memfile %s", memfilename);
       end
       if (CopyRAM) begin
         LogXLEN = (1 + P.XLEN/32); // 2 for rv32 and 3 for rv64

testbench/tests.vh

@@ -31,6 +31,7 @@
 `define EMBENCH "4"
 `define CUSTOM "5"
 `define COVERAGE "6"
+`define BUILDROOT "7"
 
 string tvpaths[] = '{
     "$RISCV/imperas-riscv-tests/work/",
@@ -71,6 +72,11 @@ string tvpaths[] = '{
     "pmpadrdecs"
   };
 
+  string buildroot[] = '{
+    `BUILDROOT,
+    "buildroot"
+  };
+
   string coremark[] = '{
     `COREMARK,
     "coremark.bare.riscv"