diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index 2ef9df8ae..e69335ce0 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -33,6 +33,7 @@ module alu #(parameter WIDTH=32) ( input logic [WIDTH-1:0] A, B, // Operands input logic [2:0] ALUControl, // With Funct3, indicates operation to perform input logic [2:0] ALUSelect, // ALU mux select signal + input logic [3:0] BSelect, // One-Hot encoding of ZBA_ZBB_ZBC_ZBS instruction input logic [6:0] Funct7, // Funct7 from execute stage (we only need this for b instructions and should be optimized out later) input logic [2:0] Funct3, // With ALUControl, indicates operation to perform NOTE: Change signal name to ALUSelect output logic [WIDTH-1:0] Result, // ALU result @@ -40,15 +41,18 @@ module alu #(parameter WIDTH=32) ( // CondInvB = ~B when subtracting, B otherwise. Shift = shift result. SLT/U = result of a slt/u instruction. // FullResult = ALU result before adjusting for a RV64 w-suffix instruction. - logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult; // Intermediate results - logic Carry, Neg; // Flags: carry out, negative - logic LT, LTU; // Less than, Less than unsigned - logic W64; // RV64 W-type instruction - logic SubArith; // Performing subtraction or arithmetic right shift - logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops - logic Asign, Bsign; // Sign bits of A, B + logic [WIDTH-1:0] CondInvB, Shift, SLT, SLTU, FullResult,ALUResult, ZBCResult, CondMaskB; // Intermediate results + logic Carry, Neg; // Flags: carry out, negative + logic LT, LTU; // Less than, Less than unsigned + logic W64; // RV64 W-type instruction + logic SubArith; // Performing subtraction or arithmetic right shift + logic ALUOp; // 0 for address generation addition or 1 for regular ALU ops + logic Asign, Bsign; // Sign bits of A, B logic Rotate; + + decoder #($clog2(WIDTH)) maskgen (B[$clog2(WIDTH)-1:0], CondMaskB); + // Extract control signals from ALUControl. assign {W64, SubArith, ALUOp} = ALUControl; diff --git a/src/ieu/bmu/bmuctrl.sv b/src/ieu/bmu/bmuctrl.sv index 2b0bb63f9..7c95f06c5 100644 --- a/src/ieu/bmu/bmuctrl.sv +++ b/src/ieu/bmu/bmuctrl.sv @@ -36,19 +36,20 @@ module bmuctrl( input logic StallD, FlushD, // Stall, flush Decode stage input logic [31:0] InstrD, // Instruction in Decode stage output logic [2:0] ALUSelectD, // ALU Mux select signal - output logic bextD, // Indicates if bit extract instruction // Execute stage control signals input logic StallE, FlushE, // Stall, flush Execute stage output logic [6:0] Funct7E, // Instruction's funct7 field (note: eventually want to get rid of this) - output logic [2:0] ALUSelectE + output logic [2:0] ALUSelectE, + output logic [3:0] BSelectE // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding ); logic [6:0] OpD; // Opcode in Decode stage logic [2:0] Funct3D; // Funct3 field in Decode stage logic [6:0] Funct7D; // Funct7 field in Decode stage logic [4:0] Rs1D; // Rs1 source register in Decode stage + logic [3:0] BSelectD; // Indicates if ZBA_ZBB_ZBC_ZBS instruction decode stage - `define BMUCTRLW 4 + `define BMUCTRLW 7 logic [`BMUCTRLW-1:0] BMUControlsD; // Main B Instructions Decoder control signals @@ -62,25 +63,25 @@ module bmuctrl( // Main Instruction Decoder always_comb casez({OpD, Funct7D, Funct3D}) - // ALUSelect_bextD - 17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0; // bclri - 17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_1; // bexti - 17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0; // binvi - 17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0; // bseti - 17'b0110011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0; // bclr - 17'b0110011_010010?_101: BMUControlsD = `BMUCTRLW'b101_1; // bext - 17'b0110011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0; // binv - 17'b0110011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0; // bset - 17'b0110011_0?00000_?01: BMUControlsD = `BMUCTRLW'b001_0; // sra, srl, sll - default: BMUControlsD = {Funct3D, {1'b0}};// not B instruction or shift + // ALUSelect_zbsD + 17'b0010011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0001; // bclri + 17'b0010011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001; // bexti + 17'b0010011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001; // binvi + 17'b0010011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001; // bseti + 17'b0110011_010010?_001: BMUControlsD = `BMUCTRLW'b111_0001; // bclr + 17'b0110011_010010?_101: BMUControlsD = `BMUCTRLW'b101_0001; // bext + 17'b0110011_011010?_001: BMUControlsD = `BMUCTRLW'b100_0001; // binv + 17'b0110011_001010?_001: BMUControlsD = `BMUCTRLW'b110_0001; // bset + 17'b0110011_0?00000_?01: BMUControlsD = `BMUCTRLW'b001_0001; // sra, srl, sll + default: BMUControlsD = {Funct3D, {4'b0}}; // not B instruction or shift endcase // Unpack Control Signals - assign {ALUSelectD,bextD} = BMUControlsD; + assign {ALUSelectD,BSelectD} = BMUControlsD; // BMU Execute stage pipieline control register - flopenrc#(10) controlregBMU(clk, reset, FlushE, ~StallE, {Funct7D, ALUSelectD}, {Funct7E, ALUSelectE}); + flopenrc#(14) controlregBMU(clk, reset, FlushE, ~StallE, {Funct7D, ALUSelectD, BSelectD}, {Funct7E, ALUSelectE, BSelectE}); endmodule \ No newline at end of file diff --git a/src/ieu/controller.sv b/src/ieu/controller.sv index 7e054b5d7..0ed3d727e 100644 --- a/src/ieu/controller.sv +++ b/src/ieu/controller.sv @@ -56,6 +56,7 @@ module controller( output logic JumpE, // jump instruction output logic SCE, // Store Conditional instruction output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) + output logic [3:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction // Memory stage control signals input logic StallM, FlushM, // Stall, flush Memory stage output logic [1:0] MemRWM, // Mem read/write: MemRWM[1] = 1 for read, MemRWM[0] = 1 for write @@ -104,7 +105,7 @@ module controller( logic InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$ logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu - logic subD, sraD, sltD, sltuD, bextD; // Indicates if is one of these instructions + logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions logic BranchTakenE; // Branch is taken logic eqE, ltE; // Comparator outputs logic unused; @@ -197,15 +198,15 @@ module controller( assign sltuD = (Funct3D == 3'b011); assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi assign sraD = (Funct3D == 3'b101 & Funct7D[5]); - assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & bextD)); // TRUE for R-type subtracts and sra, slt, sltu + assign SubArithD = ALUOpD & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & BSelectE[0] & ALUSelectD == 3'b101)); // TRUE for R-type subtracts and sra, slt, sltu, bext assign ALUControlD = {W64D, SubArithD, ALUOpD}; if (`ZBS_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags - bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .bextD, .StallE, .FlushE, .Funct7E, .ALUSelectE); + bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .StallE, .FlushE, .Funct7E, .ALUSelectE, BSelectE); end else begin: bitmanipi assign ALUSelectD = Funct3D; assign ALUSelectE = Funct3E; - assign bextD = 1'b0; + assign BSelectE = 4'b000; assign Funct7E = 7'b0; end diff --git a/src/ieu/datapath.sv b/src/ieu/datapath.sv index 3cf12b37d..604eab8d0 100644 --- a/src/ieu/datapath.sv +++ b/src/ieu/datapath.sv @@ -18,6 +18,7 @@ module datapath ( input logic [2:0] ALUSelectE, // ALU mux select signal input logic JumpE, // Is a jump (j) instruction input logic BranchSignedE, // Branch comparison operands are signed (if it's a branch) + input logic [3:0] BSelectE, // One hot encoding of ZBA_ZBB_ZBC_ZBS instruction output logic [1:0] FlagsE, // Comparison flags ({eq, lt}) output logic [`XLEN-1:0] IEUAdrE, // Address computed by ALU output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B @@ -82,7 +83,7 @@ module datapath ( comparator #(`XLEN) comp(ForwardedSrcAE, ForwardedSrcBE, BranchSignedE, FlagsE); mux2 #(`XLEN) srcamux(ForwardedSrcAE, PCE, ALUSrcAE, SrcAE); mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE); - alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, Funct7E, Funct3E, ALUResultE, IEUAdrE); + alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, ALUSelectE, BSelectE, Funct7E, Funct3E, ALUResultE, IEUAdrE); mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE); mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE); diff --git a/src/ieu/ieu.sv b/src/ieu/ieu.sv index b8ee90d0b..ba1d8756c 100644 --- a/src/ieu/ieu.sv +++ b/src/ieu/ieu.sv @@ -83,6 +83,7 @@ module ieu ( logic SCE; // Store Conditional instruction logic FWriteIntM; // FPU writing to integer register file logic IntDivW; // Integer divide instruction + logic [3:0] BSelectE; // Indicates if ZBA_ZBB_ZBC_ZBS instruction in one-hot encoding // Forwarding signals logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E; // Source and destination registers @@ -96,7 +97,7 @@ module ieu ( controller c( .clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE, - .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .MemReadE, .CSRReadE, + .PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .BSelectE, .MemReadE, .CSRReadE, .Funct3E, .Funct7E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM, .CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M, .RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .InstrValidE, .InstrValidD, .FWriteIntM, @@ -105,7 +106,7 @@ module ieu ( datapath dp( .clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE, .ALUControlE, .Funct3E, .Funct7E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .ALUSelectE, .JumpE, .BranchSignedE, - .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, + .PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BSelectE, .StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW, .StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW, .CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);