diff --git a/config/rv64gc/wally-config.vh b/config/rv64gc/wally-config.vh deleted file mode 100644 index 1dd3d7f4f..000000000 --- a/config/rv64gc/wally-config.vh +++ /dev/null @@ -1,159 +0,0 @@ -////////////////////////////////////////// -// wally-config.vh -// -// Written: David_Harris@hmc.edu 4 January 2021 -// Modified: -// -// Purpose: Specify which features are configured -// Macros to determine which modes are supported based on MISA -// -// A component of the Wally configurable RISC-V project. -// -// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 -// -// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file -// except in compliance with the License, or, at your option, the Apache License version 2.0. You -// may obtain a copy of the License at -// -// https://solderpad.org/licenses/SHL-2.1/ -// -// Unless required by applicable law or agreed to in writing, any work distributed under the -// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, -// either express or implied. See the License for the specific language governing permissions -// and limitations under the License. -//////////////////////////////////////////////////////////////////////////////////////////////// - -// include shared configuration -`include "wally-shared.vh" - -`define FPGA 0 -`define QEMU 0 - -// RV32 or RV64: XLEN = 32 or 64 -`define XLEN 64 - -// IEEE 754 compliance -`define IEEE754 0 - -// MISA RISC-V configuration per specification -`define MISA (32'h00000104 | 1 << 5 | 1 << 3 | 1 << 18 | 1 << 20 | 1 << 12 | 1 << 0 ) -`define ZICSR_SUPPORTED 1 -`define ZIFENCEI_SUPPORTED 1 -`define COUNTERS 32 -`define ZICOUNTERS_SUPPORTED 1 -`define ZFH_SUPPORTED 0 -`define SSTC_SUPPORTED 1 - -// LSU microarchitectural Features -`define BUS_SUPPORTED 1 -`define DCACHE_SUPPORTED 1 -`define ICACHE_SUPPORTED 1 -`define VIRTMEM_SUPPORTED 1 -`define VECTORED_INTERRUPTS_SUPPORTED 1 -`define BIGENDIAN_SUPPORTED 1 - -// TLB configuration. Entries should be a power of 2 -`define ITLB_ENTRIES 32 -`define DTLB_ENTRIES 32 - -// Cache configuration. Sizes should be a power of two -// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines -`define DCACHE_NUMWAYS 4 -`define DCACHE_WAYSIZEINBYTES 4096 -`define DCACHE_LINELENINBITS 512 -`define ICACHE_NUMWAYS 4 -`define ICACHE_WAYSIZEINBYTES 4096 -`define ICACHE_LINELENINBITS 512 - -// Integer Divider Configuration -// IDIV_BITSPERCYCLE must be 1, 2, or 4 -`define IDIV_BITSPERCYCLE 4 -`define IDIV_ON_FPU 1 - -// Legal number of PMP entries are 0, 16, or 64 -`define PMP_ENTRIES 16 - -// Address space -`define RESET_VECTOR 64'h0000000080000000 - -// Bus Interface width -`define AHBW 64 - -// WFI Timeout Wait -`define WFI_TIMEOUT_BIT 16 - -// Peripheral Physical Addresses -// Peripheral memory space extends from BASE to BASE+RANGE -// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits - -// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file? -`define DTIM_SUPPORTED 1'b0 -`define DTIM_BASE 56'h80000000 -`define DTIM_RANGE 56'h007FFFFF -`define IROM_SUPPORTED 1'b0 -`define IROM_BASE 56'h80000000 -`define IROM_RANGE 56'h007FFFFF -`define BOOTROM_SUPPORTED 1'b1 -`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder -`define BOOTROM_RANGE 56'h00000FFF -`define UNCORE_RAM_SUPPORTED 1'b1 -`define UNCORE_RAM_BASE 56'h80000000 -`define UNCORE_RAM_RANGE 56'h7FFFFFFF -`define EXT_MEM_SUPPORTED 1'b0 -`define EXT_MEM_BASE 56'h80000000 -`define EXT_MEM_RANGE 56'h07FFFFFF -`define CLINT_SUPPORTED 1'b1 -`define CLINT_BASE 56'h02000000 -`define CLINT_RANGE 56'h0000FFFF -`define GPIO_SUPPORTED 1'b1 -`define GPIO_BASE 56'h10060000 -`define GPIO_RANGE 56'h000000FF -`define UART_SUPPORTED 1'b1 -`define UART_BASE 56'h10000000 -`define UART_RANGE 56'h00000007 -`define PLIC_SUPPORTED 1'b1 -`define PLIC_BASE 56'h0C000000 -`define PLIC_RANGE 56'h03FFFFFF -`define SDC_SUPPORTED 1'b0 -`define SDC_BASE 56'h00012100 -`define SDC_RANGE 56'h0000001F - -// Test modes - -// Tie GPIO outputs back to inputs -`define GPIO_LOOPBACK_TEST 1 - -// Hardware configuration -`define UART_PRESCALE 1 - -// Interrupt configuration -`define PLIC_NUM_SRC 10 -// comment out the following if >=32 sources -`define PLIC_NUM_SRC_LT_32 -`define PLIC_GPIO_ID 3 -`define PLIC_UART_ID 10 - -`define BPRED_SUPPORTED 1 -//`define BPRED_TYPE "BP_GLOBAL_BASIC" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -`define BPRED_TYPE "BP_GSHARE" // "BP_LOCAL_REPAIR" // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT -`define BPRED_SIZE 10 -`define BPRED_NUM_LHR 4 -`define BTB_SIZE 10 - -`define SVADU_SUPPORTED 1 -`define ZMMUL_SUPPORTED 0 - -// FPU division architecture -`define RADIX 32'h4 -`define DIVCOPIES 32'h4 - -// bit manipulation -`define ZBA_SUPPORTED 1 -`define ZBB_SUPPORTED 1 -`define ZBC_SUPPORTED 1 -`define ZBS_SUPPORTED 1 - -// Memory synthesis configuration -`define USE_SRAM 0 diff --git a/src/cache/cacheLRU.sv b/src/cache/cacheLRU.sv index e84c34dee..146a67cd1 100644 --- a/src/cache/cacheLRU.sv +++ b/src/cache/cacheLRU.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module cacheLRU #(parameter NUMWAYS = 4, SETLEN = 9, OFFSETLEN = 5, NUMLINES = 128) ( input logic clk, diff --git a/src/cache/cachefsm.sv b/src/cache/cachefsm.sv index 544e3454e..0909ae82d 100644 --- a/src/cache/cachefsm.sv +++ b/src/cache/cachefsm.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module cachefsm #(parameter READ_ONLY_CACHE = 0) ( input logic clk, input logic reset, diff --git a/src/cache/subcachelineread.sv b/src/cache/subcachelineread.sv index ea305fb6c..0c0e11c29 100644 --- a/src/cache/subcachelineread.sv +++ b/src/cache/subcachelineread.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module subcachelineread #(parameter LINELEN, WORDLEN, parameter MUXINTERVAL )( // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$ input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, // Physical address diff --git a/src/generic/adder.sv b/src/generic/adder.sv index 7acd20df0..13b649a48 100644 --- a/src/generic/adder.sv +++ b/src/generic/adder.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module adder #(parameter WIDTH=8) ( input logic [WIDTH-1:0] a, b, output logic [WIDTH-1:0] y diff --git a/src/generic/aplusbeq0.sv b/src/generic/aplusbeq0.sv index d322216b3..f8d675b33 100644 --- a/src/generic/aplusbeq0.sv +++ b/src/generic/aplusbeq0.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module aplusbeq0 #(parameter WIDTH = 8) ( input logic [WIDTH-1:0] a, b, output logic zero @@ -40,4 +38,4 @@ module aplusbeq0 #(parameter WIDTH = 8) ( assign x = a ^ b; assign orshift = {a[WIDTH-2:0] | b[WIDTH-2:0], 1'b0}; assign zero = (x == orshift); -endmodule \ No newline at end of file +endmodule diff --git a/src/generic/arrs.sv b/src/generic/arrs.sv index 5a9cf21f0..dd473b307 100644 --- a/src/generic/arrs.sv +++ b/src/generic/arrs.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module arrs( input logic clk, input logic areset, diff --git a/src/generic/clockgater.sv b/src/generic/clockgater.sv index c09f98f2c..c0150133c 100644 --- a/src/generic/clockgater.sv +++ b/src/generic/clockgater.sv @@ -24,16 +24,14 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - -module clockgater ( +module clockgater #(parameter FPGA) ( input logic E, input logic SE, input logic CLK, output logic ECLK ); - if (`FPGA) BUFGCE bufgce_i0 (.I(CLK), .CE(E | SE), .O(ECLK)); + if (FPGA) BUFGCE bufgce_i0 (.I(CLK), .CE(E | SE), .O(ECLK)); else begin // *** BUG // VERY IMPORTANT. diff --git a/src/generic/counter.sv b/src/generic/counter.sv index 1480dc929..7957976ee 100644 --- a/src/generic/counter.sv +++ b/src/generic/counter.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module counter #(parameter WIDTH=8) ( input logic clk, reset, en, output logic [WIDTH-1:0] q diff --git a/src/generic/decoder.sv b/src/generic/decoder.sv index 807a6d6ca..6284a454c 100644 --- a/src/generic/decoder.sv +++ b/src/generic/decoder.sv @@ -23,8 +23,6 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-config.vh" - module decoder #(parameter BINARY_BITS = 3) ( input logic [BINARY_BITS-1:0] binary, output logic [(2**BINARY_BITS)-1:0] onehot diff --git a/src/generic/mem/ram1p1rwbe.sv b/src/generic/mem/ram1p1rwbe.sv index 95ba152f7..56637c0ce 100644 --- a/src/generic/mem/ram1p1rwbe.sv +++ b/src/generic/mem/ram1p1rwbe.sv @@ -30,8 +30,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words module ram1p1rwbe import cvw::*; #(parameter cvw_t P, parameter DEPTH=64, WIDTH=44) ( diff --git a/src/generic/mem/ram2p1r1wbe.sv b/src/generic/mem/ram2p1r1wbe.sv index 18ed9d5ea..202d0432b 100644 --- a/src/generic/mem/ram2p1r1wbe.sv +++ b/src/generic/mem/ram2p1r1wbe.sv @@ -29,11 +29,10 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - // WIDTH is number of bits in one "word" of the memory, DEPTH is number of such words -module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68, USE_SRAM=1) ( +module ram2p1r1wbe import cvw::*; #(parameter cvw_t P, + parameter DEPTH=1024, WIDTH=68) ( input logic clk, input logic ce1, ce2, input logic [$clog2(DEPTH)-1:0] ra1, @@ -52,7 +51,7 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68, USE_SRAM=1) ( // TRUE Smem macro // *************************************************************************** - if ((USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin + if ((P.USE_SRAM == 1) & (WIDTH == 68) & (DEPTH == 1024)) begin ram2p1r1wbe_1024x68 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), @@ -64,7 +63,7 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68, USE_SRAM=1) ( .QA(rd1), .QB()); - end else if ((USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin + end else if ((P.USE_SRAM == 1) & (WIDTH == 36) & (DEPTH == 1024)) begin ram2p1r1wbe_1024x36 memory1(.CLKA(clk), .CLKB(clk), .CEBA(~ce1), .CEBB(~ce2), @@ -76,7 +75,7 @@ module ram2p1r1wbe #(parameter DEPTH=1024, WIDTH=68, USE_SRAM=1) ( .QA(rd1), .QB()); - end else if ((`USE_SRAM == 1) & (WIDTH == 2) & (DEPTH == 1024)) begin + end else if ((P.USE_SRAM == 1) & (WIDTH == 2) & (DEPTH == 1024)) begin logic [SRAMWIDTH-1:0] SRAMReadData; logic [SRAMWIDTH-1:0] SRAMWriteData; diff --git a/src/generic/mux.sv b/src/generic/mux.sv index 223d41afc..9c1dfe335 100644 --- a/src/generic/mux.sv +++ b/src/generic/mux.sv @@ -24,7 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" /* verilator lint_off DECLFILENAME */ module mux2 #(parameter WIDTH = 8) ( diff --git a/src/generic/neg.sv b/src/generic/neg.sv index 66be9e073..df2a9b9c7 100644 --- a/src/generic/neg.sv +++ b/src/generic/neg.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module neg #(parameter WIDTH = 8) ( input logic [WIDTH-1:0] a, output logic [WIDTH-1:0] y); diff --git a/src/generic/onehotdecoder.sv b/src/generic/onehotdecoder.sv index 5e8f01c26..b672a08e5 100644 --- a/src/generic/onehotdecoder.sv +++ b/src/generic/onehotdecoder.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module onehotdecoder #(parameter WIDTH = 2) ( input logic [WIDTH-1:0] bin, output logic [2**WIDTH-1:0] decoded diff --git a/src/generic/or_rows.sv b/src/generic/or_rows.sv index 160bc7447..9a8aeb8cc 100644 --- a/src/generic/or_rows.sv +++ b/src/generic/or_rows.sv @@ -24,8 +24,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - // perform an OR of all the rows in an array, producing one output for each column // equivalent to assign y = a.or module or_rows #(parameter ROWS = 8, COLS=2) ( diff --git a/src/generic/priorityonehot.sv b/src/generic/priorityonehot.sv index ba5ebb90f..1cddb2bfc 100644 --- a/src/generic/priorityonehot.sv +++ b/src/generic/priorityonehot.sv @@ -33,8 +33,6 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-config.vh" - module priorityonehot #(parameter N = 8) ( input logic [N-1:0] a, output logic [N-1:0] y diff --git a/src/generic/prioritythermometer.sv b/src/generic/prioritythermometer.sv index d1970a805..6fe261265 100644 --- a/src/generic/prioritythermometer.sv +++ b/src/generic/prioritythermometer.sv @@ -29,8 +29,6 @@ // OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. /////////////////////////////////////////// -`include "wally-config.vh" - module prioritythermometer #(parameter N = 8) ( input logic [N-1:0] a, output logic [N-1:0] y diff --git a/src/ieu/alu.sv b/src/ieu/alu.sv index c3ad75551..4269a9af6 100644 --- a/src/ieu/alu.sv +++ b/src/ieu/alu.sv @@ -27,8 +27,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" - module alu import cvw::*; #(parameter cvw_t P, parameter WIDTH) ( input logic [WIDTH-1:0] A, B, // Operands input logic W64, // W64-type instruction diff --git a/src/ifu/bpred/bpred.sv b/src/ifu/bpred/bpred.sv index 2bc65caa6..2477f0cae 100644 --- a/src/ifu/bpred/bpred.sv +++ b/src/ifu/bpred/bpred.sv @@ -97,45 +97,45 @@ module bpred import cvw::*; #(parameter cvw_t P) ( // Part 1 branch direction prediction if (P.BPRED_TYPE == BP_TWOBIT) begin:Predictor - twoBitPredictor #(P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, + twoBitPredictor #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE, .BranchE, .BranchM, .PCSrcE); end else if (P.BPRED_TYPE == BP_GSHARE) begin:Predictor - gshare #(P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + gshare #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirPredF, .BPDirPredWrongE, .BPBranchF, .BranchD, .BranchE, .BranchM, .BranchW, .PCSrcE); end else if (P.BPRED_TYPE == BP_GLOBAL) begin:Predictor - gshare #(P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + gshare #(P, P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCF, .PCD, .PCE, .PCM, .BPDirPredF, .BPDirPredWrongE, .BPBranchF, .BranchD, .BranchE, .BranchM, .BranchW, .PCSrcE); end else if (P.BPRED_TYPE == BP_GSHARE_BASIC) begin:Predictor - gsharebasic #(P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + gsharebasic #(P, P.XLEN, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE, .BranchE, .BranchM, .PCSrcE); end else if (P.BPRED_TYPE == BP_GLOBAL_BASIC) begin:Predictor - gsharebasic #(P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, + gsharebasic #(P, P.XLEN, P.BPRED_SIZE, 0) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE, .BranchE, .BranchM, .PCSrcE); end else if (P.BPRED_TYPE == BP_LOCAL_BASIC) begin:Predictor - localbpbasic #(P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, + localbpbasic #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCM, .BPDirPredF, .BPDirPredWrongE, .BranchE, .BranchM, .PCSrcE); end else if (P.BPRED_TYPE == BP_LOCAL_AHEAD) begin:Predictor - localaheadbp #(P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, + localaheadbp #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE, .BranchE, .BranchM, .PCSrcE); end else if (P.BPRED_TYPE == BP_LOCAL_REPAIR) begin:Predictor - localrepairbp #(P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, + localrepairbp #(P, P.XLEN, P.BPRED_NUM_LHR, P.BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW, .PCNextF, .PCE, .PCM, .BPDirPredD(BPDirPredF), .BPDirPredWrongE, .BranchD, .BranchE, .BranchM, .PCSrcE); diff --git a/src/ifu/bpred/btb.sv b/src/ifu/bpred/btb.sv index d0e4db45e..e93c1decb 100644 --- a/src/ifu/bpred/btb.sv +++ b/src/ifu/bpred/btb.sv @@ -92,7 +92,7 @@ module btb import cvw::*; #(parameter cvw_t P, // An optimization may be using a PC relative address. - ram2p1r1wbe #(2**Depth, P.XLEN+4, P.USE_SRAM) memory( + ram2p1r1wbe #(P, 2**Depth, P.XLEN+4) memory( .clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredF), .ce2(~StallW & ~FlushW), .wa2(PCMIndex), .wd2({InstrClassM, IEUAdrM}), .we2(BTBWrongM), .bwe2('1)); diff --git a/src/ifu/bpred/gshare.sv b/src/ifu/bpred/gshare.sv index 640ddb273..460acbcbf 100644 --- a/src/ifu/bpred/gshare.sv +++ b/src/ifu/bpred/gshare.sv @@ -28,10 +28,10 @@ //////////////////////////////////////////////////////////////////////////////////////////////// -module gshare #(parameter XLEN, +module gshare import cvw::*; #(parameter cvw_t P, + parameter XLEN, parameter k = 10, - parameter integer TYPE = 1, - parameter USE_SRAM = 1) ( + parameter integer TYPE = 1) ( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -84,7 +84,7 @@ module gshare #(parameter XLEN, assign BPDirPredF = MatchX ? FwdNewDirPredF : TableBPDirPredF; - ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), + ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(TableBPDirPredF), diff --git a/src/ifu/bpred/gsharebasic.sv b/src/ifu/bpred/gsharebasic.sv index 636e5408c..2914c3e3f 100644 --- a/src/ifu/bpred/gsharebasic.sv +++ b/src/ifu/bpred/gsharebasic.sv @@ -27,10 +27,10 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module gsharebasic #(parameter XLEN, +module gsharebasic import cvw::*; #(parameter cvw_t P, + parameter XLEN, parameter k = 10, - parameter TYPE = 1, - parameter USE_SRAM = 1) ( + parameter TYPE = 1) ( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -58,7 +58,7 @@ module gsharebasic #(parameter XLEN, assign IndexM = GHRM; end - ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), + ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(BPDirPredF), diff --git a/src/ifu/bpred/localaheadbp.sv b/src/ifu/bpred/localaheadbp.sv index 2ba9ef960..266219416 100644 --- a/src/ifu/bpred/localaheadbp.sv +++ b/src/ifu/bpred/localaheadbp.sv @@ -25,10 +25,10 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module localaheadbp #(parameter XLEN, +module localaheadbp import cvw::*; #(parameter cvw_t P, + parameter XLEN, parameter m = 6, // 2^m = number of local history branches - parameter k = 10, - parameter USE_SRAM = 1) ( // number of past branches stored + parameter k = 10) ( // number of past branches stored input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -59,7 +59,7 @@ module localaheadbp #(parameter XLEN, //assign IndexNextF = LHR; assign IndexM = LHRW; - ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), + ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk), .ce1(~StallD), .ce2(~StallW & ~FlushW), .ra1(LHRF), .rd1(BPDirPredD), @@ -92,7 +92,7 @@ module localaheadbp #(parameter XLEN, assign IndexLHRM = {PCW[m+1] ^ PCW[1], PCW[m:2]}; assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]}; - ram2p1r1wbe #(2**m, k, USE_SRAM) BHT(.clk(clk), + ram2p1r1wbe #(P, 2**m, k) BHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexLHRNextF), .rd1(LHRF), diff --git a/src/ifu/bpred/localbpbasic.sv b/src/ifu/bpred/localbpbasic.sv index 1fc302d1c..8037b743d 100644 --- a/src/ifu/bpred/localbpbasic.sv +++ b/src/ifu/bpred/localbpbasic.sv @@ -26,10 +26,10 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module localbpbasic #(parameter XLEN, +module localbpbasic import cvw::*; #(parameter cvw_t P, + parameter XLEN, parameter m = 6, // 2^m = number of local history branches - parameter k = 10, - parameter USE_SRAM = 1) ( // number of past branches stored + parameter k = 10) ( // number of past branches stored input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -56,7 +56,7 @@ module localbpbasic #(parameter XLEN, assign IndexNextF = LHR; assign IndexM = LHRM; - ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), + ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(BPDirPredF), diff --git a/src/ifu/bpred/localrepairbp.sv b/src/ifu/bpred/localrepairbp.sv index 835096452..3af6d7b9f 100644 --- a/src/ifu/bpred/localrepairbp.sv +++ b/src/ifu/bpred/localrepairbp.sv @@ -25,10 +25,10 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module localrepairbp #(parameter XLEN, +module localrepairbp import cvw::*; #(parameter cvw_t P, + parameter XLEN, parameter m = 6, // 2^m = number of local history branches - parameter k = 10, - parameter USE_SRAM = 1) ( // number of past branches stored + parameter k = 10) ( // number of past branches stored input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -58,7 +58,7 @@ module localrepairbp #(parameter XLEN, logic SpeculativeFlushedF; - ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), + ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk), .ce1(~StallD), .ce2(~StallW & ~FlushW), .ra1(LHRF), .rd1(BPDirPredD), @@ -89,7 +89,7 @@ module localrepairbp #(parameter XLEN, assign IndexLHRM = {PCW[m+1] ^ PCW[1], PCW[m:2]}; assign IndexLHRNextF = {PCNextF[m+1] ^ PCNextF[1], PCNextF[m:2]}; - ram2p1r1wbe #(2**m, k, USE_SRAM) BHT(.clk(clk), + ram2p1r1wbe #(P, 2**m, k) BHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexLHRNextF), .rd1(LHRCommittedF), @@ -101,7 +101,7 @@ module localrepairbp #(parameter XLEN, assign IndexLHRD = {PCE[m+1] ^ PCE[1], PCE[m:2]}; assign LHRNextE = BranchD ? {BPDirPredD[1], LHRE[k-1:1]} : LHRE; // *** replace with a small CAM - ram2p1r1wbe #(2**m, k) SHB(.clk(clk), + ram2p1r1wbe #(P, 2**m, k) SHB(.clk(clk), .ce1(~StallF), .ce2(~StallE & ~FlushE), .ra1(IndexLHRNextF), .rd1(LHRSpeculativeF), diff --git a/src/ifu/bpred/twoBitPredictor.sv b/src/ifu/bpred/twoBitPredictor.sv index aeae77f14..52e24d901 100644 --- a/src/ifu/bpred/twoBitPredictor.sv +++ b/src/ifu/bpred/twoBitPredictor.sv @@ -26,9 +26,8 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -module twoBitPredictor #(parameter XLEN, - parameter k = 10, - parameter USE_SRAM = 1) ( +module twoBitPredictor import cvw::*; #(parameter cvw_t P, parameter XLEN, + parameter k = 10) ( input logic clk, input logic reset, input logic StallF, StallD, StallE, StallM, StallW, @@ -54,7 +53,7 @@ module twoBitPredictor #(parameter XLEN, assign IndexM = {PCM[k+1] ^ PCM[1], PCM[k:2]}; - ram2p1r1wbe #(2**k, 2, USE_SRAM) PHT(.clk(clk), + ram2p1r1wbe #(P, 2**k, 2) PHT(.clk(clk), .ce1(~StallF), .ce2(~StallW & ~FlushW), .ra1(IndexNextF), .rd1(BPDirPredF), diff --git a/testbench/common/wallyTracer.sv b/testbench/common/wallyTracer.sv index 221c8d7f8..142434de9 100644 --- a/testbench/common/wallyTracer.sv +++ b/testbench/common/wallyTracer.sv @@ -19,7 +19,6 @@ // and limitations under the License. //////////////////////////////////////////////////////////////////////////////////////////////// -`include "wally-config.vh" `define NUM_REGS 32 `define NUM_CSRS 4096 @@ -29,9 +28,10 @@ `define PRINT_ALL 0 `define PRINT_CSRS 0 -module wallyTracer(rvviTrace rvvi); - localparam NUMREGS = `E_SUPPORTED ? 16 : 32; +module wallyTracer import cvw::*; #(parameter cvw_t P) (rvviTrace rvvi); + + localparam NUMREGS = P.E_SUPPORTED ? 16 : 32; // wally specific signals logic reset; @@ -39,8 +39,8 @@ module wallyTracer(rvviTrace rvvi); logic InstrValidD, InstrValidE; logic StallF, StallD; logic STATUS_SXL, STATUS_UXL; - logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW; - logic [`XLEN-1:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW; + logic [P.XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM, PCW; + logic [P.XLEN-1:0] InstrRawD, InstrRawE, InstrRawM, InstrRawW; logic InstrValidM, InstrValidW; logic StallE, StallM, StallW; logic FlushD, FlushE, FlushM, FlushW; @@ -48,16 +48,16 @@ module wallyTracer(rvviTrace rvvi); logic IntrF, IntrD, IntrE, IntrM, IntrW; logic HaltM, HaltW; logic [1:0] PrivilegeModeW; - logic [`XLEN-1:0] rf[NUMREGS]; + logic [P.XLEN-1:0] rf[NUMREGS]; logic [NUMREGS-1:0] rf_wb; logic [4:0] rf_a3; logic rf_we3; - logic [`XLEN-1:0] frf[32]; + logic [P.XLEN-1:0] frf[32]; logic [`NUM_REGS-1:0] frf_wb; logic [4:0] frf_a4; logic frf_we4; - logic [`XLEN-1:0] CSRArray [logic[11:0]]; - logic [`XLEN-1:0] CSRArrayOld [logic[11:0]]; + logic [P.XLEN-1:0] CSRArray [logic[11:0]]; + logic [P.XLEN-1:0] CSRArrayOld [logic[11:0]]; logic [`NUM_CSRS-1:0] CSR_W; logic CSRWriteM, CSRWriteW; logic [11:0] CSRAdrM, CSRAdrW; @@ -102,8 +102,8 @@ module wallyTracer(rvviTrace rvvi); // PMPCFG space is 0-15 3a0 - 3af int i, i4, i8, csrid; - logic [`XLEN-1:0] pmp; - for (i=0; i<`PMP_ENTRIES; i+=8) begin + logic [P.XLEN-1:0] pmp; + for (i=0; i