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https://github.com/openhwgroup/cvw
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Fixed testbench-fp to reflect signal name changes
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@ -95,16 +95,13 @@ localparam BIAS2 = ((F_SUPPORTED & (LEN1 != S_LEN)) ? S_BIAS : H_BIAS);
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// intermediate division parameters not directly used in Divider
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// intermediate division parameters not directly used in Divider
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localparam FPDIVN = NF+3; // length of floating-point inputs: Ns + 2 = Nf + 3 for 1 integer bit, Nf fracitonal bits, 2 extra bits to shift sqrt into [1/4, 1)]
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localparam FPDIVN = NF+3; // length of floating-point inputs: Ns + 2 = Nf + 3 for 1 integer bit, Nf fracitonal bits, 2 extra bits to shift sqrt into [1/4, 1)]
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localparam DIVN = ((FPDIVN<XLEN) & IDIV_ON_FPU) ? XLEN : FPDIVN+3; // standard length of input: max(XLEN, NF+2) ***
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localparam DIVN = ((FPDIVN<XLEN) & IDIV_ON_FPU) ? XLEN : FPDIVN; // standard length of input: max(XLEN, NF+2) ***
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// division constants
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// division constants
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// *** define NF+2, justify, use in DIVN
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localparam LOGR = $clog2(RADIX); // r = log(R)
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localparam LOGR = $clog2(RADIX); // r = log(R)
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localparam RK = LOGR*DIVCOPIES; // r*k bits per cycle generated
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localparam RK = LOGR*DIVCOPIES; // r*k bits per cycle generated
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//localparam FPDUR = (DIVN+1)/RK + 1 + (RADIX/4); // *** relate to algorithm for rest of these
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localparam FPDUR = (DIVN+LOGR-1)/RK + 1 ; // ceiling((n+r)/rk)
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localparam FPDUR = (DIVN+LOGR-1)/RK + 1 ; // ceiling((DIVN+LOGR)/RK)
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localparam DURLEN = $clog2(FPDUR+1); // number of bits to represent the duration
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localparam DURLEN = $clog2(FPDUR+1);
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localparam DIVb = FPDUR*RK - 1; // canonical fdiv size (b)
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localparam DIVb = FPDUR*RK - 1; // canonical fdiv size (b)
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localparam DIVBLEN = $clog2(DIVb+2)-1; // *** where is 2 coming from?
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localparam DIVBLEN = $clog2(DIVb+2)-1; // *** where is 2 coming from?
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@ -115,8 +115,8 @@ module testbenchfp;
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logic FlushE;
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logic FlushE;
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logic IFDivStartE;
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logic IFDivStartE;
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logic FDivDoneE;
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logic FDivDoneE;
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logic [P.NE+1:0] QeM;
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logic [P.NE+1:0] UeM;
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logic [P.DIVb:0] QmM;
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logic [P.DIVb:0] UmM;
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logic [P.XLEN-1:0] FIntDivResultM;
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logic [P.XLEN-1:0] FIntDivResultM;
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logic ResMatch; // Check if result match
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logic ResMatch; // Check if result match
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logic FlagMatch; // Check if IEEE flags match
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logic FlagMatch; // Check if IEEE flags match
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@ -705,7 +705,7 @@ module testbenchfp;
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end
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end
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postprocess #(P) postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]),
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postprocess #(P) postprocess(.Xs(Xs), .Ys(Ys), .PostProcSel(UnitVal[1:0]),
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.OpCtrl(OpCtrlVal), .DivQm(Quot), .DivQe(DivCalcExp),
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.OpCtrl(OpCtrlVal), .DivUm(Quot), .DivUe(DivCalcExp),
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.Xm(Xm), .Ym(Ym), .Zm(Zm), .CvtCe(CvtCalcExpE), .DivSticky(DivSticky), .FmaSs(Ss),
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.Xm(Xm), .Ym(Ym), .Zm(Zm), .CvtCe(CvtCalcExpE), .DivSticky(DivSticky), .FmaSs(Ss),
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.XNaN(XNaN), .YNaN(YNaN), .ZNaN(ZNaN), .CvtResSubnormUf(CvtResSubnormUfE),
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.XNaN(XNaN), .YNaN(YNaN), .ZNaN(ZNaN), .CvtResSubnormUf(CvtResSubnormUfE),
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.XZero(XZero), .YZero(YZero), .CvtShiftAmt(CvtShiftAmtE),
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.XZero(XZero), .YZero(YZero), .CvtShiftAmt(CvtShiftAmtE),
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@ -734,8 +734,8 @@ module testbenchfp;
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.XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero),
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.XInfE(XInf), .YInfE(YInf), .XZeroE(XZero), .YZeroE(YZero),
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.XNaNE(XNaN), .YNaNE(YNaN),
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.XNaNE(XNaN), .YNaNE(YNaN),
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.FDivStartE(DivStart), .IDivStartE(1'b0), .W64E(1'b0),
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.FDivStartE(DivStart), .IDivStartE(1'b0), .W64E(1'b0),
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.StallM(1'b0), .DivStickyM(DivSticky), .FDivBusyE, .QeM(DivCalcExp),
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.StallM(1'b0), .DivStickyM(DivSticky), .FDivBusyE, .UeM(DivCalcExp),
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.QmM(Quot),
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.UmM(Quot),
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.FlushE(1'b0), .ForwardedSrcAE('0), .ForwardedSrcBE('0), .Funct3M(Funct3M),
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.FlushE(1'b0), .ForwardedSrcAE('0), .ForwardedSrcBE('0), .Funct3M(Funct3M),
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.Funct3E(Funct3E), .IntDivE(1'b0), .FIntDivResultM(FIntDivResultM),
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.Funct3E(Funct3E), .IntDivE(1'b0), .FIntDivResultM(FIntDivResultM),
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.FDivDoneE(FDivDoneE), .IFDivStartE(IFDivStartE));
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.FDivDoneE(FDivDoneE), .IFDivStartE(IFDivStartE));
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