Merge pull request #485 from davidharrishmc/dev

Wally sweep running again, embench sweep across configs

.gitignore

@@ -10,7 +10,7 @@ __pycache__/
 addins/riscv-arch-test/Makefile.include
 addins/riscv-tests/target
 addins/TestFloat-3e/build/Linux-x86_64-GCC/*
-benchmarks/embench/wally*.json
+
 
 #vsim work files to ignore
 transcript
@@ -175,3 +175,6 @@ tests/fp/combined_IF_vectors/IF_vectors/*.tv
 sim/bp-results/*.log
 sim/branch*.log
 /tests/custom/fpga-test-sdc/bin/fpga-test-sdc
+benchmarks/embench/wally*.json
+benchmarks/embench/run*
+sim/cfi.log

addins/riscv-arch-test

@@ -1 +1 @@
-Subproject commit 4eea0a0f0e21f2613a114e45a5ad738e721c4044
+Subproject commit 9f9bdd62d3e37fcd8ad1b1a39d71694ccf1d74f3

benchmarks/embench/Makefile

@@ -3,6 +3,7 @@
 # Compile Embench for Wally
 
 embench_dir = ../../addins/embench-iot
+ARCH=rv32imac_zicsr
 
 all: build 
 run: build size sim
@@ -15,7 +16,7 @@ buildsize: build_speedopt_size build_sizeopt_size
 
 # uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size
 build_speedopt_speed:
-	$(embench_dir)/build_all.py --builddir=bd_speedopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-O2 -nostartfiles" 
+	$(embench_dir)/build_all.py --builddir=bd_speedopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S -march=$(ARCH)" --cflags="-O2 -nostartfiles -march=$(ARCH)" 
 	# remove files not used in embench1.0  When changing to 2.0, restore these files		
 	#rm -rf $(embench_dir)/bd_speedopt_speed/src/md5sum
 	#rm -rf $(embench_dir)/bd_speedopt_speed/src/tarfind
@@ -23,7 +24,7 @@ build_speedopt_speed:
 	find $(embench_dir)/bd_speedopt_speed/ -type f ! -name "*.*" | while read f; do cp "$$f" "$$f.elf"; done
 
 build_sizeopt_speed:
-	$(embench_dir)/build_all.py --builddir=bd_sizeopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S" --cflags="-Os -nostartfiles" 
+	$(embench_dir)/build_all.py --builddir=bd_sizeopt_speed --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/crt0.S -march=$(ARCH)" --cflags="-Os -nostartfiles -march=$(ARCH)" 
 	# remove files not used in embench1.0  When changing to 2.0, restore these files		
 	#rm -rf $(embench_dir)/bd_sizeopt_speed/src/md5sum
 	#rm -rf $(embench_dir)/bd_sizeopt_speed/src/tarfind
@@ -32,10 +33,10 @@ build_sizeopt_speed:
 
 # uses the build_all.py python file to build the tests in addins/embench-iot/bd_speed/ optimized for speed and size
 build_speedopt_size:
-	$(embench_dir)/build_all.py --builddir=bd_speedopt_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S" --cflags="-O2 -msave-restore" --dummy-libs="libgcc libm libc crt0"
+	$(embench_dir)/build_all.py --builddir=bd_speedopt_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S -march=$(ARCH)" --cflags="-O2 -msave-restore -march=$(ARCH)" --dummy-libs="libgcc libm libc crt0"
 
 build_sizeopt_size:
-	$(embench_dir)/build_all.py --builddir=bd_sizeopt_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S" --cflags="-Os -msave-restore" --dummy-libs="libgcc libm libc crt0"
+	$(embench_dir)/build_all.py --builddir=bd_sizeopt_size --arch riscv32 --chip generic --board rv32wallyverilog --ldflags="-nostdlib -nostartfiles ../../../config/riscv32/boards/rv32wallyverilog/startup/dummy.S -march=$(ARCH)" --cflags="-Os -msave-restore -march=$(ARCH)" --dummy-libs="libgcc libm libc crt0"
 
 # builds dependencies, then launches modelsim and finally runs python wrapper script to present results
 sim: modelsim_build_memfile modelsim_run speed

benchmarks/embench/embench_arch_sweep.py

@@ -0,0 +1,86 @@
+#!/usr/bin/python3
+# embench_arch_sweep.py
+# David_Harris@hmc.edu 16 November 2023
+# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
+
+# Run embench on a variety of architectures and collate results
+
+import os
+from datetime import datetime
+import re
+import collections
+
+archs = ["rv32i_zicsr", "rv32im_zicsr", "rv32imc_zicsr", "rv32imc_zba_zbb_zbc_zbs_zicsr", "rv32imafdc_zba_zbb_zbc_zbs_zicsr"]
+
+def calcgeomean(d, arch):
+    progs = ["aha-mont64", "crc32", "cubic", "edn", "huffbench", "matmult-int", "minver", "nbody", "nettle-aes", "nettle-sha256", "nsichneu", "picojpeg", "qrduino", "sglib-combined", "slre", "st", "statemate", "ud", "wikisort"]
+    result = 1.0
+    for p in progs:
+        #val = d[arch][p]
+        val = d[arch].get(p, 1.0)
+        result = result *float(val)
+    result = pow(result, (1.0/float(len(progs))))
+    return result
+
+def tabulate_arch_sweep(directory):
+    for case in ["wallySizeOpt_size", "wallySpeedOpt_speed"]:
+        d = collections.defaultdict(dict)
+        for arch in archs:
+            file = case+"_"+arch+".json"
+            file_path = os.path.join(directory, file)
+            lines = []
+            try:
+                f = open(file_path, "r")
+                lines = f.readlines()
+            except:
+                f.close()
+                #print(file_path+" does not exist")
+            for line in lines:
+                #print("File: "+file+" Line: "+line)
+                #p = re.compile('".*" : .*,')
+                p = r'"([^"]*)" : ([^,\n]+)'
+                match = re.search(p, line)
+                if match:
+                    prog = match.group(1)
+                    result = match.group(2);
+                    d[arch][prog] = result;
+                    #print(match.group(1)+" " + match.group(2))
+            f.close()
+        for arch in [""] + archs:
+            print (arch, end="\t")
+        print("")
+        for prog in d[archs[0]]:
+            print(prog, end="\t")
+            for arch in archs:
+                entry = d[arch].get(prog, "n/a");
+                print (entry, end="\t")
+            print("")
+        print("New geo mean", end="\t")
+        for arch in archs:
+            geomean = calcgeomean(d, arch)
+            print(geomean, end="\t")
+        print("")
+ 
+def run_arch_sweep():
+    # make a folder whose name depends on the date
+    # Get current date
+    current_date = datetime.now()
+    # Format date as a string in the format YYYYMMDD
+    date_string = current_date.strftime('%Y%m%d_%H%M%S')
+    dir = "run_"+date_string
+    # Create a directory with the date string as its name
+    os.mkdir(dir)
+
+    # make a directory with the current date as its name 
+
+    # sweep the runs and save the results in the run directory
+    for arch in archs:
+        os.system("make clean")
+        os.system("make run ARCH="+arch)
+        for res in ["SizeOpt_size", "SizeOpt_speed", "SpeedOpt_size", "SpeedOpt_speed"]:
+            os.system("mv -f wally"+res+".json "+dir+"/wally"+res+"_"+arch+".json")
+    return dir
+
+#directory = run_arch_sweep()
+directory = "run_20231116_071322"
+tabulate_arch_sweep(directory)

config/rv32gc/config.vh

@@ -74,8 +74,8 @@ localparam ICACHE_LINELENINBITS = 32'd512;
 
 // Integer Divider Configuration
 // IDIV_BITSPERCYCLE must be 1, 2, or 4
-localparam IDIV_BITSPERCYCLE = 32'd4;
+localparam IDIV_BITSPERCYCLE = 32'd2;
-localparam IDIV_ON_FPU = 1;
+localparam IDIV_ON_FPU = 0;
 
 // Legal number of PMP entries are 0, 16, or 64
 localparam PMP_ENTRIES = 32'd16;

config/rv64gc/config.vh

@@ -150,7 +150,7 @@ localparam PLIC_SDC_ID = 32'd9;
 localparam BPRED_SUPPORTED = 1;
 localparam BPRED_TYPE = `BP_GSHARE; // BP_GSHARE_BASIC, BP_GLOBAL, BP_GLOBAL_BASIC, BP_TWOBIT
 localparam BPRED_NUM_LHR = 32'd6;
-localparam BPRED_SIZE = 32'd6;
+localparam BPRED_SIZE = 32'd10;
 localparam BTB_SIZE = 32'd10;
 localparam RAS_SIZE = 32'd16;
 

src/ieu/datapath.sv

@@ -131,7 +131,7 @@ module datapath import cvw::*;  #(parameter cvw_t P) (
   if (P.F_SUPPORTED) begin:fpmux
     mux2  #(P.XLEN)  resultmuxM(IEUResultM, FIntResM, FWriteIntM, IFResultM);
     mux2  #(P.XLEN)  cvtresultmuxW(IFResultW, FCvtIntResW, FCvtIntW, IFCvtResultW);
-    if (P.IDIV_ON_FPU) begin
+    if (P.IDIV_ON_FPU & P.F_SUPPORTED) begin
       mux2  #(P.XLEN)  divresultmuxW(MDUResultW, FIntDivResultW, IntDivW, MulDivResultW);
     end else begin 
       assign MulDivResultW = MDUResultW;

src/mdu/mdu.sv

@@ -57,7 +57,7 @@ module mdu import cvw::*;  #(parameter cvw_t P) (
   // Start a divide when a new division instruction is received and the divider isn't already busy or finishing
   // When IDIV_ON_FPU is set, use the FPU divider instead
   // In ZMMUL, with M_SUPPORTED = 0, omit the divider
-  if ((P.IDIV_ON_FPU) || (!P.M_SUPPORTED)) begin:nodiv  
+  if ((P.IDIV_ON_FPU & P.F_SUPPORTED) || (!P.M_SUPPORTED)) begin:nodiv  
     assign QuotM = 0;
     assign RemM = 0;
     assign DivBusyE = 0;

synthDC/Makefile

@@ -24,7 +24,7 @@ export WIDTH ?= 32
 
 time := $(shell date +%F-%H-%M)
 hash := $(shell git rev-parse --short HEAD)
-export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(TECH)_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
+export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
 export SAIFPOWER ?= 0
 
 OLDCONFIGDIR ?= ${WALLY}/config

synthDC/ppa/ppaSynth.py

@@ -85,7 +85,8 @@ if __name__ == '__main__':
 
     ##### Run a sweep for multiple modules/widths based on best delay found in existing syntheses
 	modules = ['adder']
-	widths = [8, 16, 32, 64, 128]
+#	widths = [8, 16, 32, 64, 128]
+	widths = [32]
 	tech = 'sky130'
 	synthsToRun = freqModuleSweep(widths, modules, tech)