Reduced complexity of logic supressing cache operations.

pipelined/src/cache/cache.sv

@@ -35,8 +35,8 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   input logic                   reset,
    // cpu side
   input logic                   CPUBusy,
-  input logic [1:0]             RW,
+  input logic [1:0]             CacheRW,
-  input logic [1:0]             Atomic,
+  input logic [1:0]             CacheAtomic,
   input logic                   FlushCache,
   input logic                   InvalidateCache,
   input logic [11:0]            NextAdr, // virtual address, but we only use the lower 12 bits.
@@ -49,9 +49,6 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   output logic                  CacheMiss,
   output logic                  CacheAccess,
    // lsu control
-  input logic                   IgnoreRequestTLB,
-  input logic                   TrapM, 
-  input logic                   Cacheable,
   input logic                   SelHPTW,
    // Bus fsm interface
   output logic [1:0]            CacheBusRW,
@@ -102,7 +99,6 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   logic                       ResetOrFlushAdr, ResetOrFlushWay;
   logic [NUMWAYS-1:0]         SelectedWay;
   logic [NUMWAYS-1:0]         SetValidWay, ClearValidWay, SetDirtyWay, ClearDirtyWay;
-  logic [1:0]                 CacheRW, CacheAtomic;
   logic [LINELEN-1:0]         ReadDataLine, ReadDataLineCache;
   logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1:0]          WordOffsetAddr;
   logic                       SelBusBuffer;
@@ -209,10 +205,8 @@ module cache #(parameter LINELEN,  NUMLINES,  NUMWAYS, LOGBWPL, WORDLEN, MUXINTE
   /////////////////////////////////////////////////////////////////////////////////////////////
   // Cache FSM
   /////////////////////////////////////////////////////////////////////////////////////////////
-  assign CacheRW = Cacheable ? RW : 2'b00;
-  assign CacheAtomic = Cacheable ? Atomic : 2'b00;
   cachefsm cachefsm(.clk, .reset, .CacheBusRW, .CacheBusAck, 
-		.CacheRW, .CacheAtomic, .CPUBusy, .IgnoreRequestTLB, .TrapM,
+		.CacheRW, .CacheAtomic, .CPUBusy,
  		.CacheHit, .VictimDirty, .CacheStall, .CacheCommitted, 
 		.CacheMiss, .CacheAccess, .SelAdr, 
 		.ClearValid, .ClearDirty, .SetDirty,

pipelined/src/cache/cachefsm.sv

@@ -40,9 +40,6 @@ module cachefsm
    input logic        InvalidateCache,
    // hazard inputs
    input logic        CPUBusy,
-   // interlock fsm
-   input logic        IgnoreRequestTLB,
-   input logic        TrapM,
    // Bus inputs
    input logic        CacheBusAck,
    // dcache internals
@@ -96,17 +93,12 @@ module cachefsm
 					               STATE_FLUSH_WRITE_BACK} statetype;
 
   (* mark_debug = "true" *) statetype CurrState, NextState;
-  logic               IgnoreRequest;
-  assign IgnoreRequest = IgnoreRequestTLB | TrapM;
 
-  // if the command is used in the READY state then the cache needs to be able to supress
+  assign DoFlush = FlushCache;
-  // using both IgnoreRequestTLB and DCacheTrapM.  Otherwise we can just use IgnoreRequestTLB.
-
-  assign DoFlush = FlushCache & ~TrapM; // do NOT suppress flush on DTLBMissM. Does not depend on address translation.
   assign AMO = CacheAtomic[1] & (&CacheRW);
-  assign DoAMO = AMO & ~IgnoreRequest; 
+  assign DoAMO = AMO; 
-  assign DoRead = CacheRW[1] & ~IgnoreRequest; 
+  assign DoRead = CacheRW[1]; 
-  assign DoWrite = CacheRW[0] & ~IgnoreRequest; 
+  assign DoWrite = CacheRW[0]; 
 
   assign DoAnyMiss = (DoAMO | DoRead | DoWrite) & ~CacheHit & ~InvalidateCache;
   assign DoAnyUpdateHit = (DoAMO | DoWrite) & CacheHit;
@@ -129,7 +121,7 @@ module cachefsm
   always_comb begin
     NextState = STATE_READY;
     case (CurrState)
-      STATE_READY: if(IgnoreRequest | InvalidateCache)         NextState = STATE_READY;
+      STATE_READY: if(InvalidateCache)         NextState = STATE_READY;
                    else if(DoFlush)                            NextState = STATE_FLUSH;
       // Delayed LRU update.  Cannot check if victim line is dirty on this cycle.
       // To optimize do the fetch first, then eviction if necessary.
@@ -204,9 +196,7 @@ module cachefsm
 //  assign CacheBusRW[0] = (CurrState == STATE_MISS_FETCH_WDV & CacheBusAck & VictimDirty) |
 //                          (CurrState == STATE_FLUSH_CHECK & VictimDirty);
   // **** can this be simplified?
-  assign SelAdr = (CurrState == STATE_READY & (IgnoreRequestTLB & ~TrapM)) | // Ignore Request is needed on TLB miss.
+  assign SelAdr = (CurrState == STATE_READY & ((AMO | CacheRW[0]) & CacheHit)) | // changes if store delay hazard removed
-                  // use the raw requests as we don't want TrapM in the critical path
-                  (CurrState == STATE_READY & ((AMO | CacheRW[0]) & CacheHit)) | // changes if store delay hazard removed
                   (CurrState == STATE_READY & (DoAnyMiss)) |
                   (CurrState == STATE_MISS_FETCH_WDV) |
                   (CurrState == STATE_MISS_EVICT_DIRTY) |

pipelined/src/ifu/ifu.sv

@@ -212,26 +212,25 @@ module ifu (
       logic [LINELEN-1:0]  FetchBuffer;
       logic [`PA_BITS-1:0] ICacheBusAdr;
       logic                ICacheBusAck;
-      logic [1:0]          CacheBusRW, BusRW;
+      logic [1:0]          CacheBusRW, BusRW, CacheRWF;
-
       
       //assign BusRW = IFURWF & ~{IgnoreRequest, IgnoreRequest} & ~{CacheableF, CacheableF} & ~{SelIROM, SelIROM};
       assign BusRW = ~IgnoreRequest & ~CacheableF & ~SelIROM ? IFURWF : '0;
+      assign CacheRWF = ~IgnoreRequest & CacheableF & ~SelIROM ? IFURWF : '0;
       cache #(.LINELEN(`ICACHE_LINELENINBITS),
               .NUMLINES(`ICACHE_WAYSIZEINBYTES*8/`ICACHE_LINELENINBITS),
               .NUMWAYS(`ICACHE_NUMWAYS), .LOGBWPL(LOGBWPL), .WORDLEN(32), .MUXINTERVAL(16), .DCACHE(0))
-      icache(.clk, .reset, .CPUBusy, .IgnoreRequestTLB(ITLBMissF), .TrapM,
+      icache(.clk, .reset, .CPUBusy,
              .FetchBuffer, .CacheBusAck(ICacheBusAck),
              .CacheBusAdr(ICacheBusAdr), .CacheStall(ICacheStallF), 
              .CacheBusRW,
              .ReadDataWord(ICacheInstrF),
-             .Cacheable(CacheableF),
              .SelHPTW('0),
              .CacheMiss(ICacheMiss), .CacheAccess(ICacheAccess),
              .ByteMask('0), .WordCount('0), .SelBusWord('0),
              .FinalWriteData('0),
-             .RW(IFURWF), 
+             .CacheRW(CacheRWF), 
-             .Atomic('0), .FlushCache('0),
+             .CacheAtomic('0), .FlushCache('0),
              .NextAdr(PCNextFSpill[11:0]),
              .PAdr(PCPF),
              .CacheCommitted(CacheCommittedF), .InvalidateCache(InvalidateICacheM));

pipelined/src/lsu/lsu.sv

@@ -212,6 +212,8 @@ module lsu (
     // The DTIM uses untranslated addresses, so it is not compatible with virtual memory.
     assign DTIMAdr = MemRWM[0] ? IEUAdrExtM[`PA_BITS-1:0] : IEUAdrExtE[`PA_BITS-1:0]; // zero extend or contract to PA_BITS
     assign DTIMMemRWM = SelDTIM & ~IgnoreRequest ? LSURWM : '0;
+    // **** fix ReadDataWordM to be LLEN. ByteMask is wrong length.
+    // **** create config to support DTIM with floating point.
     dtim dtim(.clk, .reset, .ce(~CPUBusy), .MemRWM(DTIMMemRWM),
               .Adr(DTIMAdr),
               .TrapM, .WriteDataM(LSUWriteDataM), 
@@ -237,18 +239,23 @@ module lsu (
       logic [1:0]          CacheBusRW, BusRW;
       localparam integer   LLENPOVERAHBW = `LLEN / `AHBW;
       logic                CacheableOrFlushCacheM;
+      logic [1:0]          CacheRWM, CacheAtomicM;
+      logic                CacheFlushM;
       
       assign BusRW = ~CacheableM & ~IgnoreRequest & ~SelDTIM ? LSURWM : '0;
       assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM;
+      assign CacheRWM = CacheableM & ~IgnoreRequest & ~SelDTIM ? LSURWM : '0;
+      assign CacheAtomicM = CacheableM & ~IgnoreRequest & ~SelDTIM ? LSUAtomicM : '0;
+      assign CacheFlushM  = ~TrapM & FlushDCacheM;
       
       cache #(.LINELEN(`DCACHE_LINELENINBITS), .NUMLINES(`DCACHE_WAYSIZEINBYTES*8/LINELEN),
               .NUMWAYS(`DCACHE_NUMWAYS), .LOGBWPL(LLENLOGBWPL), .WORDLEN(`LLEN), .MUXINTERVAL(`LLEN), .DCACHE(1)) dcache(
-        .clk, .reset, .CPUBusy, .SelBusWord, .RW(LSURWM), .Atomic(LSUAtomicM),
+        .clk, .reset, .CPUBusy, .SelBusWord, .CacheRW(CacheRWM), .CacheAtomic(CacheAtomicM),
-        .FlushCache(FlushDCacheM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), 
+        .FlushCache(CacheFlushM), .NextAdr(IEUAdrE[11:0]), .PAdr(PAdrM), 
         .ByteMask(ByteMaskM), .WordCount(WordCount[AHBWLOGBWPL-1:AHBWLOGBWPL-LLENLOGBWPL]),
-        .FinalWriteData(LSUWriteDataM), .Cacheable(CacheableOrFlushCacheM), .SelHPTW,
+        .FinalWriteData(LSUWriteDataM), .SelHPTW,
         .CacheStall(DCacheStallM), .CacheMiss(DCacheMiss), .CacheAccess(DCacheAccess),
-        .IgnoreRequestTLB, .TrapM, .CacheCommitted(DCacheCommittedM), 
+        .CacheCommitted(DCacheCommittedM), 
         .CacheBusAdr(DCacheBusAdr), .ReadDataWord(DCacheReadDataWordM), 
         .FetchBuffer, .CacheBusRW, 
         .CacheBusAck(DCacheBusAck), .InvalidateCache(1'b0));
@@ -264,6 +271,8 @@ module lsu (
 
       // FetchBuffer[`AHBW-1:0] needs to be duplicated LLENPOVERAHBW times.
       // DTIMReadDataWordM should be increased to LLEN.
+      // *** DTIMReadDataWordM should be LLEN
+      // pma should generate expection for LLEN read to periph.
       mux3 #(`LLEN) UnCachedDataMux(.d0(DCacheReadDataWordM), .d1({LLENPOVERAHBW{FetchBuffer[`XLEN-1:0]}}),
                                     .d2({{`LLEN-`XLEN{1'b0}}, DTIMReadDataWordM[`XLEN-1:0]}),
                                     .s({SelDTIM, ~(CacheableOrFlushCacheM)}), .y(ReadDataWordMuxM));

pipelined/src/lsu/lsuvirtmen.sv

@@ -75,6 +75,9 @@ module lsuvirtmem(
   logic                       DTLBMissOrDAFaultM, DTLBMissOrDAFaultNoTrapM;
   logic                       SelHPTWAdr;
 
+  /// **** move to HPTW
+  // **** rename to walker mux?
+  // move all the muxes to walkermux and instantiate these in lsu under virtmem_supported.
   assign ITLBMissOrDAFaultF = ITLBMissF | (`HPTW_WRITES_SUPPORTED & InstrDAPageFaultF);
   assign DTLBMissOrDAFaultM = DTLBMissM | (`HPTW_WRITES_SUPPORTED & DataDAPageFaultM);  
   assign ITLBMissOrDAFaultNoTrapF = ITLBMissOrDAFaultF & ~TrapM;