Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity

Made Q4.k interface to fgen2/4 consistent

Browse Source
This commit is contained in:
David Harris 2023-01-01 15:06:32 -08:00
parent 3d5acc7c2a
commit 43f45c62a6
2 changed files with 6 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
pipelined/src/fpu/fdivsqrt/fdivsqrtfgen2.sv
View File

@ -32,25 +32,18 @@
module fdivsqrtfgen2 ( module fdivsqrtfgen2 (
input logic up, uz, input logic up, uz,
input logic [`DIVb+1:0] C, input logic [`DIVb+3:0] C, U, UM,
input logic [`DIVb:0] U, UM,
output logic [`DIVb+3:0] F output logic [`DIVb+3:0] F
); );
logic [`DIVb+3:0] FP, FN, FZ; logic [`DIVb+3:0] FP, FN, FZ;
logic [`DIVb+3:0] UExt, UMExt, CExt;
assign UExt = {3'b0, U};
assign UMExt = {3'b0, UM};
assign CExt = {2'b11, C}; // extend C from Q2.k to Q4.k
// Generate for both positive and negative bits // Generate for both positive and negative bits
assign FP = ~(UExt << 1) & CExt; assign FP = ~(U << 1) & C;
assign FN = (UMExt << 1) | (CExt & ~(CExt << 2)); assign FN = (UM << 1) | (C & ~(C << 2));
assign FZ = '0; assign FZ = '0;
// Choose which adder input will be used
always_comb always_comb // Choose which adder input will be used
if (up) F = FP; if (up) F = FP;
else if (uz) F = FZ; else if (uz) F = FZ;
else F = FN; else F = FN;

4
pipelined/src/fpu/fdivsqrt/fdivsqrtstage2.sv
View File

@ -61,8 +61,8 @@ module fdivsqrtstage2 (
// 0001 = -2 // 0001 = -2
fdivsqrtqsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], up, uz, un); fdivsqrtqsel2 qsel2(WS[`DIVb+3:`DIVb], WC[`DIVb+3:`DIVb], up, uz, un);
// Sqrt F generation // Sqrt F generation. Extend C, U, UM to Q4.k
fdivsqrtfgen2 fgen2(.up, .uz, .C(CNext), .U, .UM, .F); fdivsqrtfgen2 fgen2(.up, .uz, .C({2'b11, CNext}), .U({3'b000, U}), .UM({3'b000, UM}), .F);
// Divisor multiple // Divisor multiple
always_comb always_comb