Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

.gitignore

@@ -103,3 +103,4 @@ pipelined/config/rv64ic_noMulDiv
 pipelined/config/rv64ic_noPriv
 pipelined/config/rv64ic_orig
 synthDC/Summary.csv
+pipelined/srt/exptestgen

pipelined/config/rv64gc/wally-config.vh

@@ -131,8 +131,8 @@
 `define PLIC_GPIO_ID 3
 `define PLIC_UART_ID 10
 
-`define TWO_BIT_PRELOAD "../config/rv64ic/twoBitPredictor.txt"
+`define TWO_BIT_PRELOAD "../config/shared/twoBitPredictor.txt"
-`define BTB_PRELOAD "../config/rv64ic/BTBPredictor.txt"
+`define BTB_PRELOAD "../config/shared/BTBPredictor.txt"
 `define BPRED_ENABLED 1
 `define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
 `define TESTSBP 0

pipelined/src/ifu/bpred.sv

@@ -116,7 +116,7 @@ module bpred
 
   // this predictor will have two pieces of data,
   // 1) A direction (1 = Taken, 0 = Not Taken)
-  // 2) Any information which is necessary for the predictor to built it's next state.
+  // 2) Any information which is necessary for the predictor to build its next state.
   // For a 2 bit table this is the prediction count.
 
   assign SelBPPredF = ((BPInstrClassF[0] & BPPredF[1] & BTBValidF) | 

pipelined/srt/lint-srt

@@ -1,2 +1,2 @@
 verilator --lint-only --top-module srt srt.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv
-verilator --lint-only --top-module testbench testbench.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv ../src/fpu/unpacking.sv
+verilator --lint-only --top-module testbench testbench.sv -I../config/rv64gc -I../config/shared ../src/generic/*.sv ../src/generic/flop/*.sv ../src/fpu/unpack.sv

pipelined/srt/srt.do

@@ -17,7 +17,7 @@ if [file exists work] {
 }
 vlib work
 
-vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/fpu/unpacking.sv
+vlog +incdir+../config/rv64gc +incdir+../config/shared srt.sv testbench.sv ../src/generic/flop/flop*.sv ../src/generic/mux.sv ../src/fpu/unpack.sv
 vopt +acc work.testbench -o workopt 
 vsim workopt
 

pipelined/srt/srt.sv

@@ -92,6 +92,7 @@ module srtpostproc #(parameter N=52) (
   output [N-1:0] Quot
 );
 
+  // replace with on-the-fly conversion
   //assign Quot = rp - rm;
   finaladd finaladd(rp, rm, Quot); 
 endmodule

pipelined/srt/testbench.sv

@@ -1,7 +1,7 @@
 /////////////
-// counter //
+// divcounter //
 /////////////
-module counter(input  logic clk, 
+module divcounter(input  logic clk, 
                input  logic req, 
                output logic done);
  
@@ -36,6 +36,9 @@ endmodule
 //////////
 // testbench //
 //////////
+
+/* verilator lint_off STMTDLY */
+/* verilator lint_off INFINITELOOP */
 module testbench;
   logic         clk;
   logic        req;
@@ -83,11 +86,11 @@ module testbench;
 
   // Unpacker
   // Note: BiasE will probably get taken out eventually
-  unpack unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), .FOpCtrlE(3'b0),
+  unpack unpack(.X({1'b1,a[62:0]}), .Y({1'b1,b[62:0]}), .Z(64'b0), .FmtE(1'b1), 
                   .XSgnE(XSgnE), .YSgnE(YSgnE), .ZSgnE(ZSgnE), .XExpE(XExpE), .YExpE(YExpE), .ZExpE(ZExpE),
                   .XManE(XManE), .YManE(YManE), .ZManE(ZManE), .XNormE(XNormE), .XNaNE(XNaNE), .YNaNE(YNaNE), .ZNaNE(ZNaNE),
                   .XSNaNE(XSNaNE), .YSNaNE(YSNaNE), .ZSNaNE(ZSNaNE), .XDenormE(XDenormE), .YDenormE(YDenormE), .ZDenormE(ZDenormE),
-                  .XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE), .BiasE(BiasE),
+                  .XZeroE(XZeroE), .YZeroE(YZeroE), .ZZeroE(ZZeroE), 
                   .XInfE(XInfE), .YInfE(YInfE), .ZInfE(ZInfE), .XExpMaxE(XExpMaxE));
 
   // Divider
@@ -101,8 +104,8 @@ module testbench;
 
   assign result = {1'b0, e, r};
 
-  // Counter
+  // Divcounter
-  counter counter(clk, req, done);
+  divcounter divcounter(clk, req, done);
 
 
     initial
@@ -123,7 +126,7 @@ module testbench;
       a = Vec[`mema];
       b = Vec[`memb];
       nextr = Vec[`memr];
-      req <= #5 1;
+      req = #5 1;
     end
   
   // Apply directed test vectors read from file.
@@ -132,7 +135,7 @@ module testbench;
     begin
       if (done) 
 	begin
-	  req <= #5 1;
+	  req = #5 1;
     diffp = correctr - result;
     diffn = result - correctr;
 	  if (($signed(diffn) > 1) | ($signed(diffp) > 1)) // check if accurate to 1 ulp
@@ -152,7 +155,7 @@ module testbench;
 	end
       if (req) 
 	begin
-	  req <= #5 0;
+	  req = #5 0;
 	  correctr = nextr;
     $display("pre increment");
 	  testnum = testnum+1;
@@ -167,3 +170,5 @@ module testbench;
  
 endmodule
  
+/* verilator lint_on STMTDLY  */
+/* verilator lint_on INFINITELOOP  */

pipelined/testbench/testbench.sv

@@ -329,8 +329,18 @@ logic [3:0] dummy;
   // initialize the branch predictor
   if (`BPRED_ENABLED == 1)
     initial begin
-      $readmemb(`TWO_BIT_PRELOAD, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem);
+      integer adrindex;
-      $readmemb(`BTB_PRELOAD, dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem);    
+      
+      // Initializing all zeroes into the branch predictor memory.
+      for(adrindex = 0; adrindex < 1024; adrindex++) begin
+        force dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex] = 0;
+        force dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex] = 0;
+      end 
+      #1;
+      for(adrindex = 0; adrindex < 1024; adrindex++) begin
+        release dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PHT.mem[adrindex];
+        release dut.core.ifu.bpred.bpred.TargetPredictor.memory.mem[adrindex];
+      end
     end
 endmodule
 

pipelined/testbench/tests.vh

@@ -962,7 +962,7 @@ string imperas32f[] = '{
     "rv64i_m/I/andi-01", "6010",
     "rv64i_m/I/auipc-01", "2010",
     "rv64i_m/I/beq-01", "47010",
-    "rv64i_m/I/bge-01", "46010",
+    "rv64i_m/I/bge-01", "47010",
     "rv64i_m/I/bgeu-01", "56010",
     "rv64i_m/I/blt-01", "4d010",
     "rv64i_m/I/bltu-01", "57010",