From 4365c99b5248571c6aa3b3b5b9531f0cb62c3db6 Mon Sep 17 00:00:00 2001 From: David Harris Date: Thu, 15 Dec 2022 10:56:18 -0800 Subject: [PATCH] Refactored stalls and flushes, including FDIV flush with FlushE --- pipelined/regression/regression-wally | 2 +- pipelined/regression/wkdir/.gitignore | 4 ---- pipelined/src/fpu/fdivsqrt/fdivsqrt.sv | 4 ++-- pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv | 4 ++-- pipelined/src/fpu/fpu.sv | 4 ++-- pipelined/src/hazard/hazard.sv | 8 ++++---- pipelined/src/wally/wallypipelinedcore.sv | 2 +- 7 files changed, 12 insertions(+), 16 deletions(-) delete mode 100644 pipelined/regression/wkdir/.gitignore diff --git a/pipelined/regression/regression-wally b/pipelined/regression/regression-wally index 17f255251..aae1b5415 100755 --- a/pipelined/regression/regression-wally +++ b/pipelined/regression/regression-wally @@ -161,9 +161,9 @@ def main(): os.mkdir("logs") #print(os.getcwd()) #print(regressionDir) - shutil.rmtree("wkdir") except: pass + shutil.rmtree("wkdir") os.mkdir("wkdir") if '-makeTests' in sys.argv: diff --git a/pipelined/regression/wkdir/.gitignore b/pipelined/regression/wkdir/.gitignore deleted file mode 100644 index 5e7d2734c..000000000 --- a/pipelined/regression/wkdir/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -# Ignore everything in this directory -* -# Except this file -!.gitignore diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv index 2c1aa7ed3..881def027 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrt.sv @@ -43,7 +43,7 @@ module fdivsqrt( input logic FDivStartE, IDivStartE, input logic StallM, input logic StallE, - input logic TrapM, + input logic FlushE, input logic SqrtE, SqrtM, input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // *** these are the src outputs before the mux choosing between them and PCE to put in srcA/B input logic [2:0] Funct3E, Funct3M, @@ -77,7 +77,7 @@ module fdivsqrt( .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E); fdivsqrtfsm fdivsqrtfsm( .clk, .reset, .FmtE, .XsE, .SqrtE, - .FDivBusyE, .FDivStartE, .IDivStartE, .IFDivStartE, .FDivDoneE, .StallE, .StallM, .TrapM, /*.DivDone, */ .XZeroE, .YZeroE, + .FDivBusyE, .FDivStartE, .IDivStartE, .IFDivStartE, .FDivDoneE, .StallE, .StallM, .FlushE, /*.DivDone, */ .XZeroE, .YZeroE, .XNaNE, .YNaNE, .MDUE, .n, .XInfE, .YInfE, .WZero, .SpecialCaseM); fdivsqrtiter fdivsqrtiter( diff --git a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv index dc9b1efca..175f356b7 100644 --- a/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv +++ b/pipelined/src/fpu/fdivsqrt/fdivsqrtfsm.sv @@ -42,7 +42,7 @@ module fdivsqrtfsm( input logic SqrtE, input logic StallE, input logic StallM, - input logic TrapM, + input logic FlushE, input logic WZero, input logic MDUE, input logic [`DIVBLEN:0] n, @@ -107,7 +107,7 @@ module fdivsqrtfsm( /* verilator lint_on WIDTH */ always_ff @(posedge clk) begin - if (reset | TrapM) begin + if (reset | FlushE) begin state <= #1 IDLE; end else if (IFDivStartE) begin step <= cycles; diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv index 10fa4d70e..65992a26e 100755 --- a/pipelined/src/fpu/fpu.sv +++ b/pipelined/src/fpu/fpu.sv @@ -38,7 +38,7 @@ module fpu ( input logic [`FLEN-1:0] ReadDataW, // Read data (from LSU) input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // Integer input (from IEU) input logic StallE, StallM, StallW, // stall signals (from HZU) - input logic TrapM, + //input logic TrapM, input logic FlushE, FlushM, FlushW, // flush signals (from HZU) input logic [4:0] RdM, RdW, // which FP register to write to (from IEU) input logic [1:0] STATUS_FS, // Is floating-point enabled? (From privileged unit) @@ -268,7 +268,7 @@ module fpu ( fdivsqrt fdivsqrt(.clk, .reset, .FmtE, .XmE, .YmE, .XeE, .YeE, .SqrtE(OpCtrlE[0]), .SqrtM(OpCtrlM[0]), .XInfE, .YInfE, .XZeroE, .YZeroE, .XNaNE, .YNaNE, .FDivStartE, .IDivStartE, .XsE, .ForwardedSrcAE, .ForwardedSrcBE, .Funct3E, .Funct3M, .MDUE, .W64E, - .StallE, .StallM, .TrapM, .DivSM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .QeM, + .StallE, .StallM, .FlushE, .DivSM, .FDivBusyE, .IFDivStartE, .FDivDoneE, .QeM, .QmM, .FPIntDivResultM /*, .DivDone(DivDoneM) */); // diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv index 50c077f60..0b7cbc644 100644 --- a/pipelined/src/hazard/hazard.sv +++ b/pipelined/src/hazard/hazard.sv @@ -62,7 +62,7 @@ module hazard( // If any stages are stalled, the first stage that isn't stalled must flush. assign FlushDCause = TrapM | RetM | BPPredWrongE | CSRWriteFenceM; - assign FlushECause = TrapM | RetM | BPPredWrongE | CSRWriteFenceM; + assign FlushECause = TrapM | RetM | (BPPredWrongE & ~(DivBusyE | FDivBusyE)) | CSRWriteFenceM; assign FlushMCause = TrapM | RetM | CSRWriteFenceM; // on Trap the memory stage should be flushed going into the W stage, // except if the instruction causing the Trap is an ecall or ebreak. @@ -70,11 +70,11 @@ module hazard( assign StallFCause = '0; // stall in decode if instruction is a load/mul/csr dependent on previous - assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | FStallD) & ~(FlushDCause); - assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM | CSRWriteFenceM); // *** can we move to decode stage (KP?) + assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FCvtIntStallD | FStallD) & ~FlushDCause; + assign StallECause = (DivBusyE | FDivBusyE) & ~FlushECause; // WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM)); - assign StallWCause = ((IFUStallF | LSUStallM) & ~TrapM); // | (FDivBusyE & ~TrapM & ~IntPendingM); + assign StallWCause = (IFUStallF | LSUStallM) & ~TrapM; assign #1 StallF = StallFCause | StallD; assign #1 StallD = StallDCause | StallE; diff --git a/pipelined/src/wally/wallypipelinedcore.sv b/pipelined/src/wally/wallypipelinedcore.sv index a07809343..c61b5e1a9 100644 --- a/pipelined/src/wally/wallypipelinedcore.sv +++ b/pipelined/src/wally/wallypipelinedcore.sv @@ -390,7 +390,7 @@ module wallypipelinedcore ( .ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory .ForwardedSrcAE, // Integer input being processed (from IEU) .StallE, .StallM, .StallW, // stall signals from HZU - .TrapM, + //.TrapM, .FlushE, .FlushM, .FlushW, // flush signals from HZU .RdM, .RdW, // which FP register to write to (from IEU) .STATUS_FS, // is floating-point enabled?