mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
update busybear testbench to conform to new structure
aaaaaaaaaaaaaaaaaahhhh so many changes also the testbench now uses another internal signal, which I don't like, but I can't think of a better option rn
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@ -57,7 +57,19 @@
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// Address space
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// Address space
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`define RESET_VECTOR 64'h0000000000001000
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`define RESET_VECTOR 64'h0000000000001000
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// Bus Interface
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// Peripheral Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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`define TIMBASE 64'h0000000080000000
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`define TIMRANGE 64'h000000000007FFFF
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`define CLINTBASE 64'h0000000002000000
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`define CLINTRANGE 64'h000000000000FFFF
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`define GPIOBASE 64'h0000000010012000
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`define GPIORANGE 64'h00000000000000FF
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`define UARTBASE 64'h0000000010000000
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`define UARTRANGE 64'h0000000000000007
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// Bus Interface width
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`define AHBW 64
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`define AHBW 64
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// Test modes
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// Test modes
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@ -26,7 +26,7 @@ vlib work
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# suppress spurious warnngs about
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# suppress spurious warnngs about
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# "Extra checking for conflicts with always_comb done at vopt time"
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# "Extra checking for conflicts with always_comb done at vopt time"
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# because vsim will run vopt
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# because vsim will run vopt
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vlog +incdir+../config/busybear ../testbench/*.sv ../src/*.sv -suppress 2583
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vlog +incdir+../config/busybear ../testbench/*.sv ../src/*/*.sv -suppress 2583
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# start and run simulation
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# start and run simulation
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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# remove +acc flag for faster sim during regressions if there is no need to access internal signals
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@ -50,12 +50,11 @@ add wave /testbench_busybear/lastPC2
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add wave -divider
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add wave -divider
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# registers!
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# registers!
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add wave -hex /testbench_busybear/rfExpected
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add wave -hex /testbench_busybear/rfExpected
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add wave -hex /testbench_busybear/MemRWM[0]
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add wave -hex /testbench_busybear/HWRITE
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add wave -hex /testbench_busybear/MemRWM[1]
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add wave -hex /testbench_busybear/dut/MemRWM[1]
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add wave -hex /testbench_busybear/ByteMaskM
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add wave -hex /testbench_busybear/HWDATA
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add wave -hex /testbench_busybear/WriteDataM
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add wave -hex /testbench_busybear/HRDATA
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add wave -hex /testbench_busybear/ReadDataM
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add wave -hex /testbench_busybear/HADDR
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add wave -hex /testbench_busybear/DataAdrM
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[1]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[1]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[2]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[2]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[3]
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add wave -hex /testbench_busybear/dut/ieu/dp/regf/rf[3]
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@ -3,15 +3,12 @@
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module testbench_busybear();
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module testbench_busybear();
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logic clk, reset;
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logic clk, reset;
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logic [`XLEN-1:0] WriteDataM, DataAdrM;
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logic [1:0] MemRWM;
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logic [31:0] GPIOPinsIn;
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logic [31:0] GPIOPinsIn;
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logic [31:0] GPIOPinsOut, GPIOPinsEn;
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logic [31:0] GPIOPinsOut, GPIOPinsEn;
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// instantiate device to be tested
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// instantiate device to be tested
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logic [`XLEN-1:0] PCF, ReadDataM;
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logic [`XLEN-1:0] PCF;
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logic [31:0] InstrF;
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logic [31:0] InstrF;
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logic [7:0] ByteMaskM;
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logic InstrAccessFaultF, DataAccessFaultM;
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logic InstrAccessFaultF, DataAccessFaultM;
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logic TimerIntM = 0, SwIntM = 0; // from CLINT
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logic TimerIntM = 0, SwIntM = 0; // from CLINT
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logic ExtIntM = 0; // not yet connected
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logic ExtIntM = 0; // not yet connected
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@ -26,6 +23,7 @@ module testbench_busybear();
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logic [3:0] HPROT;
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logic [3:0] HPROT;
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logic [1:0] HTRANS;
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logic [1:0] HTRANS;
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logic HMASTLOCK;
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logic HMASTLOCK;
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logic HCLK, HRESETn;
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assign GPIOPinsIn = 0;
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assign GPIOPinsIn = 0;
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assign UARTSin = 1;
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assign UARTSin = 1;
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@ -115,40 +113,37 @@ module testbench_busybear();
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logic [`XLEN-1:0] readAdrExpected;
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logic [`XLEN-1:0] readAdrExpected;
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// this might need to change
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// this might need to change
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always @(MemRWM[1] or DataAdrM) begin
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always @(dut.MemRWM[1] or HADDR) begin
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if (MemRWM[1]) begin
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if (dut.MemRWM[1]) begin
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if($feof(data_file_memR)) begin
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if($feof(data_file_memR)) begin
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$display("no more memR data to read");
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$display("no more memR data to read");
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$stop;
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$stop;
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end
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end
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scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected);
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scan_file_memR = $fscanf(data_file_memR, "%x\n", readAdrExpected);
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scan_file_memR = $fscanf(data_file_memR, "%x\n", ReadDataM);
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scan_file_memR = $fscanf(data_file_memR, "%x\n", HRDATA);
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if (DataAdrM != readAdrExpected) begin
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#1;
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$display("%t ps, instr %0d: DataAdrM does not equal readAdrExpected: %x, %x", $time, instrs, DataAdrM, readAdrExpected);
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if (HADDR != readAdrExpected) begin
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$display("%t ps, instr %0d: HADDR does not equal readAdrExpected: %x, %x", $time, instrs, HADDR, readAdrExpected);
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end
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end
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end
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end
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end
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end
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logic [`XLEN-1:0] writeDataExpected, writeAdrExpected;
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logic [`XLEN-1:0] writeDataExpected, writeAdrExpected;
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// this might need to change
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// this might need to change
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always @(WriteDataM or DataAdrM or ByteMaskM) begin
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always @(HWDATA or HADDR or HSIZE) begin
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#1;
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#1;
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if (MemRWM[0]) begin
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if (HWRITE) begin
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if($feof(data_file_memW)) begin
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if($feof(data_file_memW)) begin
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$display("no more memW data to read");
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$display("no more memW data to read");
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$stop;
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$stop;
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end
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end
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scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected);
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scan_file_memW = $fscanf(data_file_memW, "%x\n", writeDataExpected);
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scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected);
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scan_file_memW = $fscanf(data_file_memW, "%x\n", writeAdrExpected);
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for(int i=0; i<8; i++) begin
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if (writeDataExpected != HWDATA) begin
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if (ByteMaskM[i]) begin
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$display("%t ps, instr %0d: HWDATA does not equal writeDataExpected: %x, %x", $time, instrs, HWDATA, writeDataExpected);
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if (writeDataExpected[i*8+7 -: 8] != WriteDataM[i*8+7 -: 8]) begin
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$display("%t ps, instr %0d: WriteDataM does not equal writeDataExpected: %x, %x", $time, instrs, WriteDataM, writeDataExpected);
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end
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end
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end
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end
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if (writeAdrExpected != DataAdrM) begin
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if (writeAdrExpected != HADDR) begin
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$display("%t ps, instr %0d: DataAdrM does not equal writeAdrExpected: %x, %x", $time, instrs, DataAdrM, writeAdrExpected);
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$display("%t ps, instr %0d: HADDR does not equal writeAdrExpected: %x, %x", $time, instrs, HADDR, writeAdrExpected);
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end
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end
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end
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end
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end
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end
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