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Switch to use RV64IC for the benchmarks.

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Still not working correctly with the icache.

instr
addr   correct   got
This commit is contained in:
Ross Thompson 2021-04-07 19:12:43 -05:00
parent c91436d3b7
commit 4322694f7a
11 changed files with 10165 additions and 56 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
testsBP/crt0/Makefile
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@ -3,10 +3,13 @@ TARGET := $(TARGETDIR)/start
ROOT := .. ROOT := ..
LIBRARY_DIRS := LIBRARY_DIRS :=
LIBRARY_FILES := LIBRARY_FILES :=
LINK_FLAGS := -nostartfiles
AFLAGS =-march=rv64ifd -W MARCH :=-march=rv64ic
CFLAGS =-march=rv64ifd -mcmodel=medany MABI :=-mabi=lp64
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles
AFLAGS =$(MARCH) $(MABI) -march=rv64ic -mabi=lp64 -W
CFLAGS =$(MARCH) $(MABI) -march=rv64ic -mabi=lp64 -mcmodel=medany
AS=riscv64-unknown-elf-as AS=riscv64-unknown-elf-as
CC=riscv64-unknown-elf-gcc CC=riscv64-unknown-elf-gcc
AR=riscv64-unknown-elf-ar AR=riscv64-unknown-elf-ar

3
testsBP/mibench_qsort/LICENSE Normal file
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@ -0,0 +1,3 @@
Matt wrote this using STL.
It is GPL'ed.

19
testsBP/mibench_qsort/Makefile Normal file
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@ -0,0 +1,19 @@
TARGETDIR := qsort
TARGET := $(TARGETDIR)/$(TARGETDIR).elf
ROOT := ..
LIBRARY_DIRS := ${ROOT}/crt0
LIBRARY_FILES := crt0
MARCH :=-march=rv64ic
MABI :=-mabi=lp64
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align
CC=riscv64-unknown-elf-gcc
DA=riscv64-unknown-elf-objdump -d
include $(ROOT)/makefile.inc

10038
testsBP/mibench_qsort/qsort_small.c Normal file
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File diff suppressed because it is too large Load Diff

8
testsBP/sieve/Makefile
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@ -3,9 +3,13 @@ TARGET := $(TARGETDIR)/$(TARGETDIR).elf
ROOT := .. ROOT := ..
LIBRARY_DIRS := ${ROOT}/crt0 LIBRARY_DIRS := ${ROOT}/crt0
LIBRARY_FILES := crt0 LIBRARY_FILES := crt0
LINK_FLAGS := -nostartfiles -Wl,-Map=$(TARGET).map
CFLAGS =-march=rv64ifd -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align MARCH :=-march=rv64ic
MABI :=-mabi=lp64
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align
CC=riscv64-unknown-elf-gcc CC=riscv64-unknown-elf-gcc
DA=riscv64-unknown-elf-objdump -d DA=riscv64-unknown-elf-objdump -d

7
testsBP/simple/Makefile
View File

@ -3,9 +3,12 @@ TARGET := $(TARGETDIR)/$(TARGETDIR).elf
ROOT := .. ROOT := ..
LIBRARY_DIRS := ${ROOT}/crt0 LIBRARY_DIRS := ${ROOT}/crt0
LIBRARY_FILES := crt0 LIBRARY_FILES := crt0
LINK_FLAGS := -nostartfiles -Wl,-Map=$(TARGET).map
CFLAGS =-march=rv64ifd -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align MARCH :=-march=rv64ic
MABI :=-mabi=lp64
LINK_FLAGS :=$(MARCH) $(MABI) -nostartfiles -Wl,-Map=$(TARGET).map
CFLAGS =$(MARCH) $(MABI) -Wa,-alhs -Wa,-L -mcmodel=medany -mstrict-align
CC=riscv64-unknown-elf-gcc CC=riscv64-unknown-elf-gcc
DA=riscv64-unknown-elf-objdump -d DA=riscv64-unknown-elf-objdump -d

19
testsBP/simple/lbu_test.s Normal file
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@ -0,0 +1,19 @@
.section .text
.global lbu_test
.type lbu_test, @function
lbu_test:
li t0, 0x80000
lbu t1, 0(t0)
pass:
li a0, 0
done:
ret
fail:
li a0, -1
j done

4
wally-pipelined/bin/exe2memfile0.pl
View File

@ -18,11 +18,7 @@ my $maxaddress = 0;
STDOUT->autoflush(1); STDOUT->autoflush(1);
# *** Ross Thompson I think there is a bug here needs to be +1 # *** Ross Thompson I think there is a bug here needs to be +1
<<<<<<< HEAD
print ("Processing $#ARGV memfiles: \n"); print ("Processing $#ARGV memfiles: \n");
=======
print ("Processing $#ARGV memfiles: ");
>>>>>>> icache_bp_bug
my $frac = $#ARGV/10; my $frac = $#ARGV/10;
for(my $i=0; $i<=$#ARGV; $i++) { for(my $i=0; $i<=$#ARGV; $i++) {
if ($i < 10 || $i % $frac == 0) { print ("$i ") }; if ($i < 10 || $i % $frac == 0) { print ("$i ") };

85
wally-pipelined/regression/wave.do
View File

@ -59,29 +59,30 @@ add wave -noupdate -group Bpred -expand -group direction -group other /testbench
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/TargetWrongE add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/TargetWrongE
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/FallThroughWrongE add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/FallThroughWrongE
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionPCWrongE add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PredictionPCWrongE
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/BPPredClassNonCFIWrongE
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PCSrcE
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/BPPredWrongE add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/BPPredWrongE
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/InstrClassE add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/InstrClassE
add wave -noupdate -group Bpred -expand -group {bp wrong} -divider pcs add wave -noupdate -group Bpred -expand -group {bp wrong} -divider pcs
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PCD add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/hart/ifu/bpred/PCD
add wave -noupdate -group Bpred -expand -group BTB -divider Update add wave -noupdate -group Bpred -group BTB -divider Update
add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateEN add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateEN
add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePC add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePC
add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/InstrClassE add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/InstrClassE
add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateTarget add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdateTarget
add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePCIndexQ add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/UpdatePCIndexQ
add wave -noupdate -group Bpred -expand -group BTB -divider Lookup add wave -noupdate -group Bpred -group BTB -divider Lookup
add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/TargetPC add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/TargetPC
add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/InstrClass add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/InstrClass
add wave -noupdate -group Bpred -expand -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/Valid add wave -noupdate -group Bpred -group BTB /testbench/dut/hart/ifu/bpred/TargetPredictor/Valid
add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/BPPredWrongE add wave -noupdate -group Bpred /testbench/dut/hart/ifu/bpred/BPPredWrongE
add wave -noupdate -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/pop add wave -noupdate -group Bpred -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/pop
add wave -noupdate -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/push add wave -noupdate -group Bpred -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/push
add wave -noupdate -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/pushPC add wave -noupdate -group Bpred -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/pushPC
add wave -noupdate -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/PtrD add wave -noupdate -group Bpred -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/PtrD
add wave -noupdate -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/PtrQ add wave -noupdate -group Bpred -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/PtrQ
add wave -noupdate -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/memory add wave -noupdate -group Bpred -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/memory
add wave -noupdate -group Bpred -expand -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/popPC add wave -noupdate -group Bpred -group RAS /testbench/dut/hart/ifu/bpred/RASPredictor/popPC
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrF
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrD
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrE
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/hart/ifu/InstrM
@ -94,25 +95,26 @@ add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PCNext1F
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/SelBPPredF
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/BPPredWrongE
add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM add wave -noupdate -group {PCNext Generation} /testbench/dut/hart/ifu/PrivilegedChangePCM
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ifu/InstrD add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ifu/InstrD
add wave -noupdate -group {Decode Stage} /testbench/InstrDName add wave -noupdate -expand -group {Decode Stage} /testbench/InstrDName
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/c/RegWriteD
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/RdD
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs1D
add wave -noupdate -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ieu/dp/Rs2D
add wave -noupdate -group RegFile -expand /testbench/dut/hart/ieu/dp/regf/rf add wave -noupdate -expand -group {Decode Stage} /testbench/dut/hart/ifu/ic/DelaySideF
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a1 add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rf
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a2 add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a1
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/a3 add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a2
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1 add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/a3
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2 add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd1
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/we3 add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/rd2
add wave -noupdate -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3 add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/we3
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW add wave -noupdate -expand -group RegFile /testbench/dut/hart/ieu/dp/regf/wd3
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ALUResultW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ReadDataW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/CSRReadValW
add wave -noupdate -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultSrcW
add wave -noupdate -expand -group RegFile -group {write regfile mux} /testbench/dut/hart/ieu/dp/ResultW
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/a
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/b
add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol add wave -noupdate -expand -group alu /testbench/dut/hart/ieu/dp/alu/alucontrol
@ -186,8 +188,8 @@ add wave -noupdate /testbench/dut/imem/InstrF
add wave -noupdate /testbench/dut/InstrF add wave -noupdate /testbench/dut/InstrF
add wave -noupdate /testbench/dut/InstrF add wave -noupdate /testbench/dut/InstrF
add wave -noupdate -divider {New Divider} add wave -noupdate -divider {New Divider}
add wave -noupdate /testbench/dut/hart/ifu/ic/InDataF
add wave -noupdate /testbench/dut/hart/ifu/InstrInF add wave -noupdate /testbench/dut/hart/ifu/InstrInF
add wave -noupdate /testbench/dut/hart/ifu/rd2
add wave -noupdate /testbench/dut/hart/InstrRData add wave -noupdate /testbench/dut/hart/InstrRData
add wave -noupdate /testbench/dut/hart/rd2 add wave -noupdate /testbench/dut/hart/rd2
add wave -noupdate /testbench/dut/hart/ebu/InstrRData add wave -noupdate /testbench/dut/hart/ebu/InstrRData
@ -217,9 +219,10 @@ add wave -noupdate -radix hexadecimal /testbench/dut/uncore/dtim/HADDR
add wave -noupdate /testbench/dut/uncore/dtim/RAM add wave -noupdate /testbench/dut/uncore/dtim/RAM
add wave -noupdate /testbench/dut/uncore/dtim/HREADTim add wave -noupdate /testbench/dut/uncore/dtim/HREADTim
add wave -noupdate /testbench/dut/uncore/dtim/HREADTim0 add wave -noupdate /testbench/dut/uncore/dtim/HREADTim0
add wave -noupdate /testbench/dut/uncore/dtim/HRESETn
TreeUpdate [SetDefaultTree] TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 7} {15047768 ns} 0} {{Cursor 2} {34763538 ns} 0} {{Cursor 3} {15046271 ns} 0} {{Cursor 4} {15047307 ns} 0} WaveRestoreCursors {{Cursor 7} {10896277 ns} 1} {{Cursor 9} {10896453 ns} 0} {{wrong instruction} {10895117 ns} 0}
quietly wave cursor active 1 quietly wave cursor active 3
configure wave -namecolwidth 250 configure wave -namecolwidth 250
configure wave -valuecolwidth 229 configure wave -valuecolwidth 229
configure wave -justifyvalue left configure wave -justifyvalue left
@ -234,4 +237,4 @@ configure wave -griddelta 40
configure wave -timeline 0 configure wave -timeline 0
configure wave -timelineunits ns configure wave -timelineunits ns
update update
WaveRestoreZoom {15047734 ns} {15047902 ns} WaveRestoreZoom {10895029 ns} {10895205 ns}

16
wally-pipelined/src/uncore/dtim.sv
View File

@ -37,6 +37,9 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
output logic HRESPTim, HREADYTim output logic HRESPTim, HREADYTim
); );
localparam integer MemStartAddr = BASE>>(1+`XLEN/32);
localparam integer MemEndAddr = (RANGE+BASE)>>1+(`XLEN/32);
logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)]; logic [`XLEN-1:0] RAM[BASE>>(1+`XLEN/32):(RANGE+BASE)>>1+(`XLEN/32)];
logic [31:0] HWADDR, A; logic [31:0] HWADDR, A;
logic [`XLEN-1:0] HREADTim0; logic [`XLEN-1:0] HREADTim0;
@ -48,6 +51,7 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
logic memread, memwrite; logic memread, memwrite;
logic [3:0] busycount; logic [3:0] busycount;
assign initTrans = HREADY & HSELTim & (HTRANS != 2'b00); assign initTrans = HREADY & HSELTim & (HTRANS != 2'b00);
// *** this seems like a weird way to use reset // *** this seems like a weird way to use reset
@ -82,12 +86,22 @@ module dtim #(parameter BASE=0, RANGE = 65535) (
assign risingHREADYTim = HREADYTim & ~prevHREADYTim; assign risingHREADYTim = HREADYTim & ~prevHREADYTim;
// Model memory read and write // Model memory read and write
/* -----\/----- EXCLUDED -----\/-----
integer index;
initial begin
for(index = MemStartAddr; index < MemEndAddr; index = index + 1) begin
RAM[index] <= {`XLEN{1'b0}};
end
end
-----/\----- EXCLUDED -----/\----- */
generate generate
if (`XLEN == 64) begin if (`XLEN == 64) begin
always_ff @(posedge HCLK) begin always_ff @(posedge HCLK) begin
HWADDR <= #1 A; HWADDR <= #1 A;
HREADTim0 <= #1 RAM[A[31:3]]; HREADTim0 <= #1 RAM[A[31:3]];
if (memwrite && risingHREADYTim) RAM[HWADDR[31:3]] <= #1 HWDATA; if (memwrite && risingHREADYTim) RAM[HWADDR[31:3]] <= #1 HWDATA;
end end
end else begin end else begin
always_ff @(posedge HCLK) begin always_ff @(posedge HCLK) begin

13
wally-pipelined/testbench/testbench-imperas.sv
View File

@ -386,17 +386,24 @@ string tests32i[] = {
InstrEName, InstrMName, InstrWName); InstrEName, InstrMName, InstrWName);
// initialize tests // initialize tests
localparam integer MemStartAddr = `TIMBASE>>(1+`XLEN/32);
localparam integer MemEndAddr = (`TIMRANGE+`TIMBASE)>>1+(`XLEN/32);
initial initial
begin begin
test = 0; test = 0;
totalerrors = 0; totalerrors = 0;
testadr = 0; testadr = 0;
// fill memory with defined values to reduce Xs in simulation // fill memory with defined values to reduce Xs in simulation
// Quick note the memory will need to be initialized. The C library does not
// guarantee the initialized reads. For example a strcmp can read 6 byte
// strings, but uses a load double to read them in. If the last 2 bytes are
// not initialized the compare results in an 'x' which propagates through
// the design.
if (`XLEN == 32) meminit = 32'hFEDC0123; if (`XLEN == 32) meminit = 32'hFEDC0123;
else meminit = 64'hFEDCBA9876543210; else meminit = 64'hFEDCBA9876543210;
for (i=0; i<=65535; i = i+1) begin for (i=MemStartAddr; i<MemEndAddr; i = i+1) begin
//dut.imem.RAM[i] = meminit; dut.uncore.dtim.RAM[i] = meminit;
// dut.uncore.RAM[i] = meminit;
end end
// read test vectors into memory // read test vectors into memory
memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"}; memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};