comment cleanup

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-01.S

@@ -36,7 +36,7 @@ WRITE_READ_CSR mie, 0xFFF
 // test 5.3.1.6 Interrupt enabling and priority tests 
 
 // Cause interrupt, ensuring that status.mie = 0 , status.mpie = 1, and status.mpp = 11 during trap handling 
-jal cause_m_soft_interrupt // *** only cause one interrupt because we just want to test the status stack
+jal cause_m_soft_interrupt /// only cause one interrupt because we just want to test the status stack
 
 li x28, 0x8
 csrc mstatus, x28 // set mstatus.MIE bit to 0. interrupts from M mode should not happen

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PIE-stack-s-01.S

@@ -40,7 +40,7 @@ WRITE_READ_CSR mideleg 0xFFFF // delegate all interrupts to S mode.
 GOTO_S_MODE
 
 // Cause interrupt, ensuring that status.sie = 0 , status.spie = 1, and status.spp = 1 during trap handling 
-jal cause_s_soft_interrupt // *** only cause one interrupt because we just want to test the status stack
+jal cause_s_soft_interrupt // only cause one interrupt because we just want to test the status stack
 
 li x28, 0x2
 csrc sstatus, x28 // set sstatus.SIE bit to 0. interrupts from S mode should not happen

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-PMP.S

@@ -57,7 +57,7 @@ test_cases:
 # Test 12.3.2.2.1 Config: Write known values and set PMP config according to table 12.4 in the *** riscv book, copied below
 
 # write pmpaddr regs. Each of these should output the value of the pmpaddr after being written.
- # *** change the pmpcfg and addr commands to the right number                                       # | Reg   | pmpaddr     | pmpcfg    | L | A     | X | W | R | Comments 		                |
+#                                          | Reg   | pmpaddr     | pmpcfg    | L | A     | X | W | R | Comments 		                |
 .8byte 0x0, 0x0FFFFFFF, write_pmpaddr_0  # | 0     | 0x0FFFFFFF  | 1F        | 0 | NAPOT | 0 | 1 | 1 | I/O 00000000-7FFFFFFF RW 		|
 .8byte 0x1, 0x20040000, write_pmpaddr_1  # | 1     | 0x20040000  | 00        | 0 | OFF   | 0 | 0 | 0 |    		                    |
 .8byte 0x2, 0x2004003F, write_pmpaddr_2  # | 2     | 0x2004003F  | 09        | 0 | TOR   | 0 | 0 | 1 | 80100000-801000FF R 		    |

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-TEST-LIB-64.h

@@ -116,7 +116,7 @@ cause_store_acc:
     ret
 
 cause_ecall:
-    // *** ASSUMES you have already gone to the mode you need to call this from.
+    // ASSUMES you have already gone to the mode you need to call this from.
     ecall
     ret
 
@@ -656,8 +656,6 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
 //   write_read_csr     : write to specified CSR                    : old CSR value, 0x2, depending on perms    : value written to CSR
 //   csr_r_access       : test read-only permissions on CSR         : 0xbad                                     : 0x2, then 0x11
 
-// *** TESTS TO ADD: execute inline, read unknown value out, read CSR unknown value, just read CSR value
-
 .macro WRITE64 ADDR VAL
     // attempt to write VAL to ADDR
     // Success outputs:
@@ -748,7 +746,6 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
 //      0x9: test called from S mode
 //      0xB: test called from M mode
 // they generally do not fault or cause issues as long as these modes are enabled 
-// *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not?
 
 .macro GOTO_M_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
     li a0, 2 // determine trap handler behavior (go to machine mode)
@@ -775,7 +772,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
 .endm
 
 // These tests change virtual memory settings, turning it on/off and changing between types.
-// They don't have outputs as any error with turning on virtual memory should reveal itself in the tests *** Consider changing this policy?
+// They don't have outputs as any error with turning on virtual memory should reveal itself in the tests
 
 .macro GOTO_BAREMETAL
     // Turn translation off
@@ -814,7 +811,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
     //      value read back out from CSR after writing
     // Fault outputs:
     //      The previous CSR value before write attempt
-    //      *** Most likely 0x2, the mcause for illegal instruction if we don't have write or read access
+    //      Most likely 0x2, the mcause for illegal instruction if we don't have write or read access
     li x30, 0xbad // load bad value to be overwritten by csrr
     li x29, \VAL\()
     csrw \CSR\(), x29
@@ -828,9 +825,9 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
     // verify that a csr is accessible to read but not to write
     // Success outputs:
     //      0x2, then
-    //      0x11 *** consider changing to something more meaningful
+    //      0x11
     // Fault outputs:
-    //      0xBAD *** consider changing this one as well. in general, do we need the branching if it hould cause an illegal instruction fault? 
+    //      0xBAD
     csrr x29, \CSR
     csrwi \CSR\(), 0xA // Attempt to write a 'random' value to the CSR
     csrr x30, \CSR
@@ -847,7 +844,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
 
 .macro EXECUTE_AT_ADDRESS ADDR
     // Execute the code already written to ADDR, returning the value in x7. 
-    // *** Note: this test itself doesn't write the code to ADDR because it might be callled at a point where we dont have write access to ADDR
+    // Note: this test itself doesn't write the code to ADDR because it might be callled at a point where we dont have write access to ADDR
     // Assumes the code modifies x7, usually to become 0x111. 
     // Sample code:  0x11100393 (li x7, 0x111), 0x00008067 (ret)
     // Success outputs:
@@ -893,7 +890,7 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
     //     Label for the location of the test that's about to take place
     // ------------------------------------------------------------------------------------------------------------------------------------
 
-.macro INIT_TEST_TABLE // *** Consider renaming this test. to what???
+.macro INIT_TEST_TABLE
 
 test_loop_setup:
     la x5, test_cases

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-misa-01.S

@@ -29,8 +29,8 @@ TRAP_HANDLER m
 
 // Test 5.3.2.2: Machine ISA register test
 
-// Misa is a specific case *** so I don't want to add a whole test case for reading nonzero but unkown value CSRs.
+// Misa is a specific case so I don't want to add a whole test case for reading nonzero but unkown value CSRs.
-csrr x30, misa // should not cause a fault in machine mode. *** not writing to output because MISA is different for different configs.
+csrr x30, misa // should not cause a fault in machine mode. not writing to output because MISA is different for different configs.
 li x7, 0x111 // success value for read of nonzero misa 
 bnez x30, misa_nonzero
 li x7, 0xbad // misa was zero, store bad value

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-mtvec-01.S

@@ -32,12 +32,12 @@ CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtva
 TRAP_HANDLER m, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
 
 li x28, 0x8
-csrs mstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
+csrs mstatus, x28 // set sstatus.MIE bit to 1
 WRITE_READ_CSR mie, 0xFFF
 
 // cause traps, ensuring that we DONT go through the vectored part of the trap handler
 
-jal cause_m_time_interrupt // *** only cause one interrupt because we just want to test the status stack
+jal cause_m_time_interrupt // only cause one interrupt because we just want to test the status stack
 
 END_TESTS
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-stvec-01.S

@@ -41,7 +41,7 @@ WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
 
 GOTO_S_MODE
 
-jal cause_s_soft_interrupt // *** only cause one interrupt since we just want to test the tvec csr
+jal cause_s_soft_interrupt // only cause one interrupt since we just want to test the tvec csr
 
 GOTO_M_MODE 
 

tests/wally-riscv-arch-test/riscv-test-suite/rv64i_m/privilege/src/WALLY-trap-01.S

@@ -31,7 +31,7 @@ TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
 
 li x28, 0x8
 csrs mstatus, x28 // set mstatus.MIE bit to 1
-WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
+WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources
 
 // test 5.3.1.4 Basic trap tests