Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main

wally-pipelined/config/rv32ic/wally-config.vh

@@ -50,7 +50,7 @@
 `define UARCH_SUPERSCALR 0
 `define UARCH_SINGLECYCLE 0
 `define MEM_DTIM 1
-`define MEM_DCACHE 1
+`define MEM_DCACHE 0
 `define MEM_IROM 1
 `define MEM_ICACHE 1
 `define MEM_VIRTMEM 0

wally-pipelined/src/ifu/ifu.sv

@@ -218,7 +218,7 @@ module ifu (
   assign LocalIfuBusAdr = SelUncachedAdr ? PCPFmmu : ICacheBusAdr;
   assign IfuBusAdr = ({{`PA_BITS-LOGWPL{1'b0}}, WordCount} << $clog2(`XLEN/8)) + LocalIfuBusAdr;
 
-  busfsm #(WordCountThreshold, LOGWPL)
+  busfsm #(WordCountThreshold, LOGWPL, `MEM_ICACHE)
   busfm(.clk, .reset, .IgnoreRequest,
 		.LsuRWM(2'b10), .DCacheFetchLine(ICacheFetchLine), .DCacheWriteLine(1'b0), 
 		.LsuBusAck(IfuBusAck),

wally-pipelined/src/lsu/busfsm.sv

@@ -27,7 +27,7 @@
 
 
 module busfsm #(parameter integer   WordCountThreshold,
-				parameter integer LOGWPL)
+				parameter integer LOGWPL, parameter logic CacheEnabled )
   (input logic clk,
    input logic 				 reset,
 
@@ -55,6 +55,7 @@ module busfsm #(parameter integer   WordCountThreshold,
   logic 			   CntReset;
   logic 			   WordCountFlag;
   logic [LOGWPL-1:0]   NextWordCount;
+  logic 			   UnCachedAccess;
   
 
   typedef enum {STATE_BUS_READY,
@@ -81,6 +82,8 @@ module busfsm #(parameter integer   WordCountThreshold,
   assign WordCountFlag = (WordCount == WordCountThreshold[LOGWPL-1:0]);
   assign CntEn = PreCntEn & LsuBusAck;
 
+  assign UnCachedAccess = ~CacheEnabled | ~CacheableM;
+
   always_ff @(posedge clk)
     if (reset)    BusCurrState <= #1 STATE_BUS_READY;
     else BusCurrState <= #1 BusNextState;  
@@ -88,8 +91,8 @@ module busfsm #(parameter integer   WordCountThreshold,
   always_comb begin
 	case(BusCurrState)
 	  STATE_BUS_READY:           if(IgnoreRequest)               BusNextState = STATE_BUS_READY;
-	                             else if(LsuRWM[0] & (~CacheableM | ~`MEM_DCACHE)) BusNextState = STATE_BUS_UNCACHED_WRITE;
+	                             else if(LsuRWM[0] & (UnCachedAccess)) BusNextState = STATE_BUS_UNCACHED_WRITE;
-		                         else if(LsuRWM[1] & (~CacheableM | ~`MEM_DCACHE)) BusNextState = STATE_BUS_UNCACHED_READ;
+		                         else if(LsuRWM[1] & (UnCachedAccess)) BusNextState = STATE_BUS_UNCACHED_READ;
 		                         else if(DCacheFetchLine)            BusNextState = STATE_BUS_FETCH;
 		                         else if(DCacheWriteLine)            BusNextState = STATE_BUS_WRITE;
                                  else                             BusNextState = STATE_BUS_READY;
@@ -113,27 +116,27 @@ module busfsm #(parameter integer   WordCountThreshold,
 
 
   assign CntReset = BusCurrState == STATE_BUS_READY;
-  assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((~CacheableM & (|LsuRWM)) | DCacheFetchLine | DCacheWriteLine)) |
+  assign BusStall = (BusCurrState == STATE_BUS_READY & ~IgnoreRequest & ((UnCachedAccess & (|LsuRWM)) | DCacheFetchLine | DCacheWriteLine)) |
 					(BusCurrState == STATE_BUS_UNCACHED_WRITE) |
 					(BusCurrState == STATE_BUS_UNCACHED_READ) |
 					(BusCurrState == STATE_BUS_FETCH)  |
 					(BusCurrState == STATE_BUS_WRITE);
   assign PreCntEn = BusCurrState == STATE_BUS_FETCH | BusCurrState == STATE_BUS_WRITE;
-  assign UnCachedLsuBusWrite = (BusCurrState == STATE_BUS_READY & ~CacheableM & (LsuRWM[0])) |
+  assign UnCachedLsuBusWrite = (BusCurrState == STATE_BUS_READY & UnCachedAccess & (LsuRWM[0])) |
 							   (BusCurrState == STATE_BUS_UNCACHED_WRITE);
   assign LsuBusWrite = UnCachedLsuBusWrite | (BusCurrState == STATE_BUS_WRITE);
 
-  assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & ~CacheableM & (|LsuRWM[1])) |
+  assign UnCachedLsuBusRead = (BusCurrState == STATE_BUS_READY & UnCachedAccess & (|LsuRWM[1])) |
 							  (BusCurrState == STATE_BUS_UNCACHED_READ);
   assign LsuBusRead = UnCachedLsuBusRead | (BusCurrState == STATE_BUS_FETCH) | (BusCurrState == STATE_BUS_READY & DCacheFetchLine);
 
   assign DCacheBusAck = (BusCurrState == STATE_BUS_FETCH & WordCountFlag & LsuBusAck) |
 						(BusCurrState == STATE_BUS_WRITE & WordCountFlag & LsuBusAck);
   assign BusCommittedM = BusCurrState != STATE_BUS_READY;
-  assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|LsuRWM & ~CacheableM)) |
+  assign SelUncachedAdr = (BusCurrState == STATE_BUS_READY & (|LsuRWM & UnCachedAccess)) |
 						  (BusCurrState == STATE_BUS_UNCACHED_READ |
 						   BusCurrState == STATE_BUS_UNCACHED_READ_DONE |
 						   BusCurrState == STATE_BUS_UNCACHED_WRITE |
 						   BusCurrState == STATE_BUS_UNCACHED_WRITE_DONE) |
-						  ~`MEM_DCACHE; // if no dcache always select uncachedadr.
+						  ~CacheEnabled; // if no dcache always select uncachedadr.
 endmodule

wally-pipelined/src/lsu/lsu.sv

@@ -273,8 +273,8 @@ module lsu
   // 2. cache `MEM_DCACHE
   // 3. wire pass-through
 
-  localparam integer   WORDSPERLINE = `MEM_DCACHE ? `DCACHE_BLOCKLENINBITS/`XLEN : `XLEN/8;
+  localparam integer   WORDSPERLINE = `MEM_DCACHE ? `DCACHE_BLOCKLENINBITS/`XLEN : 1;
-  localparam integer   LOGWPL = $clog2(WORDSPERLINE);
+  localparam integer   LOGWPL = `MEM_DCACHE ? $clog2(WORDSPERLINE) : 1;
   localparam integer   BLOCKLEN = `MEM_DCACHE ? `DCACHE_BLOCKLENINBITS : `XLEN;
   localparam integer   WordCountThreshold = `MEM_DCACHE ? WORDSPERLINE - 1 : 0;
 
@@ -384,7 +384,7 @@ module lsu
     else assign LsuBusSize = SelUncachedAdr ? LsuFunct3M : 3'b011;
   endgenerate;
 
-  busfsm #(WordCountThreshold, LOGWPL)
+  busfsm #(WordCountThreshold, LOGWPL, `MEM_DCACHE)
   busfsm(.clk, .reset, .IgnoreRequest, .LsuRWM, .DCacheFetchLine, .DCacheWriteLine,
 		 .LsuBusAck, .CPUBusy, .CacheableM, .BusStall, .LsuBusWrite, .LsuBusRead,
 		 .DCacheBusAck, .BusCommittedM, .SelUncachedAdr, .WordCount);

wally-pipelined/testbench/testbench.sv

@@ -365,6 +365,12 @@ module DCacheFlushFSM
    input logic start,
    output logic done);
 
+  genvar adr;
+
+  logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
+  
+  generate
+	if(`MEM_DCACHE) begin
 	  localparam integer numlines = testbench.dut.hart.lsu.dcache.dcache.NUMLINES;
 	  localparam integer numways = testbench.dut.hart.lsu.dcache.dcache.NUMWAYS;
 	  localparam integer blockbytelen = testbench.dut.hart.lsu.dcache.dcache.BLOCKBYTELEN;
@@ -382,11 +388,6 @@ module DCacheFlushFSM
 	  logic 			 CacheValid  [numways-1:0] [numlines-1:0] [numwords-1:0];
 	  logic 			 CacheDirty  [numways-1:0] [numlines-1:0] [numwords-1:0];
 	  logic [`PA_BITS-1:0] CacheAdr [numways-1:0] [numlines-1:0] [numwords-1:0];
-  genvar adr;
-
-  logic [`XLEN-1:0] ShadowRAM[`RAM_BASE>>(1+`XLEN/32):(`RAM_RANGE+`RAM_BASE)>>1+(`XLEN/32)];
-  
-  generate
       for(index = 0; index < numlines; index++) begin
 		for(way = 0; way < numways; way++) begin
 		  for(cacheWord = 0; cacheWord < numwords; cacheWord++) begin
@@ -408,7 +409,6 @@ module DCacheFlushFSM
 		  end
 		end
       end
-  endgenerate
 
 	  integer i, j, k;
 
@@ -428,6 +428,12 @@ module DCacheFlushFSM
 	  end
 
 	  
+	end
+  endgenerate
+
+
+  
+
   flop #(1) doneReg(.clk(clk),
 		    .d(start),
 		    .q(done));