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Updated fpga ILA constraints to match the new changes to the rtl.

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This commit is contained in:
Ross Thompson 2022-01-06 11:56:09 -06:00
parent 5a2ae561a7
commit 42623141cd
1 changed files with 7 additions and 7 deletions
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14
fpga/constraints/debug2.xdc
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@ -86,7 +86,7 @@ connect_debug_port u_ila_0/probe16 [get_nets [list {wallypipelinedsoc/uncore/sdc
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
set_property port_width 32 [get_debug_ports u_ila_0/probe17] set_property port_width 32 [get_debug_ports u_ila_0/probe17]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe17]
connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[0]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[1]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[2]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[3]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[4]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[5]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[6]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[7]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[8]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[9]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[10]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[11]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[12]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[13]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[14]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[15]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[16]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[17]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[18]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[19]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[20]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[21]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[22]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[23]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[24]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[25]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[26]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[27]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[28]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[29]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[30]} {wallypipelinedsoc/hart/lsu/dcache/dcache/cachefsm/CurrState[31]} ]] connect_debug_port u_ila_0/probe17 [get_nets [list {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[0]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[1]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[2]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[3]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[4]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[5]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[6]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[7]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[8]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[9]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[10]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[11]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[12]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[13]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[14]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[15]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[16]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[17]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[18]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[19]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[20]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[21]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[22]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[23]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[24]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[25]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[26]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[27]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[28]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[29]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[30]} {wallypipelinedsoc/hart/lsu/dcache.dcache/cachefsm/CurrState[31]} ]]
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
set_property port_width 64 [get_debug_ports u_ila_0/probe18] set_property port_width 64 [get_debug_ports u_ila_0/probe18]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe18]
@ -446,7 +446,7 @@ connect_debug_port u_ila_0/probe98 [get_nets [list wallypipelinedsoc/hart/hzu/Fl
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
set_property port_width 24 [get_debug_ports u_ila_0/probe99] set_property port_width 24 [get_debug_ports u_ila_0/probe99]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe99]
connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[0]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[1]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[2]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[3]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[4]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[5]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[6]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[7]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[8]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[9]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[10]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[11]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[12]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[13]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[14]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[15]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[16]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[17]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[18]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[19]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[20]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[21]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[22]} {wallypipelinedsoc/hart/ifu/icache/icache/cachefsm/CurrState[23]}]] connect_debug_port u_ila_0/probe99 [get_nets [list {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[0]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[1]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[2]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[3]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[4]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[5]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[6]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[7]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[8]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[9]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[10]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[11]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[12]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[13]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[14]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[15]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[16]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[17]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[18]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[19]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[20]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[21]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[22]} {wallypipelinedsoc/hart/ifu/icache.icache/cachefsm/CurrState[23]}]]
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
@ -535,27 +535,27 @@ connect_debug_port u_ila_0/probe115 [get_nets [list {wallypipelinedsoc/hart/priv
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe116] set_property port_width 1 [get_debug_ports u_ila_0/probe116]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe116] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe116]
connect_debug_port u_ila_0/probe116 [get_nets [list wallypipelinedsoc/hart/lsu/hptw/ITLBMissF]] connect_debug_port u_ila_0/probe116 [get_nets [list wallypipelinedsoc/hart/lsu/ITLBMissF]]
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe117] set_property port_width 1 [get_debug_ports u_ila_0/probe117]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe117] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe117]
connect_debug_port u_ila_0/probe117 [get_nets [list wallypipelinedsoc/hart/lsu/hptw/DTLBMissM]] connect_debug_port u_ila_0/probe117 [get_nets [list wallypipelinedsoc/hart/lsu/DTLBMissM]]
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe118] set_property port_width 1 [get_debug_ports u_ila_0/probe118]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe118] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe118]
connect_debug_port u_ila_0/probe118 [get_nets [list wallypipelinedsoc/hart/lsu/hptw/ITLBWriteF]] connect_debug_port u_ila_0/probe118 [get_nets [list wallypipelinedsoc/hart/lsu/ITLBWriteF]]
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
set_property port_width 1 [get_debug_ports u_ila_0/probe119] set_property port_width 1 [get_debug_ports u_ila_0/probe119]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe119] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe119]
connect_debug_port u_ila_0/probe119 [get_nets [list wallypipelinedsoc/hart/lsu/hptw/DTLBWriteM]] connect_debug_port u_ila_0/probe119 [get_nets [list wallypipelinedsoc/hart/lsu/DTLBWriteM]]
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe
set_property port_width 11 [get_debug_ports u_ila_0/probe120] set_property port_width 11 [get_debug_ports u_ila_0/probe120]
set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe120] set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe120]
connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM/hptw/WalkerState[0]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM/hptw/WalkerState[1]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM/hptw/WalkerState[2]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM/hptw/WalkerState[3]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM/hptw/WalkerState[4]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM/hptw/WalkerState[5]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM/hptw/WalkerState[6]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM/hptw/WalkerState[7]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM/hptw/WalkerState[8]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM/hptw/WalkerState[9]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM/hptw/WalkerState[10]}]] connect_debug_port u_ila_0/probe120 [get_nets [list {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[0]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[1]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[2]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[3]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[4]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[5]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[6]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[7]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[8]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[9]} {wallypipelinedsoc/hart/lsu/MEM_VIRTMEM.hptw/WalkerState[10]}]]
create_debug_port u_ila_0 probe create_debug_port u_ila_0 probe