diff --git a/.gitignore b/.gitignore
index 1e986c3bd..6e4868820 100644
--- a/.gitignore
+++ b/.gitignore
@@ -104,3 +104,5 @@ pipelined/config/rv64ic_noPriv
 pipelined/config/rv64ic_orig
 synthDC/Summary.csv
 pipelined/srt/exptestgen
+pipelined/srt/testgen
+pipelined/srt/qst2
diff --git a/pipelined/src/fpu/fpu.sv b/pipelined/src/fpu/fpu.sv
index b4b5a2e98..581d72408 100755
--- a/pipelined/src/fpu/fpu.sv
+++ b/pipelined/src/fpu/fpu.sv
@@ -237,6 +237,7 @@ module fpu (
    // select the result that may be written to the integer register - to IEU
    mux4  #(`XLEN)  IntResMux(CmpResE[`XLEN-1:0], FSrcXE[`XLEN-1:0], ClassResE[`XLEN-1:0], 
                CvtResE[`XLEN-1:0], FIntResSelE, FIntResE);
+   // *** DH 5/25/22: CvtRes will move to mem stage.  Premux in execute to save area, then make sure stalls are ok
 
    // E/M pipe registers
 
diff --git a/pipelined/src/hazard/hazard.sv b/pipelined/src/hazard/hazard.sv
index 159ee10ec..cf4cdaa8b 100644
--- a/pipelined/src/hazard/hazard.sv
+++ b/pipelined/src/hazard/hazard.sv
@@ -65,7 +65,7 @@ module hazard(
   assign StallFCause = CSRWritePendingDEM & ~(TrapM | RetM | BPPredWrongE);
   // stall in decode if instruction is a load/mul/csr dependent on previous
   assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE);    
-  assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM);
+  assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM);  // *** can we move to decode stage (KP?)
   // WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled.  It could also terminate with TW trap
   assign StallMCause = wfiM & (~TrapM & ~IntPendingM);  
   assign StallWCause = LSUStallM | IFUStallF;
diff --git a/pipelined/src/ieu/comparator.sv b/pipelined/src/ieu/comparator.sv
index cc2eb1723..61a17ad9f 100644
--- a/pipelined/src/ieu/comparator.sv
+++ b/pipelined/src/ieu/comparator.sv
@@ -30,6 +30,15 @@
 
 `include "wally-config.vh"
 
+module donedet #(parameter WIDTH=64) (
+  input  logic [WIDTH-1:0] a, b,
+  output logic        eq);
+
+  //assign eq = (a+b == 0); // gives good speed but 3x necessary area
+  // See CMOS VLSI Design 4th Ed. p. 463 K = A+B for K = 0
+  assign eq = ((a ^ b) == {a[WIDTH-2:0], 1'b0} | {b[WIDTH-2:0], 1'b0});
+ endmodule
+
 module comparator_sub #(parameter WIDTH=64) (
   input  logic [WIDTH-1:0] a, b,
   output logic [2:0]       flags);
diff --git a/pipelined/srt/Makefile b/pipelined/srt/Makefile
index 73a0b75fa..67fbd892c 100644
--- a/pipelined/srt/Makefile
+++ b/pipelined/srt/Makefile
@@ -1,7 +1,10 @@
-all: sqrttestgen testgen
+all: sqrttestgen testgen qst2
 
 sqrttestgen: sqrttestgen.c
 	gcc sqrttestgen.c -lm -o sqrttestgen
-	
+
 testgen: testgen.c
 	gcc testgen.c -lm -o testgen
+
+qst2: qst2.c
+	gcc qst2.c -lm -o qst2
diff --git a/pipelined/srt/testgen b/pipelined/srt/testgen
deleted file mode 100755
index bb01f81bc..000000000
Binary files a/pipelined/srt/testgen and /dev/null differ